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  • Ec0033-Asic Design-Model Qp-Vii Sem-Set2

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    This document is about an exam for an ASIC Design course. It contains two parts - Part A with 10 short answer questions worth 2 marks each (total 20 marks), and Part B with 5 long answer questions worth 16 marks each (total 80 marks). Some sample questions are about sizing logic gates, designing logic gates using transmission gates, explaining logic expanders and BIST architecture components, types of memory synthesis approaches, objectives of partitioning, and goal of global routing. It also provides two figures related to questions on minimum cut cost calculation using KL algorithm and test vector generation for SA0 fault detection.

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    This document is about an exam for an ASIC Design course. It contains two parts - Part A with 10 short answer questions worth 2 marks each (total 20 marks), and Part B with 5 long answer questions worth 16 marks each (total 80 marks). Some sample questions are about sizing logic gates, designing logic gates using transmission gates, explaining logic expanders and BIST architecture components, types of memory synthesis approaches, objectives of partitioning, and goal of global routing. It also provides two figures related to questions on minimum cut cost calculation using KL algorithm and test vector generation for SA0 fault detection.

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    13 views1 page

    Ec0033-Asic Design-Model Qp-Vii Sem-Set2

    Uploaded by

    skarthikpriya
    This document is about an exam for an ASIC Design course. It contains two parts - Part A with 10 short answer questions worth 2 marks each (total 20 marks), and Part B with 5 long answer questions worth 16 marks each (total 80 marks). Some sample questions are about sizing logic gates, designing logic gates using transmission gates, explaining logic expanders and BIST architecture components, types of memory synthesis approaches, objectives of partitioning, and goal of global routing. It also provides two figures related to questions on minimum cut cost calculation using KL algorithm and test vector generation for SA0 fault detection.

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    of 1

    Reg. No.

    D algorithm
    SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (OR)
    Model Exam – Oct - 2019 b. What is fault modeling? Explain various types of faults.
    Seventh Semester – Department of Electronics and Communication
    Engineering 15 a. Apply KL algorithm for figure2 and find the minimum cut cost
    asuume edge cost as 1
    PEC0033 – ASIC Design (OR)
    Duration: 3 Hrs Max. Marks: 100 b. With an example explain left edge channel routing algorithm and Lee
    PART – A (10 X 2 = 20 Marks) maze routing
    Answer ALL Questions

    1. Size a 3 input NAND gate to achieve equal rise time and fall time
    2. Design a XNOR gate using Transmission gates
    3. Explain logic expander in Altera Max architecture
    4. Draw a ONO and MIM Antifuse
    5. List different types of Memory synthesis approach
    6. What is logic optimization?
    7. Draw the BIST Architecture and list various components associated.
    8. Find the test vector for SA1 at the output of 2 input NOR gate
    9. What are the objectives of partitioning?
    10. What is the goal of global routing
    Figure1

    PART – B (5 X 16= 80 Marks)


    Answer ALL questions

    11. a. Explain the various steps involved in ASIC Design


    (OR)
    b. Draw OAI321 and AOI22 logic cells and size it.

    12. a. Draw and explain the features of XILINX XC5200 architecture


    (OR)
    b. Explain the features of ACTEL ACT interconnects

    13 a. Illustrate various approaches of FSM synthesis


    (OR) Figure2
    b. Write short notes on various modes of simulation

    14 a. Determine the Test vector for SA0 fault shown below in figure1
    using

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