Panashe Mushinyi

H180524V
SE Department
Microprocessor and embeded systems assignment 1 and 2

ASSIGNMENT 1.

Question (a).[MAXIMUM MODE]

  In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
  In this mode, the processor derives the status signal S2, S1, S0.Another chip called bus
controller derives the control signal usingthis status information .
  In the maximum mode, there may be more than onemicroprocessor in the system
configuration. The components inthe system are same as in the minimum mode system.
  The basic function of the bus controller chip IC8288, is to derivecontrol signals like RD
and WR ( for memory and I/O devices),DEN, DT/R, ALE etc. using the information by the
processor on thestatus lines.
 The bus controller chip has input lines S2, S1, S0 and CLK.These inputs to 8288 are driven
by CPU.
  It derives the outputs ALE, DEN, DT/R, MRDC, MWTC,AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
  AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance
of the MCE/PDEN output depends upon the status of the IOB pin.INTA pin used to issue
two interrupt acknowledge pulses to theinterrupt controller or to an interrupting device.
 IORC, IOWC are I/O read command and I/O write command signals respectively . These
signals enable an IO interface to reador write the data from or to the address port.
  The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used asmemory read or write signals.
  All these command signals instructs the memory to accept or send data from or to the
bus.

Question(b).
MAXIMUM
The 8086 is operated by strapping the MN/MX
pin to ground
The processor derives the status signal S2, S1,
S0. Another chip called bus controller derives
the control signal using this status information
More than one microprocessor.
MINIMUM
The 8086 is operated by strapping MN/MX pin
to logic 1
All the control signals are given out by the
microprocessor chip
.Single microprocessor in the minimum mode
 system
Memory Read Timing Memory Write Timing
The components in the system are same as in the The remaining components in the system are
minimum mode system. latches,
transreceivers, clock generator, memory and I/O
devices.

Question (c).There are 258 interrupts in 8086 microprocessor.(hardware-2 and software-256)

SOFTWARE INTERRUPTS
 (A) TYPE 0 corresponds to division by zero(0).
 (B) TYPE 1 is used for single step execution for debugging of program.
 (C) TYPE 2 represents NMI and is used in power failure conditions.
 (D) TYPE 3 represents a break-point interrupt.
 (E) TYPE 4 is the overflow interrupt.

Question(d).[MINIMUM MODE]
•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1.
•In this mode, all the control signals are given out by the microprocessor chip itself. There is a
single microprocessor in the minimum mode system.
•The remaining components in the system are latches, transreceivers, clock generator, memory and
I/O devices.Some type of chip selection logic may be required for selecting memory or I/O devices,
depending upon the address map of the system.
•Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for
separating the valid address from the multiplexed address/data signals and are controlled by the
ALE signal generated by 8086.
•Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They
are required to separate the valid data from the time multiplexed address/data signals.
•They are controlled by two signals namely, DEN and DT/R.
•The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains
memory for the monitor and users program storage.
•Usually, EPROMs are used for monitor storage, while RAM for users program storage. A system
may contain I/O devices.

Question(e).

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded to
generate all the bus control signals. The minimum mode is selected by applying logic 1 to the
MN/MX input lead. It is typically used for smaller single microprocessor systems.The maximum
mode is selected by applying logic 0 to the MN/MX input lead. It is typically used for larger
multiple microprocessor systems.Depending on the mode of operation selected, the assignments for
a number of the pins on the microprocessor package are changed. The pin functions specified in
parentheses pertain to the maximum-mode.In minimum mode, the 8086 itself provides all the
control signals needed to implement the memory and I/O interfaces. In maximum-mode, a separate
chip (the 8288 Bus Controller) is used to help in sending control signals over the shared bus shown
in figure.
Question (f).
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance the
speed of execution of the computer system, so that the processor is able to fetch and execute the
data from the memory easily and fast.
Advantages of memory segmentation:
1. Segmentation provides a powerful memory management mechanism.
2. It allows programmers to partition their programs into modules that operate independently of
one another.
3. Segments allow two processes to easily share data.
4. It allows to extend the address ability of a processor i.e. segmentation allows the use of 16
bit registers to give an addressing capability of 1 MB. Without segmentation, it would
require 20 bit registers.
5. Segmentation makes it possible to separate the memory areas for stack, code and data.
6. It is possible to increase the memory size of code data or stack segments beyond 64 KB by
allotting more than one segment for each area.

Question(g).
pipeline in 8086 is a technique which is used in advanced microprocessors, where the
microprocessor execute a second instruction before the completion of first. That is many
instructions are simultaneously pipelined at different processing stages.Pipelining has become
possible due to the use of queue.BIU (Bus Interfacing Unit) fills in the queue until the entire queue
is full.BIU restarts filling in the queue when at least two locations of queue are vacant.

The advantages of pipelining is performance improvement, we are able to pump more instructions
and get improved in processor speed as we are able to execute parts of instructions in parallel to
parts of other instruction.The execution unit always reads the next instruction byte from the queue
in BIU. This is faster than sending out an address to the memory and waiting for the next instruction
byte to come.

Disadvantage of pipeline is that it makes things complex, for example if we need to take care of
branch penalty and forwarding, this become complex and several research problems are arise due to
these complexity.
ASSIGNMENT 2.

Question(a).
What is it.
8257 DMA stands for 4-channel Direct Memory Access. It is specially designed by Intel for data
transfer at the highest speed. Its initial function is to generate a peripheral request which allows the
device to transfer the data directly to/from memory without any interference of the CPU.
With the use of a DMA controller, the device sends requests to the CPU to hold its data, sequential
memory address and control bus, which helps the device to transfer data directly to/from the
memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

Functionality and Operations

 Primarily, when any device requires to send data between the device and the memory, the
device need to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA signal.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 when the CPU is in HOLD state with the HOLD request, the DMA controller has to control
the operations over buses between the CPU, memory, and I/O devices.
Features

 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes,Master mode and Slave mode
Question(b).

 Figure shows the internal block diagram of 8255A. It consists of data bus buffer, control
logic and Group A and Group B controls.
 Data Bus Buffer: This tri-state bi-directional buffer is used to interface the internal data lilts
of 8255 to the system data bus. Input or Output instructions executed by the CPU either
Read date from or Write data into the buffer. Output data from the CPU to the ports or
control register, and input data to the CPU from the ports or status register are all passed
through the buffer.
 Control Logic: The control logic block accepts control bus signals as well as inputs from the
address bus, and issues commands to the individual group control blocks (Group A control
and Group B control). It issues appropriate enabling signals to access the required
data/control words or status word. The input pins for the control logic section are described
here. Group A and Group B Controls: Each of the Group A and Group B control blocks
receives control words from the CPU and issues appropriate commands to the ports
associated with it. The Group A control block controls Port A and PC_7-PC_4 while the
Group B control block controls Port B and PC_3-PC_0.
 Port A: This has an 8-bit latched and buffered output and an 8-bit input latch. It can be
programmed in three modes: mode 0, mode 1 and mode 2.
  Port B: This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be
programmed in mode 0 and mode 1.
 Port C: This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C can
be spitted into two parts and each can be used as control signals for ports A and B in the
handshake mode. It can be programmed for bit set/reset operation.
Control word
Control word is defined as a word whose individual bits represent the various control signal.
Therefore each of the control steps in the control sequence of an instruction defines a unique
combination of 0s and 1s in the CW. The control words related to an instructions are stored in
microprogram memory.It is a set of micro-instructions in a micro-routine. It is used in control data
register in any instruction cycle.
It consists of:
 branch conditions
 flags
 control signal field
 next microinstruction field
control data register size = size of control word