Que -classification of memory array ?

QUE*** - EXPLAIN SRAM? DEFINE ITS R/D OPERATION ?

**SHOW RD/WR OPERTION IN MEMORY CELL ?
NEED OF LARGE SRAM ?ALSO DRAW ITS LARGE MEMoRY
Architecture

https://courses.cs.washington.edu/courses/cse467/11wi/lectures/Memori
es.pdf
*Static Random Access Memory (SRAM) is a type of semiconductor memory.
* It is static and volatile, implying data retention persists for as long as the device
is powered without any form of a refresh, however, once the power is cut, data
will be lost.
* It is random access, meaning the next memory location that can be read or
written to does not depend on the last access location. *The static property of
SRAM comes from its use of some sort of a feedback mechanism to maintain the
stored bit state. This is in contrast to other forms of memory, such as Dynamic
RAM, where the stored state of the bit is kept in the form of a charge that leaks
over time thereby requiring the data to be refreshed (i.e, read and re-written
back).
*Large blocks of SRAM memory comprise of arrays of individual SRAM blocks
called cells . An SRAM cell is capable of storing a single bit of data for as long as
there is power. Likewise, an array of eight SRAM cells can store 1 byte of data.
Arrays of SRAM form the foundation for every
Semiconductor & Computer Engineering

Applications[edit]

Due to its relative simplicity, SRAM is the most common memory cell found in
modern microprocessors. It is used for various large buffers and caches. Current
SoCs allocate a large portion of the die to SRAM. For example, in Intel's first-
generation Atom processors, codename Bonnell,

Operation[edit]

* Static RAMs use basic memory cells with built-in feedback mechanisms that retain
the stored value for as long as the device is powered. A basic example of a feedback
mechanism is a pair of inverters that are cross-coupled such that the output of
one inverter becomes the input of the other inverter.

As long as there is power, the stored value will be continuously reinforced by the
positive feedback loop which also helps correct for leakage and noise.

*Writing a new bit value involves driving the desired value and its complement onto
the input and output of the cross-coupled inverters. By driving a stronger new value
and overpowering the older values, a new bit value may be stored in the cell.
Reading the stored value involves reading the output of the cell. Note that in practice,
due to the size of the transistors involved which makes them very weak, driving the
output directly from the bitcell is very challenging. Instead, a sense amplifier  is used
to generate a strong output from the attenuated bit value .

Bit Cells[edit]

*The SRAM bitcell is the basic building block of SRAM memory.

*A cell holds a single bit value for as long as there is power. The two access points to
the cell are known as  bitlines  (BL). The bitlines comprise of the stored bit value and
its complement. Two access transistors sit on the bitlines in order to enable and
disable access to the stored data for reading and writing operations. The signal that
controls the access transistors is referred to as a wordline  (WL).

6T Cell[edit]

The most common implementation of an SRAM bitcell is the 6-transistor bitcell (6T

cell). This cell comprises a pair of weak cross-coupled CMOS inverters and a pair of
access transistors used for reading and writing the stored state.

* 6T cells can provide excellent noise margins and low leakage with relatively good
density. Because the transistors are very small and thus weak, more complex assist
circuits are required for reading and writing the cells.
4T Cell[edit]

A 4-transistor bitcell (4T cell) is a modified version of the 6T cell with the

two PMOS pull-up transistors removed. This design sacrifices static power dissipation
in favor of higher density. In this configuration, the two PMOS transistors are replaced
with denser high resistance resistors.

8T Cell[edit]

An 8-transistor bitcell (8T cell) is an enhanced version of the 6T cell which

decouples the read port from the write por t. A new read buffer comprising 2 nMOS
transistors is added to the 6T cell.
This has a number of performance advantages. By decoupling the read from write,
the read SNM is drastically reduced. Additionally, both the read and write
performance can be optimized individually by adjusting the 6T cell part separately
from the read buffer size. In other words, the decoupled read buffer permits lower
write voltages while enabling higher read currents.

**SRAM memory cell operation

* The operation of the SRAM memory cell is relatively straightforward. When the cell is
selected, the value to be written is stored in the cross-coupled flip-flops. The cells are
arranged in a matrix, with each cell individually addressable. Most SRAM memories
select an entire row of cells at a time, and read out the contents of all the cells in the row
along the column lines.

. The two bit lines are passed to two input ports on a comparator to enable the
advantages of the differential data mode to be accessed, and the small voltage swings
that are present can be more accurately detected.
Access to the SRAM memory cell is enabled by the Word Line. This controls the two
access control transistors which control whether the cell should be connected to the bit
lines.

These two lines are used to transfer data for both read and write operations.SRAM
memory applications

As a result of these parameters, SRAM memory is used where speed or low power are
considerations. Its higher density and less complicated structure also lend it to use in
semiconductor memory scenarios where high capacity memory is used, as in the case of
the working memory within computers.

SRAM operation (NOTES COPY )

https://www.youtube.com/watch?v=k5VBJcUcaWU&list=PLfP-
D1tg0DI2Sn1DVzGdIeGyuIUjhJ9zp&index=7
An SRAM cell has three different states: standby (the circuit is idle), reading (the data
has been requested) or writing (updating the contents). SRAM operating in read mode
and write modes should have "readability" and "write stability", respectively. The three
different states work as follows:
Standby/hold[edit]
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from
the bit lines. The two cross-coupled inverters formed by M1 – M4 will continue to reinforce
each other as long as they are connected to the supply.
Reading[edit]

SRM 6T- operation

In theory, reading only requires asserting the word line WL and reading the SRAM cell
state by a single access transistor and bit line, e.g. M6, BL. However, bit lines are
relatively long and have large parasitic capacitance. To speed up reading, a more
complex process is used in practice: The read cycle is started by precharging both bit
lines BL and BL, to high (logic 1) voltage. Then asserting the word line WL enables both
the access transistors M5 and M6, which causes one bit line BL voltage to slightly drop.
Then the BL and BL lines will have a small voltage difference between them. A sense
amplifier will sense which line has the higher voltage and thus determine whether there
was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read
operation. As the NMOS is more powerful, the pull-down is easier. Therefore, bit lines are
traditionally precharged to high voltage. Many researchers are also trying to precharge at
a slightly low voltage to reduce the power consumption. [16][17]
Writing[edit]
The write cycle begins by applying the value to be written to the bit lines. If we wish to
write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is
similar to applying a reset pulse to an SR-latch, which causes the flip flop to change
state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the
value that is to be stored is latched in. This works because the bit line input-drivers are
designed to be much stronger than the relatively weak transistors in the cell itself so they
can easily override the previous state of the cross-coupled inverters. In practice, access
NMOS transistors M5 and M6 have to be stronger than either bottom NMOS (M1, M3) or top
PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are much weaker
than NMOS when same sized. Consequently, when one transistor pair (e.g. M3 and M4) is
only slightly overridden by the write process, the opposite transistors pair (M 1 and M2)
gate voltage is also changed. This means that the M1 and M2 transistors can be easier
overridden, and so on. Thus, cross-coupled inverters magnify the writing process.

QUE** : EXPLAIN SEQUENCING STATIC CIRCUIT ?EXPLAIN THE

METHOD OF STATIC SEQUENCING ?
Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking

Sequential logic –  output depends on current and previous inputs

–  Requires FLIPS FLOPS OR LATCHES (MEMORY ELEMENT )=
hold the data calledas state or tokens
 –  Ex: FSM, pipeline
 

-Use flip-flops to delay fast tokens so they move through exactly one
stage each cycle.
- Inevitably adds some delay to the slow tokens
- Makes circuit slower than just the logic delay – Called sequencing
overhead
http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect11.pdf :time dalay
http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect11.pdf ;design of
latch n f/f

QUE** : CONTENT ADDRESSABLE MEMORY (CAM)/assocaitive

memory AND ITS APPLICATION
1CAM applications include:Content-addressable memory is often used in computer
networking devices. For example, when a network switch receives a data frame from one
of its ports, it updates an internal table with the frame's source MAC address and the port
it was received on. It then looks up the destination MAC address in the table to determine
what port the frame needs to be forwarded to, and sends it out on that port. The MAC
address table is usually implemented with a binary CAM so the destination port can be
found very quickly, reducing the switch's latency.
2Ternary CAMs are often used in network routers, where each address has two parts:
the network prefix, which can vary in size depending on the subnet configuration, and the
host address, which occupies the remaining bits.
3 Other CAM applications include:
* CPU fully associative cache controllers and translation lookaside buffers (TLB)

 Database engines
 Data compression hardware
 Artificial neural networks[9]
 Intrusion prevention system
 Several custom computers, like the Goodyear STARAN, were built to implement
CAM.

QUE**: a) MAX- DALAY CONSTARINTS

b) min - delay constraints

QUE: WHAT IS DRAM ? DRAW ITS SUB-ARRAY ARCHITECTURE.

Data bits stored on a capacitor Called dynamic because the
value needs to be refreshed (rewritten) periodically and after being
read: – Charge leakage from the capacitor degrades the value –
Reading destroys the stored value