Design in Hazard states

K.B. Gan
Electrical & Electronic Program
Universiti Kebangsaan Malaysia

1
Learning Outcome
• Gate delays
• Timing waveforms
• Static/dynamic hazards and glitches
• Designs to avoid hazards
• Identify
• Eliminate
• Algebra of Hazards

2
Time Response in Combinational
Networks
• emphasis on timing behavior of circuits

• waveforms to visualize what is happening

• simulation to create these waveforms

• momentary change of signals at the outputs: hazards

can be useful— pulse shaping circuits
can be a problem — glitches: incorrect circuit operation
Terms:
gate delay— time for change at input to cause change at output
minimum delay vs. typical/nominal delay vs. maximum delay
careful designers design for the worst case!

rise time— time for output to transition from low to high voltage

fall time— time for output to transition from high to low voltage

3
Concepts of Delays and Timing
• Logic gates do not produce an output
simultaneously with a change in input.
• There is a finite propagation delay through all gates.

input output

input

output
time

propagation delay

4
 Gate Delays
• Why is there a gate delay?
• There are actual resistances and capacitances
inside digital logic
• If you apply a unit step voltage signal to an input,
the output will not respond immediately, but after
a delay proportional to R.C
T delay = R.C Resistance of driver

Capacitance
Input Output
of load
5
 Delays in Combinational Logic

Input
transition Output
transition

QUESTION: After the input goes from low to high how

long does it take for the output to go from low to high
(note depends on other inputs being 1 or 0)

ANSWER: Use simple delay models for each gate and

add up delays in a path from input to output
6
Delays in Combinational Logic
Low drive

Delay (nsec)
High drive
Wire load
Capacitance C

Load capacitance
(pF)

7
 Designing Logic With High Performance
Reduce high load due to fanout

Higher drive gate

Input
transition

QUESTION: Suppose the delay from input to output is 30 nsec and

is unacceptable. How would you make a higher performance
design?
ANSWER: Reduce capacitances at various loads, or use higher
drive gates
8
Propagation Delay in Combinational
Circuits
• Propagation Delay
• Physical characteristics of a logic circuit to be considered:
• Propagation delays
• Gate fan-in and fan-out restrictions
• Power consumption
• Size and weight

• Propagation delay: The delay between the time of an input

change and the corresponding output change.
• Typical two propagation delay parameters:
• tPLH = propagation delay time, low-to-high-level output
• tPHL = propagation delay time, high-to-low-level output
• Approximation:
• t PD = t PLH + t PHL
2
Chapter 2 9
Propagation Delay in Combinational
Circuits
• Propagation delay through a logic gate

b
a
c
b c

(a) Two-input AND gate (b) Ideal (zero) delay

a a

b b

c c
tPD tPD tPLH tPHL
(c)tPD = tPLH= tPHL (d)tPLH< tPHL

Chapter 2 10
Gate Delay Specifications
• Power dissipation and propagation delays for
several logic families

Logic Propagation Delay Power Dissipation

Family tPD(ns) Per Gate (mW) Technology
7400 10 10 Standard TTL
74H00 6 22 High-speed TTL
74L00 33 1 Low-power TTL
74LS00 9.5 2 Low-power Schottky TTL
74S00 3 19 Schottky TTL
74ALS00 3.5 1.3 Advanced low-power
Schottky TTL
74AS00 3 8 Advanced Schottky TTL
74HC00 8 0.17 High-speed CMOS

Chapter 2 11
Gate Delays for Typical TTL Families
• Propagation delays of primitive 74LS series gates

tPLH tPHL
Chip Function Typical Maximum Typical Maximum
74LS04 NOT 9 15 10 15
74LS00 NAND 9 15 10 15
74LS02 NOR 10 15 10 15
74LS08 AND 8 15 10 20
22
74LS32 OR 14 22 14 22

Chapter 2 12
Specifying Delays
• Inertial Delay Model
• reflects physical inertia of physical systems
• glitches of very small duration not reflected in outputs
• SIG_OUT <= not SIG_IN after 7 nsec
• Logic gates exhibit lowpass filtering

10ns 3 ns
SIG_IN

2ns
SIG_OUT

9 ns 19 ns

13
Transport Delays
• Under this model, ALL input signal changes are
reflected at the output
• SIG_OUT <= transport not SIG_IN after 7 ns;

10ns 3 ns
SIG_IN

2ns
SIG_OUT

9 ns 19 ns 30 ns

14
Pulse Shaping Circuit
A B C D
F
100
A
B
C
D
F

D remains high for F is not always 0, pulse width equals

three gate delays after 3 gate delays
A changes from low to high

15
Another Pulse Shaping Circuit
+
Resistor
A B
Open C D
Switch

Close Switch Open Switch

Initially undefined

A
B
C
D

16
Hazards and Glitches
Hazard is a momentary unwanted switching transient at a logic
function’s output (i.e. a glitch).

There are two types of hazards; static and dynamic

Occur because delay paths through the circuit experience different

propagation delays

Danger if logic "makes a decision" while output is unstable OR hazard

output controls an asynchronous input (these respond immediately to
changes rather than waiting for a synchronizing signal called a clock)

Usual solutions:
wait until signals are stable (by using a clock)

never, never, never use circuits with asynchronous inputs

design hazard-free circuits

17
Static Hazards
• Static‐0 Hazard:
• Occurs when output is 0 and should remain at 0, but
temporarily switches to a 1 due to a change in an input.
• Static-1 Hazard:
• Occurs when output is 1 and should remain at 1, but
temporarily switches to a 0 due to a change in an input.

18
Static Hazards
• Due to a literal and its complement momentarily taking
on the same value
• Thru different paths with different delays and reconverging
• May cause an output that should have stayed at the
same value to momentarily take on the wrong value
• Example A

A B
S
F
S

S'
B
F
S' hazard
static-0 hazard static-1 hazard
19
Dynamic Hazards
• Dynamic Hazard:
• Occurs when an input changes, and a circuit output
should change 0 -‐> 1 or 1 -‐> 0, but temporarily flips
between values.

20
Dynamic Hazards
• Due to the same versions of a literal taking on opposite
values
• Thru different paths with different delays and reconverging
• May cause an output that was to change value to
change 3 times instead of once
• Example:
A

C
A
F B1
3
B 2
B2
1
B3
C
F

hazard
dynamic hazards 21
Detecting Static 1-Hazards
We can detect hazards in a two-level AND-OR circuit using
the following procedure:

1. Write down the sum-of-products expression for the circuit.

2. Plot each term on the map and loop it.
3. If any two adjacent 1′s are not covered by the same loop, a 1-hazard
exists for the transition between the two 1′s. For an n-variable map,
this transition occurs when one variable changes and the other n – 1
variables are held constant.

22
Illustration
• Consider the following
circuit with delays where
only one input (input b)
changes…
• Draw a timing diagram to
see what happens at
output with delays.
• From the logic expression,
we see that b changing
should result in the output
remaining at logic level 1…
• Due to delay, the output
goes 1-‐>0-‐ >1 and this is
an output glitch; we see a
static-1 hazard.
23
Fixing Hazards (2‐level circuits)

24
Fixing Hazards (2-level circuits)

25
Fixing Hazards (2-level circuits)

• Hazard eliminated but f is no longer a minimum sum of

products
26
 Hazard Removal Result

° Addition of extra AND gate and extra OR gate input

° Generally does not slow down circuit
° Not as important for sequential circuits

27
Detecting Static 0-Hazards
We can detect hazards in a two-level OR-AND circuit using
the following procedure:

1. Write down the product-of-sums expression for the circuit.

2. Plot each sum term on the map and loop the zeros.
3. If any two adjacent 0′s are not covered by the same loop, a 0-hazard
exists for the transition between the two 0′s. For an n-variable map,
this transition occurs when one variable changes and the other n – 1
variables are held constant.

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Detecting Static 0-Hazards
Z=(A+C)(A’+C’)(B’+C’+D)

29
Removing Static 0-Hazards

How many redundant gates are necessary to remove the 0-hazards?

30
Algebra of Hazards

31
Algebra of Hazards

• If a circuit has a hazard, the equation of the circuit

will reduce to one of these forms.
Algebra of Hazards

• Example:
Algebra of Hazards

• Example:
35
Locating Hazards in Circuits Algebraically
Locating Hazards in Circuits Algebraically

• Equivalent graphical forms for AND, OR, NAND and

NOR, using DeMorgan’s theorem
Example
• Find All The Hazards In F.

38
Locating Hazards in Circuits Algebraically
Level 3 Level 1
Estimating which variables might
have hazards
• A hazard, has two paths which reconverge in an
AND or OR gate.
• One path must have an even number of inversions,
and the other path must have an odd number.
• One need only check for hazards in variables which
have such paths.

40
Checking a circuit for potentially
hazardous paths

41
Locating Hazards From the Circuit
Equation

42
Summary
• Gate delays
• Timing waveforms
• Static/dynamic hazards and glitches
• Hazards elimination
• Algebra of Hazards

43