The Programmable Solutions

Company

Programmable Logic
Devices
FPGA - LUT
Intellectual Property CPLD – p-term Development Software
SPLD – PAL & GAL

1
End Market Focus
Computer
Computer
Communications
Communications &
& Storage
Storage

Office
Wireless Networking Wireline Computer Storage Automation

Cellular Basestations Switches Optical Servers RAID Copiers

Wireless LAN Routers Metro Mainframe SAN Printers
Access Workstations MFP

Industrial
Industrial
Consumer
Consumer

Security/
Entertainment Broadcast Instrumentation Auto Military
Energy Mgmt.
Medical Card Readers Navigation Secure Comm.
Broadband Studio
Audio/Video Satellite Test Equipment Control Systems Entertainment Radar
Manufacturing ATM Guidance & Control
Video Display Broadcasting

2
PLD Market Forecast
6

5
Automotive
Military
4
rial
Billions $

u st
3 Ind t o rage
er & S
p u t
Com
2 Consumer

Communications
1

0
2002 2003 2004 2005 2006 2007

Source DataQuest Normalized CAGR

3
Altera’s PLD Product

Stratix 系列FPGA
Cyclone 系列FPGA
APEX 系列FPGA
ACEX 系列FPGA
FLEX 系列FPGA
MAX 系列CPLD
Altera 宏功能块及IP核

4
Altera’s Product Portfolio
Relative Cost

Next Generation

Relative Density & Features

5
Stratix Features
„ lower power consumption through Programmable Power Technology
− turn on when performance needed
− turn down the power consumption everywhere else
„ Selectable Core Voltage
„ the latest in silicon process
− 1.1-V, 65-nm all-layer copper SRAM process
„ High-speed DSP blocks
− 9×9,12×12, 18×18, 36×36 multipliers (up to 550 MHz), FIR filters, etc
„ Up to 12 phase-locked loops (PLLs)
„ High-speed external memory interfaces
− DDR,DDR2,DDR3 SDRAM, RLDRAM II, QDR II and QDR II+
„ High-speed differential I/O
− support serializer/deserializer(SERDES)
− Support dynamic phase alignment (DPA) circuitry
− 1.25 Gbps performance

6
 Price Trend
1.2
Price per LE Sold (Normalized to Q1 1993)

1
1.0
0.901
Price per Logic Element (LE)
0.8 Declines 25% to 35% per Year
0.6 0.578

0.4 0.354
0.261
0.17 0.144
0.2 0.132
0.086
0.069 0.055 0.046
0.042 0.037 0.031 0.029 0.023 0.018 0.015
0.013
0.0

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003

7
Cyclone: The Lowest-Cost FPGA Ever
„ Industry’s-First FPGA
Designed from the
Ground Up for Low
Cost
„ Low Price Without
Compromise
„ Fastest Growing Night Vision Camera by Intevac
Family Ever

8
Examples Where Cyclone Is Used

9
Filling in the Price Gap
Relative Unit Price

FPGAs

“The Gap”

HardCopy
ASICs

Relative Density

10
Case Study: HardCopy - Building The
Seamless Structured ASIC

Seamless Transition

Up to 90%
Price
Reduction

ƒ Flexibility to Change Designs ƒ Get Seamless Migration with

During Prototype Phase Quick Turnaround
ƒ Prove Out System Functionality ƒ System Re-Qualification Not
ƒ Get Fast Time-to-Market with Needed
FPGA

11
HardCopy Stratix Benefits

ASIC

Comparison ASIC HardCopy

EDA Tool Cost $200K $2K
NRE/Masks/Prototypes $700K $200K
Time to First Units 14 Months 6 + 2 Months

How Do You Want

to Spend Your Resources?

12
 DTV Encoder Non Altera Altera Functional Block Altera Devices
Altera IP Solutions
Memory Additional Resources
Video Pre-processing TS Block

Packetizer
Color •
Image Video
Space
Equalizer

Capture Encoder
Cable Equalizer

Converter

Video Processor
Processor
SDI Processor • II II

ASI Output Processor

…
…
HD-SDI

Post Processor
Video Memory • 8b10b Encoder/Decoder

HD SPTS
..
Multiplex

ASI Output
Input
SDI Cable

Color

Packetizer
Image Video • II II
Space
SDI

Capture Encoder
Converter
SDI

• Color Space Converter

VBI Processor • Complex Tuner
• FIR Compiler
Ancillary • Motion JPEG Encoder,
Data CODEC
Input
Control
II • II
Audio Audio
Audio
Input Encoder
Encoder Application Notes
• AN130: CDR in Mercury Devices
• AN203: Using TriMatrix Embedded

ASI Output Processor

Memory Blocks in Stratix and
Stratix GX Devices
Equalizer
Cable Equalizer

• AN224: High-Speed Board Layout

SD SPTS
Multiplex

ASI Output
Processor

Guidelines
SDI Processor

Video Pre-processing
Color Packetizer • AN236: Using Source-Synchronous
Signaling with DPA in Stratix GX
SD-SDI Image Video
Video Space Devices
SDI Cable

Input Capture Encoder • AN237: Using High-Speed Trans-

Converter ceiver Blocks in Stratix GX Devices
SDI

Dev. Boards, Ref. Design and Others

VBI Processor Memory
SDI

• Stratix GX SPICE Models

Control • Test Chip Demo Board
TS Block • Test Chip Characterization Data
Glossary White Paper
ASI – Asynchronous Serial Interface SDI – Serial Digital video Interface • The Evolution of High Speed
HD – High Definition SPTS – Single Program Transport Stream Transceiver Technology
SD – Standard Definition VBI – Vertical Blanking Interval • Stratix GX in HDTV Video
Production Applications
13
 Process Control
Non Altera Bus Altera Devices
Altera Functional Block Altera IP Solutions
Host Ethernet Other Services Additional Resources
System PHY

10/100 Ethernet
MAC
• II II
•
• Nios Peripheral Library
Profibus • 10/100 Ethernet MAC
UART • CAN Bus
Controller

Flash I2C Bus

Memory 32-bit Application Notes
Processor Interface • AN125: Evaluating AMPP &
MegaCore Functions
EPROMS • AN188: Custom Instructions for the
Nios Embedded Processor
CAN • AN250: Configuring Cyclone Devices
Clock Controller & • AN251: Using PLL in Cyclone
Devices
Interface • AN252: On-Chip Memory Imple-
mentation Using Cyclone Memory
Block
• AN259: Implementing DSP
A/D Receiver Functions in Cyclone Devices
• AN260: Implementing Nios
Converter Module Embedded Processor in Lower-
Density FPGA
Dev. Boards and Reference Designs
• Nios Development Boards & Kits
Automation
Measurement
System
Device

14
Auto Software Radio Receiver
Non Altera Functional Block Altera Devices
Broadcast Signal Altera Sub System Altera IP Solutions
Other Services Additional Resources
Satellite, Terrestrial
• II
• FIR Compiler
Analog SDRAM /
• FFT/IFFT
Receiver SRAM Flash
• II
ADC • Max II
Software Radio Controller

Channel Processing RISC CPU & Auto Automotive • Nios Peripheral Library
Module Subsystems Gateway system • Constellation Compiler
Channel(s) • Can Bus
Selection • MCAN2D1 CAN 2.0
Decoder Module Waveform Module Network Controller
DAB Decoder Audio • Numerically Controlled
Channel (s) DAC Oscillator
Filtering Signal
• USB 2.0 Device
FM Diversity Processing Controller
Channel (s) Demodulator
Auto Audio Application Notes
Equalization System • AN188: Custom Instructions for the
…

Nios Embedded Processor

• AN259: Implementing DSP
Functions in Cyclone Devices
Other • AN260: Implementing Nios
Embedded Processor in Lower-
Decoders Density FPGA
Dev. Boards and Reference Designs
• AN181: Multi-Master Reference
Design and Design Files Excalibur
Solutions Pack
• Nios Development Boards & Kits
• Nios Ethernet Reference Design
Enhanced with DMA (Contact Nios
Team for Details)
15
iSCSI Line Card
Non Altera Altera Devices
RapidIO, HyperTransport or PCI-X Altera Altera IP Solutions
Other Services Additional Resources

Host •
Processor • 10G Ethernet MAC&PCS
Memory • Gigabit Ethernet MAC
Interface
1G/10G Ethernet • Infiniband Link Layer
• PCI-X Master/Target
Ethernet Core 32/64-Bit
Ethernet TCP/IP
O/E Layer 3/4 • RapidIO Physical Layer
PHY+MAC Offload MegaCore Function
Processing
•
II II
SNP Traffic

Backplane
•
Management
….

• Nios Peripheral Library

Multiple & • SOPC Builder
Ports Backplane Application Notes
Interface • AN188: Custom Instructions for the
Nios Embedded Processor
• AN203: Using TriMatrix Embedded
Memory Blocks in Stratix and Stratix
Memory Host Processor GX Devices
Interface • AN224: High-Speed Board Layout
Guidelines
• AN236: Using Source-Synchronous
Singaling with DPA in Stratix GX
Ethernet Devices
Ethernet TCP/IP • AN237: Using High-Speed Transceiver
O/E Layer 3/4 Blocks in Stratix GX Devices
PHY+MAC Offload
Processing • AN240: Simulating Excalibur Systems
• AN249: Implementing XAUI in
Stratix GX Devices
Dev. Boards and Reference Designs
• Nios Development Boards & Kits
SNP White Paper
• Stratix GX in Storage Applications
16
 The Lowest-Cost CPLD Ever

© 2005 Altera Corporation

MAX II Advantages

1/2
1/2the
theCost
Cost
Consumer
Products

4x
4x the
the Density
Density
Communication
Products

1/10
1/10the
thePower
Power

Battery-Powered
Products
2x
2x the
the
Performance
Performance

Computing
Products
18
CPLD Market Leadership
MAX
MAX
The
TheCPLD
CPLD
Market
MarketLeader
Leader
45% Low Cost
2000: MAX 3000A
40%
35% High
30% Performance
Market Share

1998: MAX 7000A

25%
20% JTAG ISP
15% 1996: MAX 7000S

10%
5%
0%
Altera Lattice Xilinx Cypress Atmel Other
Source: Altera Estimate 2003

19
MAX II Architecture

Logic
Elements
(LEs)

Staggered
I/O Pads

JTAG & Control

Configuration Circuitry
Flash Memory

User Flash
Memory

20
MAX II Device Family

User
Typical User Fastest
Speed Flash
Device LEs Macro- I/O tpd1 Memory
Grades
cells Pins (ns)
(bits)
EPM240 240 192 80 3, 4, 5 4.5 8,192
EPM570 570 440 160 3, 4, 5 5.5 8,192
EPM1270 1,270 980 212 3, 4, 5 6.0 8,192
EPM2210 2,210 1,700 272 3, 4, 5 6.5 8,192

21
MAX & MAX II Comparison
Parameter MAX MAX II
Process Technology 0.3-um CMOS 0.18-um Flash
Logic Architecture Product Term Look-Up Table (LUT)
Density Range 32 to 512 Macrocells 128 to 2210 Macrocells
(240 to 2,210 LEs)
Routing Architecture Global Row & Column
On-Chip Flash Memory None 8 Kbits
Maximum User I/O 212 272
Pins
Supply Voltage 5.0 V, 3.3 V, 2.5 V 3.3 V/2.5 V, 1.8 V
I/O Voltages 5.0 V, 3.3 V, 2.5 V, 1.8 V 3.3 V, 2.5 V, 1.8 V, 1.5 V
Global Clock Networks 2 per Device 4 per Device
Output Enables (OEs) 6 to 10 per Device 1 per I/O Pin
Schmitt Triggers None 1 per I/O Pin

22
User Flash Memory
„ 8 Kbits User-Accessible Flash
Memory
„ Interfaces to Serial Peripheral Buy
Buy MAX
MAX IIII
Get
Get an
an
Interconnect (SPI), Parallel, or EPROM
EPROM for Free!
for Free!
Proprietary Busses
„ Replaces EEPROMs
„ Applications
− Storing Manufacturing Data
− System Parameters
− User Parameters
− Software Revision Data

23
Real-Time ISP
„ Update the Device’s Core Logic
Array
Program While in
Operation
− Reduce System Downtime
for ISP Update
− Change Immediately or
Wait Until Next Power Cycle
„ Application Examples
− Field Upgrades of Fault- 10110001
10110001
Tolerant Systems
Configuration Flash
− Diagnostic Design for Memory Block
Manufacturing; Convert to
Functional Design

24
Flexible Supply Voltage
„On-Chip Voltage
Regulator
„Accepts 3.3-, 2.5- &
1.8-V Supply Inputs
„Internally Converted to 1.8 V
2.5 V

1.8-V Core Voltage 3.3 V

Convenience of 3.3 V with

the Power & Performance of 1.8 V
25
Pricing & Availability
550000K
Kuu
M
Maarrqquueeee Pr
Priicciinngg
iinn 220005
05

Typical Estimated ES
Device
Macrocells Price(1) Availability
EPM240 192 $1.50 Q4 2004

EPM570 440 $2.30 Q4 2004

EPM1270 980 $4.25 Q3 2004

EPM2210 1,700 $7.00 Q1 2005

(1) Preliminary pricing based on 2005 500KU quantities; cheapest package, slowest speed grade.

26
 MAX II Power Consumption
400
MAX 7128AE (3.3 V)
350
Consumption (mW)

300
250
Power

200
150
100
(3.3 V)
50 (2.5 V) MAX II
(1.8 V)
0
0 50 100 150 200

Operating Frequency (MHz)

90% Lower Power Consumption

27
Power Comparison
Power @ Power @ Power @
Device 0 MHz 50 MHz 100 MHz
(mW) (mW) (mW)
EPM240 (3.3 V) 39 55 72

EPM240G (1.8 V) 3 12 21
~1/10
EPM7128AE 300 337 373 Power
(Turbo)
EPM7128AE 126 163 200
(Non-Turbo)
CoolRunner II 0.03 14 29
XC2C128
MACH 4000C 2.7 18 34
LC4128C
28
Low Power for New Markets
70 CoolRunner II

60

50

40

30

20

10

25 50 75 100 125 150 175 200

Frequency (MHz)
Low Power & 4X the Density
29
MAX II Replaces Small ASSPs
Solution
Price
(100K Units)

PLX 9030
„ 32-Bit, 33MHz PCI $9.00
„ 32-Bit Local Bus
„ Fixed Functionality

EPM1270F256C5
EPM1270 $4.50
„ 32-Bit, 33-MHz PCI
„ 32-Bit Local Bus
„ 50% Utilization

Lower Cost, More Capacity

30