8086 is a 16-bit microprocessor and was designed in 1978 by Intel.

Unlike, 8085,
an 8086 microprocessor has 20-bit address bus. Thus, is able to access 220 i.e.,
1 MB address in the memory.

As we know that a microprocessor performs arithmetic and logic operations. And

an 8086 microprocessor is able to perform these operations with 16-bit data in
one cycle. Hence is a 16-bit microprocessor.

The 8086 microprocessor was developed to overcome the drawbacks of the

8085 microprocessor. It means that the 8086 is a successor of the 8085
microprocessor in the Intel series. Here, the number 8086 denotes the IC number
of this microprocessor.

Features of 8086 microprocessor

1. The 8086 microprocessor is a 16-bit microprocessor. What this means is
that the ALU and the internal registers work with 16 bit of binary data at a
time.
2. It has 16 bits of the data bus. Because of this, the 8086 can read or write
either 16 bit or 8 bit of data at a time.
3. The 8086 microprocessor has 20 bits of address lines that can access
220 address locations.
4. Each memory location is a byte-addressable memory location.
Therefore, the total amount of memory that the 8086 microprocessor
contains = 220 bytes = 1 MB
Therefore, the 8086 can access up to 1 MB of memory.
5. It works in the frequency range of about 5-10 MHz. (There are 3 versions
of the 8086 microprocessor and each of them works in a different
frequency range.)
6. The 8086 microprocessor works in 2 modes:
o Maximum mode
o Minimum mode
7. The instruction queue of the 8086 microprocessor is of 6 bytes of length.
Therefore, the 8086 microprocessor can pre-fetch up to 6 instructions
from the memory and queue them in order to speed up the instruction
execution.
8. The 8086 microprocessor can perform only fixed-point arithmetic
instructions. It means that the floating-point operations cannot be
performed by it. This is a drawback of the 8086 which was later eliminated
in the further series of Intel processors.

Components of 8086 microprocessor

 The 8086 microprocessor consists of two main blocks:
a. Bus Interface Unit (BIU)
 b. Execution Unit (EU)
 The Bus Interface Unit (BIU) :- This unit handles all transfer of data and
addresses on the buses for the EU(execution unit). This unit sends out
addresses, fetches instructions from memory, reads data from ports and
memory and writes data to ports and memory. And consists of the
following components:
a. Instruction Queue
b. Segment Registers
c. Instruction Pointer (IP)
 The Execution Unit (EU) :- Execution unit gives instructions to BIU stating
from where to fetch the data and then decode and execute those instructions. Its
function is to control operations on data using the instruction decoder & ALU. EU
has no direct connection with system buses as shown in the above figure, it
performs operations over data through BIU. And consists the following:
a. Arithmetic Logic Unit (ALU)
b. Control Unit
c. General Purpose registers
d. Index registers and pointers (except IP)
e. Flags and Operands
history of microprocessor
The CPU is known as the central processing unit, and this term is
synonymous with microprocessor. The microprocessor is considered
the brain of the computer, and Intel invented the term in 1971. There
was a previous 8-bit chip developed in 1969 known as the Four-Phase
AL1; however, Intel invented a better component and coined the term
microprocessor.

Addressing modes in 8086 microprocessor

The way of specifying data to be operated by an instruction is known
as addressing modes. This specifies that the given data is an immediate data or
an address. It also specifies whether the given operand is register or register
pair.
Types of addressing modes:
1. Register mode – In this type of addressing mode both the operands are registers.

Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
2. Immediate mode – In this type of addressing mode the source operand is a 8 bit
or 16 bit data. Destination operand can never be immediate data.
Example:

MOV AX, 2000

MOV CL, 0A
ADD AL, 45
AND AX, 0000
Note that to initialize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX

3. Displacement or direct mode – In this type of addressing mode the effective
address is directly given in the instruction as displacement.
Example:
 MOV AX, [DISP]
MOV AX, [0500]

4. Register indirect mode – In this addressing mode the effective address is in SI,
DI or BX.
Example:

MOV AX, [DI]

ADD AL, [BX]
MOV AX, [SI]

5. Based indexed mode – In this the effective address is sum of base register and
index register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]

6. Indexed mode – In this type of addressing mode the effective address is sum of
index register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]

7. Based mode – In this the effective address is the sum of base register and
displacement.
Example:
MOV AL, [BP+ 0100]

8. Based indexed displacement mode – In this type of addressing mode the
effective address is the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]

9. String mode – This addressing mode is related to string instructions. In this the
value of SI and DI are auto incremented and decremented depending upon the
value of directional flag.
Example:
MOVS B
MOVS W

10. Input/Output mode – This addressing mode is related with input output
operations.
Example:
 IN A, 45
OUT A, 50

11. Relative mode –

In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address

Arithmetic Instructions:

The 8086 provides many arithmetic operations: addition, subtraction,

negation,
multiplication and comparing two values.

ADD :
The add instruction adds the contents of the source operand to the
destination
operand.
Eg. ADD AX, 0100H
ADD AX, BX
ADD AX, [SI]
ADD AX, [5000H]
ADD [5000H], 0100H
ADD 0100H

ADC : Add with Carry

This instruction performs the same operation as ADD instruction, but
adds the carry
flag to the result.
Eg. ADC 0100H
ADC AX, BX
ADC AX, [SI]
ADC AX, [5000]
ADC [5000], 0100H

SUB : Subtract
The subtract instruction subtracts the source operand from the
destination operand
and the result is left in the destination operand.
Eg. SUB AX, 0100H
SUB AX, BX
SUB AX, [5000H]
SUB [5000H], 0100H

SBB : Subtract with Borrow

The subtract with borrow instruction subtracts the source operand and
the borrow flag
(CF) which may reflect the result of the previous calculations, from the
destination
operand
Eg. SBB AX, 0100H
SBB AX, BX
SBB AX, [5000H]
SBB [5000H], 0100H

INC : Increment
This instruction increases the contents of the specified Register or
memory location
by 1. Immediate data cannot be operand of this instruction.
Eg. INC AX
INC [BX]
INC [5000H]

DEC : Decrement
The decrement instruction subtracts 1 from the contents of the specified
register or
memory location.
Eg. DEC AX
DEC [5000H]

NEG : Negate
The negate instruction forms 2’s complement of the specified
destination in the
instruction. The destination can be a register or a memory location. This
instruction can
be implemented by inverting each bit and adding 1 to it.
Eg. NEG AL
AL = 0011 0101 35H Replace number in AL with its 2’s complement
AL = 1100 1011 = CBH

CMP : Compare
This instruction compares the source operand, which may be a register
or an
immediate data or a memory location, with a destination operand that
may be a register or a memory location
Eg. CMP BX, 0100H
CMP AX, 0100H
CMP [5000H], 0100H
CMP BX, [SI]
CMP BX, CX

MUL :Unsigned Multiplication Byte or Word

This instruction multiplies an unsigned byte or word by the contents of
AL.
Eg.
MUL BH                     ; (AX)        (AL) x (BH)
MUL CX                     ; (DX)(AX) (AX) x (CX)
MUL WORD PTR [SI] ; (DX)(AX) (AX) x ([SI])

IMUL :Signed Multiplication

This instruction multiplies a signed byte in source operand by a signed
byte in AL or
a signed word in source operand by a signed word in AX.
Eg. IMUL BH
IMUL CX
IMUL [SI]

CBW : Convert Signed Byte to Word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said
to be sign extension of AL.
Eg. CBW
AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in
AX.
Result in AX = 1111 1111 1001 1000

CWD : Convert Signed Word to Double Word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said
to be sign extension of AL.
Eg. CWD
Convert signed word in AX to signed double word in DX : AX
DX= 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

DIV : Unsigned division

This instruction is used to divide an unsigned word by a byte or to divide
an unsigned
double word by a word.
Eg.
DIV CL ; Word in AX / byte in CL
            ; Quotient in AL, remainder in AH
DIV CX ; Double word in DX and AX / word
            ; in CX, and Quotient in AX,
            ; remainder in DX
AAA : ASCII Adjust After Addition
The AAA instruction is executed after an ADD instruction that adds two
ASCII coded
operand to give a byte of result in AL. The AAA instruction converts the
resulting
contents of Al to a unpacked decimal digits.
Eg.
ADD CL, DL ; [CL] = 32H = ASCII for 2
                    ; [DL] = 35H = ASCII for 5
                    ; Result [CL] = 67H
MOV AL, CL ; Move ASCII result into AL since
                    ; AAA adjust only [AL]
AAA             ; [AL]=07, unpacked BCD for 7

AAS : ASCII Adjust AL after Subtraction

This instruction corrects the result in AL register after subtracting two
unpacked
ASCII operands. The result is in unpacked decimal format. The
procedure is similar to
AAA instruction except for the subtraction of 06 from AL.

AAM : ASCII Adjust after Multiplication

This instruction, after execution, converts the product available In AL
into unpacked
BCD format.
Eg.
MOV AL, 04 ; AL = 04
MOV BL ,09 ; BL = 09
MUL BL        ; AX = AL*BL ; AX=24H
AAM             ; AH = 03, AL=06

AAD : ASCII Adjust before Division

This instruction converts two unpacked BCD digits in AH and AL to the
equivalent
binary number in AL. This adjustment must be made before dividing the
two unpacked
BCD digits in AX by an unpacked BCD byte. In the instruction
sequence, this
instruction appears Before DIV instruction.
Eg.
AX 05 08
AAD result in AL 00 3A  ,since 58D = 3AH in AL
The result of AAD execution will give the hexadecimal number 3A in AL
and 00
in AH. Where 3A is the hexadecimal Equivalent of 58 (decimal).

DAA : Decimal Adjust Accumulator

This instruction is used to convert the result of the addition of two
packed BCD
numbers to a valid BCD number. The result has to be only in AL.
Eg.
AL = 53 CL = 29
ADD AL, CL ; AL <– (AL) + (CL)
                    ; AL 53 + 29
                    ; AL 7C
DAA ; AL 7C + 06 (as C>9)
        ; AL 82

DAS : Decimal Adjust after Subtraction

This instruction converts the result of the subtraction of two packed BCD
numbers to
a valid BCD number. The subtraction has to be in AL only.
Eg.
AL = 75, BH = 46
SUB AL, BH ; AL     2F = (AL) – (BH)
                    ; AF = 1
DAS ; AL 29 (as F>9, F – 6 = 9)
JUMP GROUP

The main program control instruction, jump (JMP), allows the programmer to skip
sections of a program and branch to any part of the memory for the next instruction. A
conditional jump instruction allows the programmer to make decisions based upon
numerical tests. The results of numerical tests are held in the flag bits, which are then
tested by conditional jump instructions. Another instruction similar to the conditional
jump, the conditional set, is explained with the conditional jump instructions in this
section.

UNCONDITIONAL JUMP

Three types of unconditional jump instructions are available to the microprocessor: short
jump, near jump, and far jump.

1- short jump is a 2-byte instruction that allows jumps or branches

to memory locations within +127 and –128 bytes from the address
following the jump.
EXAMPLE
0000 33 DB XOR BX,BX
0002 B8 0001 START: MOV AX,1
0005 03 C3 ADD AX,BX
0007 EB 17 JMP SHORT NEXT
0020 8B D8 NEXT: MOV BX,AX
0022 EB DE JMP START
 2- near jump is a 3-byte instruction that allows a branch or jump
within ±32K bytes (or anywhere in the current code segment) from
the instruction in the current code segment. Remember that
segments are cyclic in nature, which means that one location
above offset address FFFFH is offset address 0000H. For this
reason, if you jump 2 bytes ahead in memory and the instruction
pointer addresses offset address FFFFH, the flow continues at
offset address 0001H. Thus, a displacement of ±32K bytes allows
a jump to any location within the current code segment.
EXAMPLE
0000 33DB XOR BX,BX
0002 B8 0001 START: MOV AX,1
0005 03 C3 ADD AX,BX
0007 E9 0200 R JMP NEXT
0200 8B D8 NEXT: MOV BX,AX
0202 E9 0002 R JMP START

3- far jump is a 5-byte instruction that allows a jump to any memory

location within the real memory system. The short and near jumps
are often called intrasegment jumps, and the far jumps are often
called intersegment jumps.
EXAMPLE
EXTRN UP:FAR
0000 33 DB XOR BX,BX
0002 B8 0001 START: ADD AX,1
0005 E9 0200 R JMP NEXT
0200 8B D8 NEXT: MOV BX,AX
0202 EA 0002 —— R JMP FAR PTR START
0207 EA 0000 —— R JMP UP

Conditional jump

Conditional jump instructions are always short jumps in the 8086 through the 80286
microprocessors. This limits the range of the jump to within +127 bytes and -128 bytes
from the location following the conditional jump. In the 80386 and above, conditional
jumps are either short or near jumps (±32K). In the 64-bit mode of the Pentium 4, the
near jump distance is ±2G for the conditional jumps. This allows these microprocessors
to use a conditional jump to any location within the current code segment.
The conditional jump instructions test the following flag bits: sign (S), zero (Z), carry (C),
parity (P), and overflow (0). If the condition under test is true, a branch to the label
associated with the jump instruction occurs. If the condition is false, the next sequential
step in the program executes. For example, a JC will jump if the carry bit is set.

The operation of most conditional jump instructions is straightforward because they often
test just one flag bit, although some test more than one. Relative magnitude
comparisons require more complicated conditional jump instructions that test more than
one flag bit.

TABLE

EXAMPLE 6

;Instructions that search a table of 100H bytes for 0AH

;The offset address of TABLE is assumed to be in SI

0017 B9 0064 MOV CX,100 ;load counter
001A B0 0A MOV AL,0AH ;load AL with 0AH
001C FC CLD ;auto-increment
001D F2/AE REPNE SCASB ;search for 0AH 001F F9 STC ;set
carry if found 0020 E3 01 J CXZ NOT_FOUND ;if not found 0022
NOT_FOUND

LOOP

The LOOP instruction is a combination of a decrement CX and the JNZ conditional jump.
In the 8086 through the 80286 processors, LOOP decrements CX; if CX != 0, it jumps to
the address indicated by the label. If CX becomes 0, the next sequential instruction
executes. In the 80386 and above, LOOP decrements either CX or ECX, depending
upon the instruction mode. If the 80386 and above operate in the l6-bit instruction mode,
LOOP uses CX; if operated in the 32-bit instruction mode, LOOP uses ECX. This default
is changed by the LOOPW (using CX) and LOOPD (using ECX) instructions in the
80386 through the Core2. In the 64-bit mode, the loop counter is in RCX and is 64 bits
wide.

EXAMPLE 6–7

;A program that sums the contents of BLOCK1 and BLOCK2

;and stores the results on top of the data in BLOCK2.

; .MODEL SMALL ;select SMALL model

 0000 .DATA ;start data segment
0000 0064[ BLOCK1 DW 100 DUP(?) ;100 words for BLOCK1
0000 ]

00C8 0064[ BLOCK2 DW 100 DUP(?) ;100 words for BLOCK2

. 0000 ]

0000 .CODE ;start code segment .STARTUP ;start program 0017 8C D8 MOV AX,DS
;overlap DS and ES 0019 8E C0 MOV ES,AX 001B FC CLD ;select auto-increment
001C B9 0064 MOV CX,100 ;load counter 001F BE 0000 R MOV SI,OFFSET
BLOCK1 ;address BLOCK1 0022 BF 00C8 R MOV DI,OFFSET BLOCK2 ;address
BLOCK2 0025 AD L1: LODSW ;load AX with BLOCK1 0026 26:03 05 ADD AX,ES:
[DI] ;add BLOCK2 0029 AB STOSW ;save answer 002A E2 F9 LOOP L1 ;repeat 100
times .EXIT END

CALL

The CALL instruction transfers the flow of the program to the procedure. The CALL
instruction differs from the jump instruction because a CALL saves a return address on
the stack. The return address returns control to the instruction that immediately follows
the CALL in a program when a RET instruction executes.

Near CALL. The near CALL instruction is 3 bytes long; the first byte contains the
opcode, and the second and third bytes contain the displacement, or distance of ±32K in
the 8086 through the 80286 processors.

Far CALL. The far CALL instruction is like a far jump because it can call a procedure
stored in any memory location in the system. The far CALL is a 5-byte instruction that
contains an opcode followed by the next value for the IP and CS registers. Bytes 2 and 3
contain the new contents of the IP, and bytes 4 and 5 contain the new contents for CS.

CALLs with Register Operands. Like jump instructions, call instructions also may contain
a register operand.

CALLs with Indirect Memory Addresses. A CALL with an indirect memory address is
particularly useful whenever different subroutines need to be chosen in a program.

RET

The return instruction (RET) removes a 16-bit number (near return) from the stack and
places it into IP, or removes a 32-bit number (far return) and places it into IP and CS.
The near and far return instructions are both defined in the procedure’s PROC directive,
which automatically selects the proper return instruction. With the 80386 through the
Pentium 4 processors operating in the protected mode, the far return removes 6 bytes
from the stack. The first 4 bytes contain the new value for EIP and the last 2 contain the
new value for CS. In the 80386 and above, a protected mode near return removes 4
bytes from the stack and places them into EIP.
8086 INSTRUCTION FORMAT:
The 8086 instruction size varies from one to six bytes. The general 8086-instruction format is
shown in the figure.

Figure: 8086 Instruction Format

The op-code register direction bit (D) and data size bit (W) in byte 1 are defined by Intel as
follows:

 Op code occupies six bits and it defines the operation to be carried out by the
instruction.
 Register Direction bit (D) occupies one bit. It defines whether the register operand in
byte 2 is the source or destination operand.
o D = 1 specifies that the register operand is the destination operand; on the
other hand,
o D = 0 indicates that the register is a source operand.
 Data size bit (W) defines whether the operation to be performed is on 8- or 16- bit
data.
o W = 0 indicates 8-bit operation.
o W = 1 specifies 16-bit operation.
 The second byte of the instruction usually identifies whether one of the operands is in
the memory or the registers; this byte contains three fields.
o The Mode (MOD) field,
o The register (REG) field,
o The Register/Memory (R/M) field.
The 2-bit MOD field specifies whether the operand is in register or memory as follows:
REG field occupies 3 bits. It defines the register for the first operand, which is specified as
the source or destination by the D-bit (byte 1). The definition of REG and W fields are given
below:

The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second
operand as shown below:
MOD 11

Effective address calculation

In the above, encoding of the R/M field depends on how the mode field is set. If MOD = 11
(register-to-register mode), then R/M identifies the second register operand. If the MOD
selects memory mode, then R/M indicates how the effective address of the memory operand
is to be calculated.

Bytes 3 through 6 of an instruction are an optional field that normally contains the
displacement value of a memory operand ‘and/or’ the actual value of an immediate constant
operand. As an example, consider the instruction.

Example: MOV CH,BL

This instruction transfers the 8-bit content of BL into CH. We will determine the machine
code of this instruction. The 6-bit op code for this instruction is 100010 (base-2). The D-bit
indicates whether the register specified by the REG field of byte 2 is a source or destination
operand. Let us define the BL in the REG field of byte 2. D = 0 indicates that the REG field of
the next byte is the source operand. The W-bit of byte 1 is 0 since this is a byte operation.

In byte 2, since the second operand is a register, MOD field is 11 (base-2). The R/M field =
101 (base-2) specifies that the destination register is CH and, therefore, R/M = 101 (base-
2).Hence the machine code
MOV CH,BL  is1000100011011101
BYTE1 BYTE2
=88DD(base-16).
BCD and ASCII arithmatic

The microprocessor allows arithmetic manipulation of both BCD (binary-coded decimal)

and ASCII (American Standard Code for Information Interchange) data. This is
accomplished by instructions that adjust the numbers for BCD and ASCII arithmetic. The
BCD operations occur in systems such as point-of-sales terminals (e.g., cash registers)
and others that seldom require complex arithmetic. The ASCII operations are performed
on ASCII data used by many programs. In many cases, BCD or ASCII arithmetic is
rarely used today, but some of the operations can be used for other purposes. None of
the instructions detailed in this section of the chapter function in the 64-bit mode of the
Pentium 4 or Core2. In the future it appears that the BCD and ASCII instruction will
become obsolete.

BCD Arithmetic

Two arithmetic techniques operate with BCD data: addition and subtraction.

DAA (decimal adjust after addition) instruction

The DAA instruction follows the ADD or ADC instruction to adjust the result into a BCD
result. Suppose that DX and BX each contain 4-digit packed BCD numbers.

Example

0000 BA 1234 MOV DX,1234H ;load 1234 BCD

0003 BB 3099 MOV BX,3099H ;load 3099 BCD
0006 8A C3 MOV AL,BL ;sum BL and DL
0008 02 C2 ADD AL,DL
000A 27 DAA
000B 8A C8 MOV CL,AL ;answer to CL
000D 9A C7 MOV AL,BH ;sum BH, DH and carry
000F 12 C6 ADC AL,DH
0011 27 DAA
0012 8A E8 MOV CH,AL ;answer to CH

DAS (decimal adjust after subtraction) instruction

The DAS instruction functions as does the DAA instruction, except that it follows a
subtraction instead of an addition.

Example

0000 BA 1234 MOV DX,1234H ;load 1234 BCD

0003 BB 3099 MOV BX,3099H ;load 3099 BCD
0006 8A C3 MOV AL,BL ;subtract DL from BL
0008 2A C2 SUB AL,DL
000A 2F DAS
000B 8A C8 MOV CL,AL ;answer to CL
000D 9A C7 MOV AL,BH ;subtract DH
000F 1A C6 SBB AL,DH
0011 2F DAS
0012 8A E8 MOV CH,AL ;answer to CH

ASCII arithmetic

The ASCII arithmetic instructions function with ASCII-coded numbers. These numbers
range in value from 30H to 39H for the numbers 0–9. There are four instructions used
with ASCII arithmetic operations:

1. AAA (ASCII adjust after addition) :- The addition of two one-digit ASCII-
coded numbers will not result in any useful data.
Example
0000 B8 0031 MOV AX,31H ;load ASCII1
0003 04 39 ADD AL,39H ;add ASCII9
0005 37 AAA ;adjust sum
0006 05 3030 ADD AX,3030H ;answer to ASCII

2. AAD (ASCII adjust before division) :- Unlike all other adjustment

instructions, the AAD instruction appears before a division.
Example
0000 B3 09 MOV BL,9 ;load divisor
0002 B8 0702 MOV AX,702H ;load dividend
0005 D5 0A AAD ;adjust
0007 F6 F3 DIV BL ;divide

3. AAM (ASCII adjust after multiplication) :- The AAM instruction follows the
multiplication instruction after multiplying two one-digit unpacked BCD numbers.
Example
0000 B0 05 MOV AL,5 ;load multiplicand
0002 B1 03 MOV CL,3 ;load multiplier
0004 F6 E1 MUL CL
0006 DA 0A AAM ;adjust
4. AAS (ASCII adjust after subtraction) :- Like other ASCII adjust
instructions, AAS adjusts the AX register after an ASCII subtraction.

 These instructions use register AX as the source and as the destination.