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Implementation of Bit-4 Calculator Using Fpga: Ms. Vemu Sulochana (Project Engineer)
Implementation of Bit-4 Calculator Using Fpga: Ms. Vemu Sulochana (Project Engineer)
A Project report
submitted in partial fulfilment of the requirement for the
Summer Training
in
VLSI Design & FPGA Implementation
SUBMITTED BY
This is to certify that Report entitled “ Implementation of bit-4 calculator using FPGA” submitted
by us in partial fulfillment of the requirement for Summer Training
in VLSI Design & FPGA Implementation C-DAC, Mohali under the supervision of Ms. Vemu
Sulochana , ACSD comprises only our original work and due acknowledgement has been made in
the text to all other material used.
Before we get into the thick of things, we would like to add a few words of appreciation
for the people who have been a part of this project right from its inception. The writing of
this project has been one of the significant academic challenges that we have faced and
without the support, patience and guidance of the people involved, it would not have been
possible to accomplish this task. It is to them we owe our deepest gratitude.
It has been our privilege to have a project guide who has assisted us from the
commencement of the project. The success of the project is a result of sheer hard work
and determination put in by us and our Project Guide. We, hereby take this opportunity to
add a special note of thanks for Ms.Vemu Sulochana(Project Engineer) who undertook
to act as our mentor despite her many other academic commitments. Without her insight,
support and energy, this project would neither have kick-started, nor
would have reached fruitfulness.
Abstract
This report describes the project “Implementation of bit-4 calculator using FPGA”.
This calculator performs four different types of tasks namely- Addition, Subtraction,
division, multiplication. This calculator is a 4 bit calculator. A calculator consists of an
input bus and an output bus. The input bus receives all the data for the calculator,
operands and operators are all input through this one bus. The output bus transmits the
result of operation.The basic idea behind the design is to eliminate tedious
computations and algebraic manipulations that discourages many students and allow
them to solve problems and appreciate the power an value of mathematics in the world
today.
Table of Contents
10 Results: Simulation
11 Implementation on Spartan 3
12 RTL Schematic
13 Implementation using FPGA
INTRODUCTION
VLSI is the field which involves packing more and more logic devices into smaller and
smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now
be put into a small space few millimetres across! This has opened up a big opportunity to
do things that were not possible before. VLSI circuits are everywhere ... your computer,
your car, your brand new state-of the-art digital camera, the cell-phones, and what have
you. All this involves a lot of expertise on many fronts within the same field, which we
will look at in later sections
VHDL is a language for describing digital electronic systems. It arose out of the United
States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in
1980. VHSIC Hardware Description Language (VHDL) was developed, and
subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers
(IEEE) in the US.
Need
1) It allows description of the structure of a design that is how it is decomposed into sub-
designs, and how those sub designs are interconnected.
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3) As a result, it allows a design to be simulated before being manufactured, so that
designers can quickly compare alternatives and test for correctness without the delay and
expense of hardware prototyping.
Scope
VHDL is suited to the specification, design and description of digital electronic hardware.
System level
VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-
software split. Simulation at this level is usually stochastic, and is concerned with
modeling performance, throughput, queuing and statistical distributions. VHDL has been
used in this area with some success, but is best suited to functional and not stochastic
simulation.
Digital
VHDL is suitable for use today in the digital hardware design process, from specification
through high-level functional simulation, manual design and logic synthesis down to
gate-level simulation. VHDL tools usually provide an integrated design environment in
this area.VHDL is not suited for specialized implementation-level design verification
tools such as analog simulation, switch level simulation and worst case timing
simulation. VHDL can be used to simulate gate level fan-out loading effects providing
coding
2
VLSI Design Flow
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Design Simulation and Design Synthesis
Synthesis
Is the process of translating a design description to another level of abstraction, i.e., from
behavior to structure. We achieved synthesis by using a Synthesis tool like Foundation
Express which outputs a net list. It is similar to the compilation of a high level
programming language like C into assembly code
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Simulation
Design Creation/Verification
Enter your VHDL design source using a text editor or a context-sensitive HDL editor.
Your VHDL design source can contain RTL-level constructs.
Behavioral Simulation
Synthesis
After you have created your behavioral VHDL design source, you must synthesize it.
Synthesis transforms the behavioral VHDL file into a gate-level netlist and optimizes the
design for a target technology.
Simulation
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Then simulator will check functionality. It means that design and code should be working
according to truth table or not. Simulation is just testing the system at software level
where as real testing is at hardware level.
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Introduction to FPGA : SPARTAN 3, SPARTAN 3E, SPARTAN 6
Xilinx
Founded in Silicon Valley in 1984, the company is headquartered in San Jose, USA, with
additional offices in Longmont, USA; Dublin, Ireland; Singapore; Hyderabad, India;
Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.
Spartan family
The Spartan series targets low cost, high-volume applications with a low-power footprint
e.g. displays, set-top boxes, wireless routers and other applications.
The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, dual-oxide process
technology. The Spartan-6 was marketed in 2009 as a low-cost option for automotive,
wireless communications, flat-panel display and video surveillance applications.
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Spartan 3E FPGA Family
Spartan-3:
Spartan-6:
General Description
The Spartan®-6 family provides leading system integration capabilities with the lowest
total cost for high-volume applications. The thirteen-member family delivers expanded
densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of
previous Spartan families, and faster, more comprehensive connectivity. Built on a
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mature 45 nm low-power copper process technology that delivers the optimal balance of
cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-
register 6-input lookup table (LUT) logic and a rich selection of built-in system-level
blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices,
SDRAM memory controllers, enhanced mixed-mode clock management blocks,
SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI
Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device
DNA protection. These features provide a lowcost programmable alternative to custom
ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution
for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive
embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for
Targeted Design Platforms that deliver integrated software and hardware components that
enable designers to focus on innovation as soon as their development cycle begins.
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FULL ADDER
Full Adder is the adder which adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to
create a byte-wide adder and cascade the carry bit from one adder to the another.
Full
Adder
The output carry is designated as C-OUT and the normal output is designated as S.
VHDL CODE:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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entity bit4adder is
u :in std_logic;
end bit4adder;
component fulladder is
port(a,b,cin:in std_logic;
s,cout:out std_logic);
end component;
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signal s:STD_LOGIC_vector(3 downto 0);
signal v: STD_LOGIC;
begin
end structural;
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Full Adder Truth Table:
With the truth-table, the full adder logic can be implemented. You can see that the output S is an XOR
between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-OUT will only
be true if any of the two inputs out of the three are HIGH.
So, we can implement a full adder circuit with the help of two half adder circuits. At first, half adder will
be used to add A and B to produce a partial Sum and a second half adder logic can be used to add C-IN
to the Sum produced by the first half adder to get the final S output.
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If any of the half adder logic produces a carry, there will be an output carry. So, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit
shown below.
The implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol
is mostly used to represent the operation. Given below is a simpler schematic representation of a one-bit
full adder.
With this type of symbol, we can add two bits together, taking a carry from the next lower order of
magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit
operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add
two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit
blocks.
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FULL SUBTRACTOR
Full subtractor is an electronic device or logic circuit which performs subtraction of two binary digits. It is a
combinational logic circuit used in digital electronics. Many combinational circuits are available in integrated
circuit technology namely adders, encoders, decoders and multiplexers. In this article, we are going to discuss full
subtractor construction using half subtractor and also the terms like truth table.
VHDL CODE:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bit4subst is
u :in std_logic;
end bit4subst;
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architecture structural of bit4subst is
component bit4adder is
u :in std_logic;
end component;
begin
m(0)<=not b(0);
m(1)<=not b(1);
m(2)<=not b(2);
m(3)<=not b(3);
r<= "0001";
--s=difference
--v=carry
--v=0;negative
--v=1;positive
end structural;
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Full Subtractor Truth Table
This subtractor circuit executes a subtraction between two bits, which has 3- inputs (A, B and Bin) and
two outputs (D and Bout). Here the inputs indicate minuend, subtrahend, & previous borrow, whereas
the two outputs are denoted as borrow o/p and difference. The following image shows the truth table of
full-subtractor.
Outputs
Inputs
Subtrahend (B) Borrow (Bin) Difference (D)
Minuend (A) Borrow (Bout)
0 0
0 0 0
0
0 1 1 1
1
0 1 0 1
1
0 1 1 0
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1
0 0 1 0
0
1 0 1 0
1
1 0 0 0
1 1
1 1 1
BOOTH MULTIPLIER
Booth algorithm gives a procedure for multiplying binary integersin signed 2’s complement
representation in efficient way, i.e., less number of additions/subtractions required. It
operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a
string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to
2^m.
As in all multiplication schemes, booth algorithm requires examination of the multiplier
bits and shifting of the partial product. Prior to the shifting, the multiplicand may be added to
the partial product, subtracted from the partial product, or left unchanged according to following
rules:
1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1’s in the multiplier
2. The multiplicand is added to the partial product upon encountering the first 0 (provided
that there was a previous ‘1’) in a string of 0’s in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.
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VHDL CODE:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity booth_multiplier is
end booth_multiplier;
signal P1,P2,P3,P4,P5,P1_shift,P2_shift,P3_shift,P4_shift,P5_shift:
STD_LOGIC_vector(10 downto 0);
begin
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u<= '0' & x;
P(0)<='0';
P1_shift(10)<=P1(10);
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P2<=P1_shift when (P1_shift(1 downto 0)="00" or P1_shift(1 downto 0)="11")else
P2_shift(10)<=P2(10);
P3_shift(10)<=P3(10);
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P4<=P3_shift when (P3_shift(1 downto 0)="00" or P3_shift(1 downto 0)="11")else
P4_shift(10)<=P4(10);
P5_shift(10)<=P5(10);
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end Behavioral;
RESTORING DIVISION
A division algorithm provides a quotient and a remainder when we divide two number. They
are generally of two type slow algorithm and fast algorithm. Slow division algorithm are
restoring, non-restoring, non-performing restoring, SRT algorithm and under fast comes
Newton–Raphson and Goldschmidt.
In this article, will be performing restoring algorithm for unsigned integer. Restoring term is due
to fact that value of register A is restored after each iteration.
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Here, register Q contain quotient and register A contain remainder. Here, n-bit dividend is
loaded in Q and divisor is loaded in M. Value of Register is initially kept 0 and this is the
register whose value is restored during iteration due to which it is named Restoring.
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Let’s pick the step involved:
Step-1: First the registers are initialized with corresponding values (Q = Dividend, M =
Divisor, A = 0, n = number of bits in dividend)
Step-2: Then the content of register A and Q is shifted right as if they are a single unit
Step-3: Then content of register M is subtracted from A and result is stored in A
Step-4: Then the most significant bit of the A is checked if it is 0 the least significant bit
of Q is set to 1 otherwise if it is 1 the least significant bit of Q is set to 0 and value of
register A is restored i.e the value of A before the subtraction with M
Step-5: The value of counter n is decremented
Step-6: If the value of n becomes zero we get of the loop otherwise we repeat from step
2
Step-7: Finally, the register Q contain the quotient and A contain remainder
Examples:
Perform Division Restoring Algorithm
Dividend = 11
Divisor = 3
N M A Q OPERATION
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VHDL CODE:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity restoring_division is
end restoring_division;
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signal
P44,P444,P33,P333,P22,P222,P11,P111,P1,P2,P3,P4,P1_shift,P2_shift,P3_shift,P4_shift
: STD_LOGIC_vector(7 downto 0);
begin
process (P,S,P1_shift,P1,P11)
begin
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P1_shift(0)<= '0';
P1<= P1_shift + S;
if(P1(7) = '1')then
P111<=P11+A;
else
P111<=P11; --P12
end if;
end process;
process(P111,S,P2_shift,P2,P22)
begin
P2_shift(0)<= '0';
P2<= P2_shift + S;
P222<=P22+A;
else
P222<=P22; --P12
end if;
end process;
process(P222,S,P3_shift,P3,P33)
begin
P3_shift(0)<= '0';
P3<= P3_shift + S;
if(P3(7) = '1')then
P333<=P33+A;
else
P333<=P33; --P12
end if;
end process;
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process(P333,S,P4_shift,P4,P44)
begin
P4_shift(0)<= '0';
P4<= P4_shift + S;
if(P4(7) = '1')then
P444<=P44+A;
else
P444<=P44; --P12
end if;
end process;
end Behavioral;
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VHDL CODE BIT-4 CALCULATOR
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity bit4calculator is
c : in STD_LOGIC; --carry
end bit4calculator;
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architecture structural of bit4calculator is
component bit4adder is
u :in std_logic;
end component;
component bit4subst is
u :in std_logic;
end component;
component booth_multiplier is
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y : in STD_LOGIC_vector(3 downto 0);
end component;
component restoring_division is
end component;
component bit8mux4x1B is
end component;
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begin
t3<= so1;
t2<= so2;
t1<=z1;
end structural;
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RESULTS
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Simulation
Implementation on FPGA
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Write ‘net’ input for input written in the primary code and ‘loc =’ ‘pin number’ for choosing
location of the board.
Check synthesize-RST.
Then implement design.
Generate programming file.
Then configure target device.
A new window pops up.
Select Boundary Scan.
Right click on the white space and the click on initialize chain.
A .bit file would be created of the code we are implementing on Spartan 3.
Right click on the device added and click program.
The program is uploaded on the hardware and code is ready to run.
RTL Schematic
42
Implementation using FPGA
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