Prepared by:

Assist. Lect. Omar Haitham Alhabieb

Computer Architecture
Lesson 2 (Instruction Set Architecture)

Instruction Set Architecture (ISA): is the part of the computer architecture

related to programming, including the native data types, instructions,
registers, addressing modes, memory architecture, interrupt and exception
handling, and external I/O. An ISA includes a specification of the set of
opcodes (machine language), and the native commands implemented by a
particular processor.

Introduction

 The operation of the CPU is determined by the instructions it

executes, referred to as (machine instructions or computer
instructions).

 The collection of different instructions that a CPU can execute is

referred to as the CPU Instruction Set.

 Instruction set design is considered as one of the most interesting, and

most analyzed, aspects of computer design.

 The design of an instruction set is very complex, because it affects so

many aspects of the computer system.

 Also, the instruction set is the programmer's means of controlling the

CPU.

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Fundamental Design Issues

 The most important fundamental design issues include the following:

1. Operation repertoire: How many and which operations to provide, and

how complex operations should be.

2. Data types: The various types of data upon which operations are
performed.

3. Instruction format: Instruction length (in bits), number of addresses,

size of various fields, and so on.

4. Registers: Number of CPU registers that can be referenced by

instructions, and their use.

5. Addressing: The mode or modes by which the address of an operand

is specified.

Instruction Format

Operation part will specify the operation performed by the instruction (e.g.
AND, ADD, MOV). Types of operations include:

1. Data transfer

2. Arithmetic

3. Logical

4. Conversion

5. I/O instructions

6. System control

7. Transfer of control.

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Operand Definition & Types

 In mathematics, an operand is the object of a mathematical operation,

a quantity on which an operation is performed.
 Operands Used to load inputs to the operation and to store the result
of the operation (source & destination operands). Types of operands
include:
1. Addresses

2. Numbers

3. Characters

4. Logical data

Types of ISA

There are mainly two types of ISA, these are:

1. Complex instruction set computer (CISC): is a processor design

where single instructions can execute several low-level operations
(such as a load from memory, an arithmetic operation, and a memory
store) or are capable of multi-step operations or addressing modes
within single instructions.
 CISC Attempts to provide a single machine instruction for each
statement that is written in a high-level language.
 More complex instruction will result in fewer instructions
needed to program the CPU.
 Since instructions are varies in length, special decoding circuits
are required.

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 Variable – length instructions will make pipelining inefficient

to implement.
 Examples: the IBM 370/168, the INTEL 80x86, VAX 11/780
architectures.

CISC characteristics

The major characteristics of CISC architecture are:

1. It includes large number of instructions, typically from 100 to 250

instructions.
2. It uses some instructions that perform specialized tasks and are used
infrequently.
3. There are large varieties of addressing modes, typically from 5 to 20
different modes.
4. Variable length instruction formats.
5. It contains instructions that manipulate operands in memory.

2. Reduced instruction set computer (RISC): is a CPU design strategy

based on the insight that a simplified instruction set (as opposed to a
complex set) provides higher performance when combined with a
microprocessor architecture capable of executing those instructions
using fewer microprocessor cycles per instruction.
 This type uses fewer instructions with simple constructs.
 Executed much faster within the CPU without having to use memory
as often.

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 Attempts to reduce execution time by simplifying the instruction set

of the computer.
 Simple instructions will result in simple control logic.
 Ability to execute one instruction per clock cycle using pipelining.
 Examples: the IBM RISC System/6000, SPARC and MIPS R4000.

RISC characteristics

The major characteristics of a RISC processor can be summarized by:

1. Relatively few instructions.

2. Relatively few addressing modes.
3. Memory access limited to load and store instructions.
4. All operations done within the registers of the CPU.
5. Fixed-length, easily decoded instruction format.
6. Single-cycle instruction execution (using pipelining).
7. Hardwired rather than microprogrammed control.

Practical Example:

The diagram below represents the storage scheme for a generic computer.
The main memory is divided into locations numbered from (row) 1:
(column) 1 to (row) 6: (column) 4. The execution unit is responsible for
carrying out all computations. However, the execution unit can only operate
on data that has been loaded into one of the six registers (A, B, C, D, E, or
F). Let's say we want to find the product of two numbers - one stored in

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location 2:3 and another stored in location 5:2 - and then store the product
back in the location 2:3.

The CISC Approach

The primary goal of CISC architecture is to complete a task in as few lines

of assembly as possible. This is achieved by building processor hardware
that is capable of understanding and executing a series of operations. For this
particular task, a CISC processor would come prepared with a specific
instruction (we'll call it "MULT"). When executed, this instruction loads the
two values into separate registers, multiplies the operands in the execution
unit, and then stores the product in the appropriate register. Thus, the entire
task of multiplying two numbers can be completed with one instruction:

MULT 2:3, 5:2

MULT is what is known as a "complex instruction." It operates directly on

the computer's memory banks and does not require the programmer to
explicitly call any loading or storing functions. It closely resembles a
command in a higher level language. For instance, if we let "a" represent the

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value of 2:3 and "b" represent the value of 5:2, then this command is
identical to the C statement "a = a * b".

One of the primary advantages of this system is that the compiler has to do
very little work to translate a high-level language statement into assembly.
Because the length of the code is relatively short, very little RAM is required
to store instructions. The emphasis is put on building complex instructions
directly into the hardware.

The RISC Approach

RISC processors only use simple instructions that can be executed within
one clock cycle. Thus, the "MULT" command described above could be
divided into three separate commands: "LOAD," which moves data from the
memory bank to a register, "PROD," which finds the product of two
operands located within the registers, and "STORE," which moves data from
a register to the memory banks. In order to perform the exact series of steps
described in the CISC approach, a programmer would need to code four
lines of assembly:

LOAD A, 2:3

LOAD B, 5:2

PROD A, B

STORE 2:3, A

At first, this may seem like a much less efficient way of completing the
operation. Because there are more lines of code, more RAM is needed to

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store the assembly level instructions. The compiler must also perform more
work to convert a high-level language statement into code of this form.

However, the RISC strategy also brings some very important advantages.
Because each instruction requires only one clock cycle to execute, the entire
program will execute in approximately the same amount of time as the
multi-cycle "MULT" command. These RISC "reduced instructions" require
less transistors of hardware space than the complex instructions, leaving
more room for general purpose registers. Because all of the instructions
execute in a uniform amount of time (i.e. one clock), pipelining is possible.

Separating the "LOAD" and "STORE" instructions actually reduces the

amount of work that the computer must perform. After a CISC-style
"MULT" command is executed, the processor automatically erases the
registers. If one of the operands needs to be used for another computation,
the processor must re-load the data from the memory bank into a register. In
RISC, the operand will remain in the register until another value is loaded in
its place.

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Comparing CISC to RISC

 The following table summarizes key features in RISC and CISC

processors.

Characteristics CISC Architecture RISC Architecture

Variable formats: 16 to 32
Instruction format
and 64 bits
Clock rate 100-266 MHz
8-24 general-purpose
Register files
registers (GPRs)
Instruction set size and Around 300, with over four
types dozen instruction types
Around one dozen,
Addressing modes including indirect/indexed
addressing
Earlier model used unified
Cache design
cache, some use split caches
1 to 20 cycles, average 4
Cycle per instruction
cycles
Most microcoded, some use
CPU control
hardwired control
Representative Intel x86, IBM 390, Intel
commodity processors Pentium, and AMD 486
Fixed 32 bits instructions
180-500 MHz
32-192 GPRs, separate
integer and floating-point
files
Around 100, most are
register-based except
load/store
Limited to 3 to 5, only
read/store addressing the
memory
Most use split data cache
and instruction cache
1 cycle for simple
operations, average around
1.5 cycles
Most hardwired control
without control memory
Sun UltraSparc, MIPS
R10000, PowerPC 604, HP
PA-8000, Digital 21164