User Manual

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88E6393X Development Board

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User Manual

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1. Introduction

54 n
16 ch
The Marvell® 88E6393X, 88E6193X, and 88E6191X are a family of pin compatible devices that are single-chip

12 n Te
11-port Ethernet switches with eight 10/100/1000 PHY’s and three SERDES. The development board is intended
to provide a design example and facilitate the evaluation of this family of products.

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2. Overview

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Refer to Figure 1 for the development board connector positions.

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Figure 1: 88E6393X Development Board
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SMI AUX PORT

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5-12 VDC
USB2SMI

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Port 0 Port 10 Port 9

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SERDES SERDES SERDES
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MDC_PHY
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MDIO_PHY
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Port 0 RGMII Port 1 – Port 8 1000BASE-T integrated PHYs

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Depending on the features required to support a given application, the same PCB design can support the
88E6393X, 88E6193X, or 88E6191X as the devices are pin compatible. Port 0 is configured in RGMII mode and

54 n
16 ch
connected to an 88E1510 transceiver. The internal PHY Polling unit will monitor the link state of the external
PHYs through the SMI PHY interface and configure the associated MAC in the switch for the correct operation

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needed for a given link partner.

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3. Development Board Connectors and Switches

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All the dip switches and SMA connectors are clearly labeled on the board. Refer to Table 1 through Table 4 for
switch and connector functions.

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Table 1: Connectors
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Connector Connector Type Interface

Reference
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Designator
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Port 0 RGMII RJ-45 with Integrated 10BASE-T / 100BASE-TX / 1000BASE-T connection to
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Magnetics 88E1510 via 3.3V RGMII interface.
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Ports 1 - 8 RJ-45 with Discrete Magnetics 10BASE-T / 100BASE-TX / 1000BASE-T connection to

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internal PHYs
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Port 9 SERDES SFP+

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Port 10 SERDES

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Port 0 SERDES SFP+ USXGMII, 10GBASE-R, 5GBASE-R, 2500BASE-

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X,1000BASE-X, SGMII

16 ch
Note Port 0 can be used in RGMII mode or SERDES
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Mode. By Default, Port 0 is configured in RGMII mode.
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Port 0 can be changed to SERDES mode by changing

C_MODE in port register 0x0

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Aux SMI RJ-11 Used with the Marvell GUI to connect to customer board
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to assist with debugging or for an external CPU to
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manage the Switch. See Section 3.1 for more

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information.
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When the USB interface is connected to a USB host,

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This connector is connected to Channel 2 of on-board

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USB-2-SMI adaptor
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When the USB interface is not connected to a powered

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host this connector is connected MDC_CPU and

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MDIO_CPU via relays.

SMI_PHY RJ-11 Connected to MDC_PHY and MDIO_PHY. This is used
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when an external PHY needs to be managed via the

switch.
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USB USB Type B This interface is used to connect for the Marvell
Proprietary USB-2-SMI adaptor, it can be used with a PC
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running Microsoft Windows or Linux Operating System.

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The USB-2-SMI adaptor exposes two master SMI

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busses. Channel 1 is connected to the 88E6393X

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Channel 2 is connected to the Aux SMI.

5-12 VDC Standard DC power connector Main power to the development board.
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Table 2: Switch 3, Eight Position Dip Switch

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Dip Switch Mode Mode Definition

16 ch
Position

12 n Te
POSITION [8:7] S_MODE[1:0] SMODE for Port 9 and Port 10.
Off = 1

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On = 0

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The SMODE is set after the board is reset. The
mode of Port 9 and Port 10 is set together. These

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can be changed by changing the C_MODE in port
Register 0x0 via the switch GUI.

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POSITION [6:5] ADDR[1:0]n
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Off = 1
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On = 0
When SMI address = 0 The Board is configured in
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Single chip Addressing mode

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When Switch 6:5 are set to:
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Off/Off = The device will be configured to address
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0x00 (Single chip Addressing Mode)

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Off/On = 0x01
On/Off = 0x02
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On/On = 0x03

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POSITION 4 Not Used

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POSITION 3 LED_SEL Selects one of two preset LED modes.

54 n
16 ch
Off = LED Config = 0x3
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On = LED Config = 0x2
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Refer to Table 6 and Table 7 for details.

LED modes can be changed with register access.

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POSITION 2 SW-24P Configures device for three chip ring topologies for
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which Ports 9 and 10 are used to establish the ring.
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Off = SW-24P is disabled

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On = SW-24P is enabled
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POSITION 1 FLOW Configures the internal PHYs to advertise Flow

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Control via PHY Page 0, Register 4 bit 10

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Off = Do not advertise Flow Control

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On = Advertise Flow Control

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Table 3: Switch 2, One Position Slide Switch

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Mode Mode Definition

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CPU_MGD CPU managed mode.

On = 1
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Off = 0
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When CPU managed is 1 after reset, all the internal PHYs will be in a
powered down state (Page 0, Register 0 bit 11 =1). The SERDES cores
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will be in a Power-Down state (Device 4 register 0x1000=1). All ports will

be in a PortState = Disabled (Port Register Offset 0x4 bits 1:0 = b’11)
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Table 4: SMA Connectors

54 n
Connector Connector Function

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GPIO9 - GPIO12 Multi-purpose pins that can be used for programable functions.

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SE_SCLK 25 MHz Clock input from clock synchronous Ethernet clock source.

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3.1. I/O Interfaces

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Auxiliary SMI
This board includes an Auxiliary SMI interface that can be connected to a customer board or a Management

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device. This allows the Marvell SwitchGUI to aid in debug and bring up of new designs using the device.
, U 2rc
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The port will operate in one of two modes depending on whether the development board is connected to a host
PC:
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• If the development board is connected to a PC, Port 1 of the onboard USB-2-SMI adapter is connected
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to the 88E6393X and Port 2 is connected to the AUX_SMI jack.
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• If the development board’s USB Connector is not connected to a PC (i.e., no power), then the board
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goes into USB Bypass mode and connects the AUX_SMI connector to the 88E6390X device’s

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MDC_CPU/MDIO_CPU interface. This is to allow an external processor to manage the board modifying

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the board.
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54 n
16 ch
The RJ-11 has the following pinout when used with the onboard USB-2-SMI adapter:
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PIN Signal
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2 MDIO

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3, 4 Signal Ground
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When in USB Bypass mode the connector is configured as:

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PIN Signal
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2 MDC
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3, 4 Signal Ground
5 MDIO
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WARNING: While managing the board in USB Bypass mode, do not connect the USB cable.
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Connecting the USB cable will connect the USB-2-SMI adapter to the external management device and
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may damage one or both devices.

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The Auxiliary SMI interface uses 3.3V I/O. Please use care when connecting to another board to ensure
that its corresponding MDC/MDIO interface also uses 3.3V I/O. The Auxiliary SMI connection is
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accessed via SMI Port 2.

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PHY SMI RJ-11

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PHY SMI connector can be used to connect an external PHY MDC_PHY and MDIO_PHY. If the PHY has a
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standard IEEE defined Clause 22 register interface it can be managed by the PPU. If the PHY has a non-
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standard register interface, it can be managed by firmware running on the Internal Management processer (IMP)
or a CPU.
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57 olo
4. Cables

54 n
16 ch
One or more cables are required in order to use the development board. A listing of the appropriate cable for

12 n Te
each connector type is indicated in Table 5.

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Table 5: 88E6320/88E6321 Development Board Cables

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Connector Type Cable
RJ-45 Straight, Category 5 (CAT5), Unshielded Twisted Pair (UTP), with RJ-45 plug

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ends
Power DC power, 5V, positive polarity supplied to the center pin

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USB slave port USB 2.0 A/B cables
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EN 3y

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5. Switches and LEDs

54 n
16 ch
5.1. Power and Fuses

12 n Te
Power is supplied to the development board via the DC power jack, J3. A 5V, 3.0A minimum, DC power supply
is required. LED D30 indicates power is present at the power jack. A 5A fuse (F1) links the power jack and the

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on-board 5V power net.

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NOTE: if F1 is blown, LED D30 will not illuminate even if power is present at J3.

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5.2. LEDs
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The 88E6390X switch features 20 LED’s and has user configurable LED modes. The two default modes are
configured by hardware configuration (LED_SEL). Table 6 and Table 7 show the default behavior of each LED
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based on the settings of SW11 [2:1].

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Table 6: SW11 [1] = [OFF] (LED Config = 0x3)
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C0_LED C1_LED C2_LED C3_LED
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R0_LED Port 1 Link/Activity Port 1 Gig Link Port 2 Link/Activity Port 2 Gig Link
R1_LED Port 3 Link/Activity Port 3 Gig Link Port 4 Link/Activity Port 4 Gig Link
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R2_LED Port 5 Link/Activity Port 5 Gig Link Port 6 Link/Activity Port 6 Gig Link

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R3_LED Port 7 Link/Activity Port 7 Gig Link Port 8 Link/Activity Port 8 Gig Link
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R4_LED Special LED 1 Special LED 4 Special LED 2 Special LED 3

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54 n
LAN Link/Activity PTP Activity WAN Link/Activity CPU Link/Activity

16 ch
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Table 7: SW11 [1] = [ON] (LED Config = 0x2)

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C0_LED C1_LED C2_LED C3_LED

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R0_LED Port 1 Gig Port 1 10/100 ND xvi

Port 2 Gig Port 2 10/100
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Link/Activity Link/Activity Link/Activity Link/Activity

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R1_LED Port 3 Gig Port 3 10/100 Port 4 Gig Port 4 10/100

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Link/Activity Link/Activity Link/Activity Link/Activity

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R2_LED Port 5 Gig Port 5 10/100 Port 6 Gig Port 6 10/100

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Link/Activity Link/Activity Link/Activity Link/Activity

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R3_LED Port 7 Gig Port 7 10/100 Port 8 Gig Port 8 10/100

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Link/Activity Link/Activity Link/Activity Link/Activity

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R4_LED Special LED 3 Special LED 2 Special LED 4 Special LED 1

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CPU Link/Activity WAN Link/Activity PTP Activity LAN Link/Activity

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INTn LED
The INTn LED is connected to the INTn signal. The LED will be turned on when there is an un-serviced interrupt.
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By default, the INTn LED will light up after the board is reset. This indicates the EEDone interrupt has been
posted and is cleared as soon. The EE_DONE interrupt can be cleared by reading Global 2 Offset 0x13.
LL 0a
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SERDES LEDs
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Each SFP+ cage has an LED which indicates that there is a module inserted.
M 28k
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57 olo
6. EEPROM

54 n
16 ch
The development board has an on-board socket labeled U5 can accommodate a 2-wire serial Electrically

12 n Te
Erasable Programmable Memory (EEPROM). The EEPROM can be used to load an operating image into the
Internal Management processor. Supported EEPROM families include: 24C64, 24C128, 24C256, 24C512.

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Similar devices from different manufacturers may also be used. The Marvell IMPGui is the only supported
method for developing EEPROM code. Most CPU managed applications do not require an EEPROM image.

ND xvi
E R Ma
Another EEPROM labeled U16 is used for the USB circuitry. Do not change the contents of this EEPROM as the
USB circuitry will not function properly unless otherwise instructed.

ND i *
, U 2rc
This chip is capable of programming the EEPROM via switch registers. Please see the GUI users’ guide and the
Functional Specification for more information about programming the EEPROM.
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7. Software tools
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The board can be managed from a standard Windows 7 or Windows 10 PC via the USB-2-SMI adaptor. The
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following tools are available from extranet.marvell.com:
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Table 8: Marvell Switching Tools

57 olo
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Tool Description Extranet Folder

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54 n
SwitchGUI A graphical user interface that be

16 ch
My Products Switching Link Street
used to access switch registers Data
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12 n Te
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Structures and counters SOHO Switch Family SwitchGUI

IMPGui Integrated Development Environment

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My Products Switching Link Street

for EEPROM code and operating
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images ND xvi
SOHO Switch Family Gigabit Ethernet
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UMSD_MCLI A command line interface built over

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Switches 88E6393X/88E6193X/88E6191X
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UMSD driver package

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UMSD An OS independent driver package (Amethyst) Software

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used for configurating the switch and

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accessing data structures.

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57 olo
54 n
16 ch
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No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the
express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied,
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with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does
not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.
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Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in
these types of equipment or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations
COm0

("EAR"), to a national of EAR Country Groups D:1 or E:2;

2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for
LL 0a

national security reasons by the EAR; and,

3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to
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EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to
controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such
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information.
M 28k

Copyright © 2019. Marvell International Ltd. All rights reserved. Marvell and the Marvell logo are registered trademarks of Marvell. For a more complete listing of Marvell trademarks, visit
www.marvell.com.
Patent(s) Pending - Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
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