1

EE 560 COMBINATIONAL MOS LOGIC

CIRCUITS
STATIC AND DYNAMIC CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania

 VDD 2

V1
Vout is Boolean
V2 function of inputs ,
V3 COMBINATIONAL Vout
M LOGIC CIRCUIT V1, V2, V3, ...., Vn.
Vn Cload “1” => VDD
“0” => 0

VDD

Load Net CMOS => pMOS Logic

Pull-Up Net
Vout
V1
nMOS Logic
V2 Cload
M Driver Net
Vn Pull-Down Net
Kenneth R. Laker, University of Pennsylvania
 3

MOS LOGIC CIRCUITS WITH DEPLETION LOADS

2-INPUT NOR GATE
VDD A
Z=A+B
VGS,L = 0 + (W/L) B
L
-
IDL
Vout VA VB Vout
(W/L)A I I
DA DB LOW LOW HIGH
VA VB LOW HIGH LOW
(W/L)B
HIGH LOW LOW
HIGH HIGH LOWER

Kenneth R. Laker, University of Pennsylvania

 4
VDD Vout dVout Vout = Vin - VT0,n
+ (W/L) =-1
VGS,L = 0 dVin SAT LIN
L VOH
- LIN B
IDL VDD + VT,L
Vout SAT D
C
(W/L)A I I A dVout
DA DB =-1
VA VB dVin
(W/L)B VOL
Vin
VIL VIH VOH
IDL = IDA + IDB VT0,n
(ASSUME VT0nA = VT0nB = VT0n)
CALCULATION OF VOH
WHEN VA = VB = 0 => IDA = IDB = 0
k 'n , L  W 
IL =   [ 2(0 − VT,L (VOH ))(VDD − VOH ) − (VDD − VOH )2 ] = 0
2 L L
VOH = VDD same as INV
Kenneth R. Laker, University of Pennsylvania
 VDD
Vout dVout Vout = Vin - VT0,n5
VGS,L = 0 +(W/L)L =-1
VOH dVin SAT LIN
-IDL B
Vout LIN
VDD + VT,L
(W/L)B IDA
IDB SAT D
VB VA
(W/L)A C
A dVout
=-1
dVin
IDL = IDA + IDB VOL
Vin
VT0,nVIL VIH VOH
CALCULATION OF VOL
i) VA = VOH, VB = VOL
ii) VA = VOL, VB = VOH 3 CASES FOR Vout = VOL
ii) VA = VOH, VB = VOH
i) and ii) => NOR Reduces to INV
VOL = VOH − VT 0,n − (VOH − VT 0 , n ) − [ − VT,L (VOL )]
2 1 2

kR
k'n,d (W/L )d
kR = '
Kenneth R. Laker, University of Pennsylvania k n , L(W/L ) L
 6

(VOH − VT 0 , n) − [ − VT,L (VOL )]

2 1 2
VOL = VOH − VT 0,n −
kR
WHERE'
k n , d( W/L )A
kR = ' for CASE i) IDA ≠ 0, IDB = 0
k n , L(W/L ) L
k 'n,d ( W/L) B
kR = ' for CASE ii) IDA = 0, IDB ≠ 0
k n , L(W/L ) L

CASE iii) VA = VOH, VB = VOH IDA ≠ 0, IDB ≠ 0

IDL = IDA + IDB
VOH
k'n , L  W  k 'n , d  W 
2 L L   [ − VT,L (VOL ) ] =
2 L A   [2(V A − VT 0,n )VOL − (VOL ]
) 2

' VOH
k n,d  W
+
2 L B   [ 2(VB − VT0,n )VOL − (VOL ) 2
]

Kenneth R. Laker, University of Pennsylvania

 7

(VOH − VT 0 , n) − [ − VT,L (VOL )]

2 1 2
VOL = VOH − VT 0,n −
kR
WHERE
k 'n,d [( W/L) A + ( W/L )B ] EQUIV DRIVER-LOAD
kR = RATIO FOR 2-INPUT NOR
k'n,L ( W/L )L

NOTE: VOL,iii < VOL,i = VOL,ii

WORST CASE CONTITION FOR VOL => CASES i) and ii)

Kenneth R. Laker, University of Pennsylvania

 8

WORST CASE CONTITION FOR VOL => CASES i) and ii)

TO DESIGN 2-INPUT NOR GATE FOR A SPECIFIED VOL

(VOH − VT 0 , n) − [ − VT,L (VOL )]

2 1 2
VOL = VOH − VT 0,n −
kR

SOLVE FOR kR:

[− VT,L (Vout )]
2
k ( W/L )A k ( W/L )B
' '

kR = n,d
= = n,d

k (W/L ) L k ( W/L )L 2(VOH − VT 0 , n)VOL − ( VOL )

' ' 2
n,L n,L

k R k 'n , L
( W/L )A = (W/L ) B = ' ( W/L )L
k n,d

Kenneth R. Laker, University of Pennsylvania

 9
GENERALIZED NOR STRUCTURE
VDD
VGS,L = 0 + (W/L)
L
-
IDL
Vout
(W/L)1 IDn
ID1 ID2
V1 V2 L Vn
(W/L)2 (W/L)n

k'n,d  W 
∑
m(ON) 2  L  m
2(VGS,m − V[ )V
T 0,n out − (Vout ) 2
] LIN

I DL = k'n,d  W 
∑
m(ON) 2  L  m
(VGS,m − V [
T 0,n ) 2
] SAT

GEQV = ΣGm = mG for m(ON)

Kenneth R. Laker, University of Pennsylvania
 k'n,d  W 
[ ]
10
2
∑ 2(V − V )V − (V ) LIN
2  L  m
GS,m T 0,n out out
m(ON)
I DL = k'n,d  W 
∑
m(ON) 2  L  m
(VGS,m − VT 0,n[) 2
] SAT

ASSUMING ALL nMOS DRIVERS ARE IDENTICAL,

VGSm = VGS for all m

k'n,d  W 

[
 ∑    2(VGS − VT 0,n )Vout − (Vout )2 LIN
2  m(ON) L m 
]
V DD
I DL = k' 
n,d  W  + (W/L)
 ∑    (VGS − VT 0,n )2 SAT L
2  m(ON) L m  -
Vout
 W =  W  W
∑   =m
 L  EQV m(ON) L m  L Vin (W/L)EQV

Kenneth R. Laker, University of Pennsylvania (W/L)k = (W/L) for all k

 TRANSIENT ANALYSIS OF 2-INPUT NOR 11

VDD
For all Input Conditions:
✓ CgdL CdbL
Cload = CgdA + CgdB + CgdL+ CdbA + CdbB
D + CsbL + Cint + Cgb
G B Note:
CsbL ✓ Cload-NOR > Cload-INV
S
Vout

✓ CgdA ✓
✓ CgdB
D CdbA ✓ D CdbB
VA G B G B ✓ ✓
VB Cint
Cgb
S S
CgsA CsbA CgsB CsbB

Kenneth R. Laker, University of Pennsylvania

CL
 VDD 12

VGS,L = 0 + (W/L)
L
-
iDL
Vout
iC
(W/L)A i iDB
DA Cload
VA VB
(W/L)B
iC= iDL- iDA- iDB

Recall for the INV:

For the n-input NOR:

Cload-INV -> Cload-NOR
kn -> mkn for m of n inputs switching simultaneously
VOL-INV -> VOL -NOR
Kenneth R. Laker, University of Pennsylvania
 13
2-INPUT NAND GATE
VDD A
VGS,L = 0 + (W/L) Z = AB
L B
-
IDL
Vout
VA VB Vout
(W/L)A IDA
VA IDL = IDA = IDB
LOW LOW HIGH
3 cases LOW HIGH HIGH
(W/L) I
B DB HIGH LOW HIGH
VB HIGH HIGH LOW

CALCULATION OF VOH
WHEN VA = 0 and/or VB = 0 =>IDL = IDA = IDB = 0
VOH = VDD FOR ALL 3 INPUT CASES
Kenneth R. Laker, University of Pennsylvania
 CALCULATION OF VOL = VDSA + VDSB: VA = VB = VOH 14

VDD
Where kn,dA = kn,dB = kn,d
(W/L)L
- IDL FOR THE INV
Vout dVout VDS = VGS - VT0,n
Vout
(W/L)A =-1
IDA dVin SAT LIN
VA VOH
VBSA ≠ 0 LIN B
(W/L)B IDB VDD + VT,L
VB SAT D
C
A dVout
=-1
IDL = IDA = IDB dVin
VOL
k'n,L  W  Vin
2  L L
[ − VT,L (VOL )] VT0,nVIL VIH VOH

k'n,d  W 
=
2  L A
2(V GSA − V [ )V
T,nA DSA − (VDSA ) 2
]
k'n,d  W 
=
2  L B
2(V GSB − V [ )V
T,n B DSB − (VDSB ) 2
]
Kenneth R. Laker, University of Pennsylvania
Some SIMPLIFYING assumptions: 15

1) VGSA = VGSB = VOH

2) NEGLECT VBSA; i.e. VTnA = VTnB = VT0n
where
k'n,L  W 
2  
L L
[ − VT,L (VOL )]
VOH VT0n
k'n,d  W 
=
2  L
2(VGSA − V [
)V
T,nA DSA − (VDSA ) 2
]
VDSA = VOH − VT 0,n − (VOH − VT 0,n ) 2
−
1
kR
[ − VT,L (VOL )]
2

k'n,L  W 
2  
L L
[ − VT,L (VOL )]
k'n,d  W 
=
2  L
2(VGSB − V[ )V
T,nB DSB − (VDSB ) 2
]
VDS B = VOH − VT 0,n − (VOH − VT 0,n ) − [ − VT,L (VOL )]
2 1 2
kR
Kenneth R. Laker, University of Pennsylvania
 16

VDSA = VD S B = VOH − VT 0,n − (VOH − VT 0,n ) − 2 1

kR
[ − VT,L OL ]
(V )
2

 2
VOL = 2  VOH − VT 0,n −

(VOH − VT 0,n ) 2
−
1
kR
[ − VT,L (VOL )] 


INV

MORE ACCURATE Analysis: let’s remove assumption VGSA = VGSB

When both driver transistors are in the linear region:
k'n,d  W 
IDA =
2  L
2(VGSA − V [
T 0,n )VDSA − (VDSA ) 2
]
k'n,d  W 
IDB =
2  L
2(VGSB − V[ )V
0,n DSB
T,nB − (VDSB ) 2
]
It is convenient to express
I DA + I DB
I D = I DA = I DB =
2
Kenneth R. Laker, University of Pennsylvania
 VDD
I DA + I DB 17

(W/L)L I D = I DA = I DB =
2
- IDL k'n,d  W 
(W/L)A IDA
Vout
IDA =
2  L
[ 2(VGSA − V T 0,n )VDSA − (VDSA ) 2
]
VA = VOH G D

k'n,d  W 
[ ]
S
IDB IDB = 2
2(V − V )V − (V )
2  L 0,n DSB
D GSB T,nB DSB
VB = VOH G
(W/L)B S
SUBSTITUTING VGSA = VGSB - VDSB
(VGSA + VDSB - VGSB = 0)
k'n,d  W 
ID =
4  L
2(V GSB − V [
T 0,n )( VDSA + VDSB ) − (VDSA
VDD
+ VDSB ) 2
]
LET VGSB = VGS and VDS = VDSA + VDSB + (W/L)
L
k'n,d  W 
ID =
4  L
[ 2
2(VGS − VT 0,n )VDS − VDS ] -
Vout
 W 1  W Vin
 L  EQV = 2  L  d
(W/L)EQV

Kenneth R. Laker, University of Pennsylvania

 VDD 18

+ (W/L)  W 1  W
L  L  EQV = 2  L d
-
FOR DESIGN:
Vout
1. Determine (W/L)L and (W/L)EQV
Vin (W/L)EQV 2. Set (W/L)dA = (W/L)dB = 2(W/L)EQV

INV WITH ONE DRIVER nMOS (W/L)d :

2-INPUT NAND GATE WITH TWO nMOS (W/L)d:

 19
GENEARALIZED NAND GATE
VDD
VGS,L = 0 + (W/L)
L
-
IDL
Vout
(W/L)1 ID1
Vin
1
(W/L)2 ID2 GEQV = = 1
ΣRm Σ1/Gm
Vin n n
1 G
(W/L)n = =
IDn n(1/G) n
Vin for all n(ON)

Kenneth R. Laker, University of Pennsylvania

 20

 
'

k n,d  1


[2(Vin − VT 0,n )Vout − (Vout ) 2 ] LIN
ID =
2  ∑ 1 
(Vin − VT 0,n )2
 n(ON)  W   SAT
  L n

 W 1
 L  EQV = 1
∑ W
n(ON)  
 L n
FOR (W/L)1 = (W/L)2 = ..... = (W/L)n
 W 1 1  W
 L  EQV = n = n L 
 W
 L
Kenneth R. Laker, University of Pennsylvania
 21

 W =
1  W
 L  EQV n  L 

n-INPUT NAND DESIGN STRATEGY

-> Find (W/L) ratios for EQV INVERTER to satisfy VOL SPEC
YIELDS: (W/L)L, (W/L)EQV.

-> Set (W/L)1 = (W/L)2 = -- = (W/L)n = n(W/L)EQV.

WHERE for INV

Kenneth R. Laker, University of Pennsylvania

 NOR VDD 22

TRANSIENT CgdL✓✓ CdbL

ANALYSIS
D
G B

S CsbL✓
✓ Vout

✓
✓CgdA
VA = VOH D CdbA✓
✓
VA
G B ✓
✓
VA = VOH -> VOL ✓CgsA ✓
CsbA Cint✓
✓ Cgb
S
✓CdbB Vx C ✓
gdB
VB = VOH -> VOL D
G B
VB
VB = VOH
S Vx -> rises
Vx -> low

Kenneth R. Laker, University of Pennsylvania

 ✓ VDD 23
✓CgdL CdbL
D
G B

S CsbL ✓
✓ Vout

VA = VOH ✓✓CgdA D CdbA✓✓

VA G B ✓✓
VA = VOH -> VOL ✓CgsA Vx ✓
CsbA Cint ✓✓ Cgb
S

VB = VOH -> VOL ✓ CgdB ✓

CdbB
D
G B
VB
VB = VOH Vx -> rises
S
Vx -> low
Vx = RISE (LONGER DELAY CASE)
Cload = CgdL + CsbL + CgdA + CgsA + CdbA + CsbA + CgdB + CdbB + Cint + Cgb
Vx = LOW (SHORTER DELAY CASE)
Cload = CgdL + CsbL + CgdA + CdbA + Cint + Cgb τPLHB > τPLHA
INPUT SWITCHING ORDER: APPLY LATEST ARRIVING
INPUT SIGNALS TO DRIVE TRANSISTORS CLOSEST TO Vout.
Kenneth R. Laker, University of Pennsylvania
 CMOS LOGIC GATES 24

2-INPUT NOR (NOR2)

VDD

S VDD
G B

D VA
pMOS
S
G B
VB Logic
VB
IDp Vout
D
Idp Vout
IDn
VA nMOS
D
IdnA
D
IdnB Logic
G G VB
VA B B
S S

nMOS Net ON, pMOS Net OFF

or
nMOS Net OFF, pMOS Net ON
Kenneth R. Laker, University of Pennsylvania
 VDD FOR THE INV 25

S
Vout A B C D E
G B
VDD LIN Vin - VT0p
D
S
VB G B SAT Vin - VT0n
D Idp Vout SAT
VDD/2
D IdnB LIN
D
IdnA G
VA G
B B
S S - VT0p
Vin
0 VT0n VDD/2
--> VOL = 0, VOH = VDD. VDD+VT0p VDD

DEFINITION Vth: VA = VB = Vout = Vth

ASSUME:
1) VA and VB switch simultaneously
2) Assume SUB bias effect for pMOS transistors is negligible.
3) (W/L)nA = (W/L)nB
4) (W/L)dA = (W/L)dB
Kenneth R. Laker, University of Pennsylvania
 VDD 26

M3
DEF: VA = VB = Vout = Vth
S
G
VA B
IDpA => VDSnA = VDSnB = VGSnA = VGSnB
D
M4 S Vx VDSn > VGS - VTn -> M1 & M2 SAT
G
VB B

D IDpB Vout
ID => VDSpB = Vout - Vx = VGSpB (for VB = Vout)
M1 M2 D IDnB VDSpB < VGSpB -VTp -> M4 SAT
D IDnA G
VA G VB
B B
S S => VDSpA =Vx - VDD
VGSpA = Vout - VDD <VTpA(for VA = Vout)
VDSpA > VGSpA - VTp -> M3 LIN

 kn 2
I D = I DnA + I DnB = 2  ( Vth − VTn )  = k n (Vth − VTn )
2

2 
I
Vth = VTn + D
kn
Kenneth R. Laker, University of Pennsylvania
 [
2(Vth − VDD − VTp ) VDSpA − VDSpA 2 ]
kp 27
I DpA =
2
I Dp B = ( Vth − VDD − VDSpA − VTp )
kp 2

2
ID = IDpA = IDpB

IDpA = IDpB =>

2(Vth − VDD − VTp ) VDSpA − VDSpA = ( Vth − VDD − VDSpA − VTp )
2 2

= VDSpA − 2(Vth − VDD − VTp ) VDSpA + ( Vth − VDD − VTp )

2 2

SOLVING FOR VDSpA:

VDSpA 
= 1+

1
2  ( Vth − VDD − VTp )

SUBSTITUTING VDSpA INTO IDpB:

ID
Vth − VDD − VTp = −2
kp
Kenneth R. Laker, University of Pennsylvania
 28
ID FROM ID = IDnA + IDnB
Vth = VTn +
kn
ID FROM ID = IDpA = IDpB
Vth − VDD − VTp = −2
kp

ID ID
VTn + − VDD − VTp = −2
kn kp

SOLVING FOR I D
 1 2  2  1 kp 
ID =  +  ( VDD − VTn + VTp ) = 1 +  (VDD − VTn + VTp )
kp  2 kn 
 kn kp 
SUBSTITUTING I D INTO I D = k n ( Vth − VTn )

( VDD + VTp )
kp
VTn +
1 kp
2 kn
( VDD + VTp ) VTn +
kn
Vth (NOR 2) = Vth (INV) =
1 kp kp
1+ 1+
2 kn kn
Kenneth R. Laker, University of Pennsylvania
 1 kp
( VDD + VTp ) ( VDD + VTp )
kp 29
VTn + VTn +
2 kn kn
Vth (NOR 2) = Vth (INV) =
1 kp kp
1+ 1+
2 kn kn
kp = kn and VTn = |VTp| => Vth(INV) = VDD/2
= 2.5 V for VDD = 5V, VTn = 1V
VDD + VTn
Vth (NOR 2) = = 2.0 V for VDD = 5V, VTn = 1V
3
VDD
VDD
VA G
S Symmetrical
kp S

D
G
kp/2 EQUIV INV
VB G
S D kp/2 = 2kn
kp Vin Vout
D Vout D
G
2kn
D S
D
Vin G
kn G
kn
VA VB S
S
VTn = |VTp|: Vth(NOR2) = VDD/2 => kp = 4kn
Kenneth R. Laker, University of Pennsylvania
 30
PARASITIC CAPACITANCES FOR CMOS NOR2
VDD

M3 S
G B
VA Cgd3 ✓ D
✓ Cdb3

Cgs4 ✓ S M4 C
VB
G B ✓ sb4
Cgd4 ✓ Cdb4 Vout
✓ D

Cint Cgb
Cgd1 Cgd2 ✓
D ✓ ✓G D
✓G Cdb1 Cdb2
VA VB B
B
M1 S
M2 S

WORST CASE:
Cload = Cgd1 + Cdb1 + Cgd2 + Cdb2 + Cgd3 + Cdb3 + Cgd4 + Cdb4
+ Cgs4 + Csb4 + Cint + Cgb
Kenneth R. Laker, University of Pennsylvania
 CMOS NAND2 31

VDD
VDD
VA S VB S
G
kp G
kp S
D D G
2kp
Vout D

Vin Vout
VA D D
G
kn G
S
Symmetrical kn/2
S
Vin VB D EQUIV INV
G kn 2kp = 2kn/2
S

( VDD + VTp )
kp
VTn + 2
kn
Vth (NAND 2) =
kp
1+ 2
kn
VTn = |VTp|: Vth(NAND2) = VDD/2 => kn = 4kp
Kenneth R. Laker, University of Pennsylvania
 Vout,Vin MACROMODELING 32
Vout
CL = 0
5V Vout
CL = 0.5 pF
3V 0.5 pF
CL = 1.0 pF Vout
1V input
t 1.0 pF
10 ns 20 ns 30 ns Vin
τPLH = τint,LH + CL × τext,LH τPLH = 0.26 +CL × 2.12 ns
τPHL = τint,HL + CL × τext,HL τPHL = 0.42 + CL × 3.88 ns
Load Conditions
τPXY
Time CL = 0 CL = 0.5 pF CL = 1.0 pF
τPLH (ns) 0.26 1.32 2.38
τint,XY slope = τext,XY τ (ns)
PHL
0.42 2.36 4.30
CL
0 τext,LH (ns/pF) 0 2.12 2.12
τint,XY = τPXY|CL = 0
τext,HL (ns/pF) 0 3.88 3.88
Kenneth R. Laker, University of Pennsylvania
 33
TYPICAL CMOS NAND AND NOR DELAYS
Delays for a Family of NAND & NOR gates
1. Wn = 6.4 µm, Ln = 1 µm, and Wp = 12.8 µm, Lp = 1 µm.
2. tinput-rise/fall = 0.1 ns and Cload = 0 -> 1 pF.

a
c b τPHXY (ns) τPHXY (ns)
e d z
g f 10.0 10.0 NR8-LH
h ND8-HL
a
c b ND8-LH NR8-HL
e d z 0 CL (pF)
g f 0
0.75
CL (pF) 0.25 0.75
h 0.25

τPHXY (ns)
5.0
z z INV-HL
INV-LH
0 CL (pF)
0.25 0.75
Kenneth R. Laker, University of Pennsylvania
 34

COLOR LEGEND
VDD VDD n-Well
S p-Well
G
VA kp n+
D
S
Polysilicon
VB G
kp Vout p+
D Vout
Gate Oxide
Field Oxide
D D GND Metal 1
VA G
kn VB G
kn VA VB Metal 2
S S
Metal 3
VDD
Contact/via

STICK DIAGRAM Vout

GND
VA VB
Kenneth R. Laker, University of Pennsylvania
 VDD COLOR LEGEND 35

n-Well
S S
G p-Well
VA kp VB
G
kp
D
n+
D

Vout Polysilicon
p+
D
VA G Gate Oxide
kn
S Field Oxide
Metal 1
D
VB G kn Metal 2
S Metal 3
VDD
Contact/via

Vout

GND
Kenneth R. Laker, University of Pennsylvania
VA VB
 COMPLEX LOGIC GATES 36

Z = A(D + E) + BC
“OR” OPS PERFORMED BY PARALLEL CONECTED DRIVERS.
“AND” OPS PERFORMED BY SERIES CONNECTED DRIVERS.
“INVERSION” IS PROVIDED BY NATURE OF MOS CIRCUIT OP.
VDD
VGS,L = 0
(W/L)L
Vout

A (W/L)A B (W/L)B

D E C (W/L)C
(W/L)D (W/L)E

Kenneth R. Laker, University of Pennsylvania

 37
VDD
VGS,L = 0 ON Drivers Out-GND Path
(W/L)L
A-D Class 1
Vout A-E Class 1
B-C Class 1
A-D-E Class 2
A (W/L)A B (W/L)B A-D-B-C Class 3
A-E-B-C Class 3
D E C (W/L)C A-D-E-B-C Class 4
(W/L)D (W/L)E G1 < G2 < G3 < G4
VOL1 > VOL2 > VOL3 > VOL4

EQV INVERTER (for case G4 where A = B = C = D = E = 1)

 W 1 1
 L  EQV = 1 1 + 1 1
+ +
 
W  
W  
W  W +  W
 L B  L  C  L  A  L D  L E
Kenneth R. Laker, University of Pennsylvania
 38
VDD
DESIGN STRATEGY:
VGS,L = 0 1. Identify all WORST CASE
(W/L)L Paths (e.g. Class 1).
Vout 2. Determine nMOS
transistor sizes such that
each Class 1 path has
A (W/L)A B (W/L)B (W/L) .
EQV

D E C (W/L)C
(W/L)D (W/L)E
 W  =  W  = 2 W 
 L A  L D  L  EQV
 W  =  W  = 2 W 
 L A  L  E  L  EQV

 W  =  W  = 2 W 
 L B  L  C  L  EQV
Kenneth R. Laker, University of Pennsylvania
 VDD 39

OPTIMIZED LAYOUT OF COMPLEX

D FULL CMOS GATES
A E
B C
Z = A(D + E) + BC

A B
D E C
ARBITRARY STICK LAYOUT
VDD
D S S D S D
D S S D
Z

D S D S D S D S S D
GND

A E B D C
 40
OTIMIZED LAYOUT OF COMPLEX FULL CMOS GATES
VDD VDD
D
D A pMOS NET
GRAPH
E
A E
B C

B C Z
Z Z
B
A
A B nMOS NET
GRAPH
D E
D E C C
GND

Kenneth R. Laker, University of Pennsylvania

 41
OTIMIZED LAYOUT OF COMPLEX FULL CMOS GATES
VDD
VDD Z
D
B
A A
D
E
D E
A E C
B C
GND
Z
B C Z
Z A
B
A B VDD Z
D E
C
D E C

GND
Kenneth R. Laker, University of Pennsylvania
 ARBITRARY ORDERING OF GATE COLUMNS 42
VDD
D S S D S D
D S S D
Z

D S D S D S D S S D

D C GND
A E B
Z
A Euler path - connected
B sequence of edges
VDD n, p diffusions for Euler
Z
D paths can have layout with
E
C out diffusion breaks.

GND
Kenneth R. Laker, University of Pennsylvania
 MINIMIZE NUMBER OF DIFFUSION BREAKS 43

VDD Z

D A
B
A COMMON
x E EULER PATH: x
y E-D-A-B-C D E
C
B C
y
Z GND
VDD

D S D S S D S D D S
Z
D S S D S D D S D S
GND
E D A B C
Kenneth R. Laker, University of Pennsylvania
 44

ALGORYTHYM FOR LINE OF GATES LAYOUT STYLE

1. Find all Euler paths that cover the graph.
2. Find n- and p- Euler paths that have identical labeling (i.e.
gate labels).
3. If no Euler paths are found in step 2, break the gate in the
minimum number of places that to achieve step 2 with
separate Euler paths.

Kenneth R. Laker, University of Pennsylvania

 FULL CMOS XOR GATE 45

A A + B = AB + AB VDD

B
A B

A B
Vout
A +B
A
A A
B
B B

Kenneth R. Laker, University of Pennsylvania

 46
AOI & OAI GATES
AOI -> AND-OR-INVERT (for SUM - of - PRODUCTS Realization)
OAI -> OR-AND-INVERT (for PRODUCT - of - SUMS Realization)
VDD
A1
A2 Dual pMOS
A3 Pullup Net
B1 Vout Vout
B2
C1
C2 A1
C B1 C1
3

AOI A2 C2

A3 B2 C3

Kenneth R. Laker, University of Pennsylvania

 47
OAI -> OR-AND-INVERT (for PRODUCT - of - SUMS Realization)
A1 VDD
A2
A3
B1 Dual pMOS
Vout Pullup Net
B2
Vout
C1 OAI
C1

B1 B2

A1 A2 A3

Kenneth R. Laker, University of Pennsylvania

 48
Pseudo-nMOS OAI Realization

VDD

Vout
C1

B1 B2

A1 A2 A3

Kenneth R. Laker, University of Pennsylvania

 49
CMOS Transmission Gates (TGs) & TG Logic

SYMBOLS
-s SWITCH CHARACTERISTICS

a C b a b
Input Output

s s a b Srong 0
0
-s -s
1 a b Strong 1

a b a b

s s

Kenneth R. Laker, University of Pennsylvania

 0V 50

ISDp G VDSn = VDD - Vout

ID = IDSn + ISDp VSBp = 0
ID VGSn = VDD - Vout
S B D
Vin = VDD Vout
D B S VDSp = Vout - VDD
IDSn VSBn = Vout VGSp = - VDD
G

VDD

REGION 1 REGION 2 REGION 3

nMOS: SAT nMOS: SAT nMOS: OFF
pMOS: SAT pMOS: LIN pMOS: LIN

Vout
0V |VTp| (VDD - VTn) VDD

VDD − Vout VDD − Vout

R eqn = R eqp = ReqTOT = Reqn||Reqp
I DSn I SDp
Kenneth R. Laker, University of Pennsylvania
 2( VDD − Vout ) 51

R eqn =
k n (VDD − Vout − VTn )
2
REGION 1:
2( VDD − Vout )
nMOS: SAT
pMOS: SAT R eqp =
k p ( VDD − | VTp |)
2

2( VDD − Vout )
REGION 2 R eqn =
k n (VDD − Vout − VTn )
2
nMOS: SAT
pMOS: LIN 2( VDD − Vout )
R eqp =
[
k p 2(VDD − | VTp |)(VDD − Vout ) − (VDD − Vout )
2
]
2
=
[
k p 2(VDD − | VTp |) − ( VDD − Vout ) ]
REGION 3 Reqn = ∞
nMOS: OFF 2
R eqp =
[ ]
pMOS: LIN
k p 2(VDD − | VTp |) − ( VDD − Vout )
Kenneth R. Laker, University of Pennsylvania
 52

Reqp Reqn

ReqTOT = Reqn||Reqp
Vout
0
(VDD - VTn) VDD

Kenneth R. Laker, University of Pennsylvania

 53

iSDp

Vin = VDD Vout

iC
iDSn
Cload

t=0

ReqTOT
Vin = VDD Vout
t=0 iC
Cload

Kenneth R. Laker, University of Pennsylvania

 54
2-INPUT MULTIPLEXER
output = A.s + B.s
-s
A B s -s output
A x 0 0 1 0 (B)
x 1 0 1 1 (B)
s
output 0 x 1 0 0 (A)
B 1 x 1 0 1 (A)

-s
XOR
A
B
A F = AB + AB

Kenneth R. Laker, University of Pennsylvania

 A A B B 55

F1 (AB)
VDD

F2(AB)
Z Z
F3 (AB)

F4 (AB)

SOME OF THE FUNCTIONS REALIZED BY THE

BOOLEAN FUNCTION UNIT
OPERATION (Z) F1 F2 F3 F4
NOR(A,B) 0 0 0 1
XOR(A,B) 0 1 1 0
NAND(A,B) 0 1 1 1
AND(A,B) 1 0 0 0
OR(A,B) 1 1 1 0
Kenneth R. Laker, University of Pennsylvania
 56

Simple and small,

poly used to achieve metal2 used to
but no metal lines achieve
horizontal metal1
can pass horizontal metal1
transparency
horizontally transparency
n+
Routing Gate Signals to Transmission Gate Poly

p+
Metal 1
Metal 2
Contact/via

horizontal, via vertical, via poly vertical, via metal1 straps

metal1 metal2 used to achieve vertical
Kenneth R. Laker, University of Pennsylvania metal1 transparency