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Datasheet
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Table of Contents
1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4 5.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 21
3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 22
4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 23
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 24
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 26
5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9 5.12.1Radiated Emissions . . . . . . . . . . . . . . . . . 27
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 ESD Protection and Latch-Up Immunity . . . . . . 11 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 28
5.7 Supply Current Characteristics . . . . . . . . . . . . . 17
5.8 External Oscillator (XOSC) and ICS
Revision History
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be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
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http://freescale.com/
The following revision history table summarizes changes contained in this document.
Related Documentation
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PTA0/ADP0
16-BIT MODULO TIMER TCLK
HCS08 CORE PTA1/ADP1
(MTIM16)
PTA2/ADP2
PORT A
CPU BDC
2-CH TIMER/PWM TPM2CH[1:0] PTA3/ADP3
MODULE (TPM2) PTA4/BKGD/MS
HCS08 SYSTEM CONTROL PTA5/IRQ/TCLK/RESET
RESETS AND INTERRUPTS
MODES OF OPERATION PTA6/TPM2CH0
RESET
POWER MANAGEMENT
IRQ PTA7/TPM2CH1
COP IRQ
INTERRUPT PRIORITY
LVD
CONTROLLER (IPC) PTB0/RxD/ADP4
PTB1/TxD/ADP5
ON-CHIP ICE AND
SERIAL COMMUNICATIONS TxD
DEBUG MODUE (DBG) RxD PTB2/ADP6
INTERFACE (SCI)
PORT B
PTB3/ADP7
USER FLASH
MC9S08FL16 — 16,384 BYTES PTB4/TPM1CH0
MC9S08FL8 — 8,192 BYTES
4-CH TIMER/PWM TPM1CH[3:0] PTB5/TPM1CH1
MODULE (TPM1) PTB6/XTAL
USER RAM
MC9S08FL16 — 1,024 BYTES
PTB7/EXTAL
MC9S08FL8 — 768 BYTES
PTC0/ADP8
20 MHz INTERNAL CLOCK
SOURCE (ICS) PTC1/ADP9
PTC2/ADP10
EXTAL
PORT C
EXTERNAL OSCILLATOR PTC3/ADP11
XTAL
SOURCE (XOSC)
PTC4
VDD PTC5
VSS VOLTAGE REGULATOR PTC6
PTC7
VREFH
VREFL 12-CH 8-BIT
ADP[11:0]
VDDA ANALOG-TO-DIGITAL
VSSA CONVERTER (ADC) PTD0
PTD1
PORT D
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4
NOTE
1. PTA4 is output only when used as port pin. PTD5
2. PTA5 is input only when used as port pin.
TCLK
1 kHz
OSCOUT
ICSLCLK
XOSC
3 Pin Assignments
This section shows the pin assignments for the MC9S08FL16 series devices.
PTC5 1 32 PTC6
PTC4 2 31 PTC7
PTA5/IRQ/TCLK/RESET 3 30 PTA0/ADP0
PTD2/TPM1CH2 4 29 PTD5
PTA4/BKGD/MS 5 28 PTA1/ADP1
PTD0 6 27 PTA2/ADP2
PTD1 7 26 PTA3/ADP3
VDD 8 25 PTA6/TPM2CH0
VSS 9 24 PTA7/TPM2CH1
PTB7/EXTAL 10 23 PTB0/RxD/ADP4
PTB6/XTAL 11 22 PTB1/TxD/ADP5
PTB5/TPM2CH1 12 21 PTB2/ADP6
PTD3/TPM1CH3 13 20 PTD4
PTB4/TPM1CH0 14 19 PTB3/ADP7
PTC3/ADP11 15 18 PTC0/ADP8
PTC2/ADP10 16 17 PTC1/ADP9
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA0/ADP0
PTC4
PTC5
PTC6
PTC7
25 PTD5
26
32
31
30
29
28
27
PTA4/BKGD/MS 1 24 PTA1/ADP1
PTD0 2 23 PTA2/ADP2
PTD1 3 22 PTA3/ADP3
VDD 4 21 PTA6/TPM2CH0
VSS 5 20 PTA7/TPM2CH1
PTB7/EXTAL 6 19 PTB0/RxD/ADP4
PTB6/XTAL 7 18 PTB1/TxD/ADP5
PTB5/TPM1CH1 8 17 PTB2/ADP6
10
11
12
13
14
15
16
PTD3/TPM1CH3 9
PTB4/TPM1CH0
PTC3/ADP11
PTC2/ADP10
PTC1/ADP9
PTC0/ADP8
PTB3/ADP7
PTD4
32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O
1 29 PTC5 I/O
2 30 PTC4 I/O
3 31 PTA5 I IRQ I TCLK I RESET I
4 32 PTD2 I/O TPM1CH2 I/O
5 1 PTA4 O BKGD I MS I
6 2 PTD0 I/O
7 3 PTD1 I/O
8 4 VDD I
9 5 VSS I
10 6 PTB7 I/O EXTAL I
11 7 PTB6 I/O XTAL O
12 8 PTB5 I/O TPM1CH1 I/O
13 9 PTD3 I/O TPM1CH3 I/O
14 10 PTB4 I/O TPM1CH0 I/O
15 11 PTC3 I/O ADP11 I
32-SDIP 32-LQFP Port Pin I/O Alt 1 I/O Alt 2 I/O Alt 3 I/O
16 12 PTC2 I/O ADP10 I
17 13 PTC1 I/O ADP9 I
18 14 PTC0 I/O ADP8 I
19 15 PTB3 I/O ADP7 I
20 16 PTD4 I/O
21 17 PTB2 I/O ADP6 I
22 18 PTB1 I/O TxD I/O ADP5 I
23 19 PTB0 I/O RxD I ADP4 I
24 20 PTA7 I/O TPM2CH1 I/O
25 21 PTA6 I/O TPM2CH0 I/O
26 22 PTA3 I/O ADP3 I
27 23 PTA2 I/O ADP2 I
28 24 PTA1 I/O ADP1 I
29 25 PTD5 I/O
30 26 PTA0 I/O ADP0 I
31 27 PTC7 I/O
32 28 PTC6 I/O
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software must clear out any associated flags before
interrupts are enabled. Table 1 illustrates the priority if multiple modules are
enabled. The highest priority module will have control over the pin.
Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module.
Disable all modules that share a pin before enabling another module.
4 Memory Map
Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16
series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and
control/status registers. The registers are divided into two groups:
• Direct-page registers (0x0000 through 0x003F)
• High-page registers (0x1800 through 0x187F)
$0000 $0000
DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS
$003F $003F
$0040 $0040
RAM 768 BYTES
$033F RAM 1024 BYTES
$0340
$043F
$0440
UNIMPLEMENTED
UNIMPLEMENTED
$17FF $17FF
$1800 $1800
HIGH PAGE REGISTERS HIGH PAGE REGISTERS
$187F $187F
$1880 $1880
UNIMPLEMENTED
UNIMPLEMENTED
$BFFF
$C000
FLASH
$DFFF
$E000 16384 BYTES
FLASH
8192 BYTES
$FFFF $FFFF
MC9S08FL8 MC9S08FL16
Figure 5. MC9S08FL16 Series Memory Map
5 Electrical Characteristics
5.1 Introduction
This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers
available at the time of publication.
P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
C
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
T under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O far much smaller than Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
5.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
50.000
45.000
40.000
35.000
-40C
30.000
0C
mA
25.000 25C
20.000 55C
85C
15.000
10.000
5.000
0.000
0 0.3 0.5 0.8 1 1.3 2
V
10.000
9.000
8.000
7.000
-40C
6.000 0C
mA
5.000 25C
4.000 55C
85C
3.000
2.000
1.000
0.000
0 0.3 0.5 0.8 1 1.3 2
V
50.000
45.000
40.000
35.000
-40C
30.000 0C
mA
25.000 25C
20.000 55C
85C
15.000
10.000
5.000
0.000
0 0.3 0.5 0.8 1 1.3 2
V
14.000
12.000
10.000
-40C
8.000 0C
mA
25C
6.000 55C
85C
4.000
2.000
0.000
0 0.3 0.5 0.8 1 1.3 2
V
5.66 –40 C
P 10 MHz 5.75 — 25 C
5.80 85 C
Run supply current
1 RIDD 5 mA
FEI mode, all modules off 1.61 –40 C
P 1 MHz 1.65 — 25 C
1.78 85 C
2.79 –40 C
C 10 MHz 2.86 — 25 C
2.88 85 C
Wait mode supply current
2 WIDD 5 A
FEI mode, all modules off 1.05 –40 C
C 1 MHz 1.06 — 25 C
1.06 85 C
C Stop2 mode supply current S2IDD — 5 1.06 — A –40 to 85 C
3 Stop3 mode supply current
C S3IDD — 5 1.17 — A –40 to 85 C
no clocks active
4 C ADC adder to stop3 — — 5 163.88 — A 25 C
ICS adder to stop3
5 C — — 5 1.25 — A 25 C
EREFSTEN = 1
6 C LVD adder to stop3 — — 5 161.3 — A 25 C
1
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
C1
2 D Load capacitors
C2 See Note3
Feedback resistor
3 D Low range (32 kHz to 38.4 kHz) RF 10 M
High range (1 MHz to 16 MHz) 1 M
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 C Ambient) (continued)
XOSC
EXTAL XTAL
RS
RF
Crystal or Resonator
C1
C2
1.00%
0.50%
0.00%
-60 -40 -20 0 20 40 60 80 100 120
Deviation (%)
-0.50%
-1.00% TBD
-1.50%
-2.00%
Temperature
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
5.9 AC Characteristics
This section describes timing characteristics for each peripheral system.
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
DD and 80% VDD levels. Temperature range –40 C to 85 C.
5 Timing is shown with respect to 20% V
textrst
RESET PIN
tIHIL
KBIPx
IRQ/KBIPx
tILIH
tTCLK
tclkh
TCLK
tclkl
tICPW
TPMCHn
TPMCHn
tICPW
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
RAS input RADIN ENGINE
protection
+
VADIN
–
VAS CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
Supply Current
ADLPC=1
T IDDA — 133 — A
ADLSMP=1
ADCO=1
Supply Current
ADLPC=1
T IDDA — 218 — A
ADLSMP=0
ADCO=1
Supply Current
ADLPC=0
T IDDA — 327 — A
ADLSMP=1
ADCO=1
Supply Current
ADLPC=0
P IDDA — 0.582 1 mA
ADLSMP=0
ADCO=1
Temp Sensor
D 25 C VTEMP25 — 1.396 — mV
Voltage
Total
Includes
P Unadjusted 8-bit mode ETUE — 0.5 1.0 LSB2 quantization
Error
Differential
P 8-bit mode3 DNL — 0.3 0.5 LSB2
Non-Linearity
Integral
T 8-bit mode INL — 0.3 0.5 LSB2
Non-Linearity
Zero-Scale
P 8-bit mode EZS — 0.5 0.5 LSB2 VADIN = VSSA
Error
Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Quantization
D 8-bit mode EQ — — 0.5 LSB2
Error
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
Level1
Parameter Symbol Conditions Frequency fOSC/fBUS Unit
(Max)
Radiated emissions, VRE_TEM VDD = 5.0 V 0.15 – 50 MHz 4 MHz crystal 9 dBV
electric field TA = 25 C 19 MHz bus
package type 50 – 150 MHz 5
32-pin LQFP 150 – 500 MHz 2
IEC Level N —
SAE Level 1 —
1
Data based on qualification test results.
6 Ordering Information
This section contains ordering information for MC9S08FL16 series devices. See below for an example of
the device numbering system.
Table 16. Device Numbering System
Memory
Device Number1 Available Packages2
FLASH RAM
MC9S08FL16 16 KB 1024 32 SDIP
MC9S08FL8 8 KB 768 32 LQFP
1
See the reference manual, MC9S08FL16 Series Reference Manual, for a complete
description of modules included on each device.
2
See Table 17 for package information.
Status
(MC = Fully Qualified) Package designator (see Table 17)
7 Package Information
Table 17. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
32 Low Quad Flat Package LQFP LC 873A-03 98ASH70029A
32 Shrink Dual In-line Package SDIP BM 1376-02 98ASA99330D
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MC9S08FL16
Rev. 3
11/2010