A Solid-State Current limiting Switch
for the Application of DC Power Network
Masaaki Komatsu
National Institute of Technology, Kushiro College
Department of Electrical Engineering
2-32-1, Otanoshike-nishi, Kushiro, Hokkaido 084-0916, Japan
komatsu@kushiro-ct.ac.jp
Abstract—when designing a large distributed dc power
network, special attention must be placed on the electrical
stability, control of the systems, and individual load on the
systems. In order to prevent the fault propagation, provide
protection against overload and fault, and isolate the faulty
load and equipment in a dc power network, an overcurrent
protection device must be applied to the switch gear for the
electric power management and control of the systems [1].
Overcurrent protection devices such as circuit breakers in the
primary and secondary distribution systems protect all branch
circuits on the load side of the discharge bus. A circuit breaker
is electromechanical devices that may be reset and reused after
an overload or low-value short circuit, but most manufactures
recommend replacement if the device ever interrupts a short
circuit with a fault current close to its interrupt rating.
Furthermore, circuit breaker has the conflicting of time delay
characteristics that trip delays must be long enough to open the
circuit when a real fault exists [4]. A solid state type of power
switching circuit has been developed as a new power protection
technique for dc power network instead of electromechanical
circuit breaker. The candidate for these switching devices
should be Si Power MOSFET, IGBT, and SiC MOSFET. As an
example of an electromechanical circuit breaker delay curve
application, consider a 50 A circuit breaker and fault that
draws 200 A (400% of circuit breaker rating).The opening
mechanism in circuit breaker will not completely open until as
much as 0.2 s has elapsed [1]. While on the other hand, solid-
state current limiting switch will open within 20 μs and this
elapsed time and current rating can be adjusted freely [2].
From the stand point of the dc network stability, when the
transient over current caused by fault and or short circuit will
be observed, a solid-state current limiting switch will act as
over current suppression as a secondary role in the dc power
network. In this paper, we describe the performance of these
solid state type of power switching circuit in DC power
network and result of stability analysis using Power
Electronics Circuit Simulator, PSIM.
Keywords—Powe Semiconductor; dc circuit breaker; current
limiting; overcurrent protection; Power MOSFET; IGBT; SiC
MOSFET, Stability, Small signal stability
I. INTRODUCTION
The future electricity grid for the electric power
distribution network is slowly moving in the direction of dc
transmission for several reasons, including lower
distribution losses as compared with ac distribution and
more efficient integration of renewables to substantially
increase the mix of clean energy source with the standard
grid in the next ten-plus years. Medium-voltage dc grids and
in-house dc distribution grids will further improve cost
savings and reliability with less maintenance [1].
When designing a large distributed dc power network,
special attention must be placed on the electrical stability,
control of the systems, and individual load on the systems.
In order to prevent the fault propagation, provide protection
against overload and fault, and isolate the faulty load and
equipment in a dc power network, an overcurrent protection
device must be applied to the switch gear for electric power
management and control of the systems [2], [3], [6].
Overcurrent protection devices such as circuit breakers
in the primary and secondary distribution systems protect all
branch circuits on the load side of the discharge bus. A
circuit breaker is electromechanical devices that may be
reset and reused after an overload or low-value short circuit,
but most manufactures recommend replacement if the
device ever interrupts a short circuit with a fault current
close to its interrupt rating. Furthermore, circuit breaker has
the conflicting of time delay characteristics that trip delays
must be long enough to open the circuit when a real fault
exists [4].
We are now developing a solid state type of power
switching circuit as a new power protection technique for dc
power network instead of electromechanical circuit breaker.
The candidate for these switching devices should be Si
Power MOSFET, IGBT, and SiC MOSFET. As an example
of a circuit breaker delay curve application, consider a 50 A
circuit breaker and fault that draws 200 A (400% of circuit
breaker rating). The opening mechanism in a circuit will not
completely open until as much as 0.2 s has elapsed [4], [5].
While on the other hand, our prototype switching circuit will
open within 20 µs and we can freely adjust this elapsed time
and current rating [8], [10]. To avoid nuisance tripping, we
successfully performed current limiting function by extend
the elapsed time using same control circuit [10].
In this paper, we describe the performance of these solid
state type of power switching circuit in DC power network
and result of stability analysis using Power Electronics
Circuit Simulator, PSIM.
II. A SOLID –STATE CURRENT LIMITING SWITCH
FOR THE APPLICATION OF DC POWERNETWORK
We are now developing a solid state type of power
switching circuit as a new power protection technique for
low voltage dc power network instead of magnetic
electromechanical circuit breaker [8]. The candidate for
these switching devices should be Si Power MOSFET,
IGBT, and SiC MOSFET.
The environment of the development of dc grids
protection, new power devices are now improved. In these
environment, focusing on the application for the low and
medium voltage dc grid, fast-acting switching function and
current limiting features are brought up the idea to apply Si
Power MOSFET, IGBT, and SiC MOSFET to the dc circuit
breaker. The very basic evaluation for this fast-acting
switching and current limiting function for the dc circuit
breaker using Power Semiconductor are shown by
experiment in this paper [8], [10].

A. Basic function for semiconductor circuit breaker

The function and design of semiconductor circuit
breaker is based on the block diagram shown in Fig. 1. This
will provide following functions.
 Overcurrent detection and suppression caused by
fault and or short circuit.
 Selectivity of fault current rating.
 Overcurrent limitation and disconnection of load.
 Selectivity of overcurrent limiting time. Fig. 1. Power Semiconductor Circuit Breaker Diagram in DC Power
Starting from basic design on semiconductor circuit Network.
breaker, the requirement for experiment was defined as
follows. 35

 DC power bus voltage should be from 100 V to 400 30

Power MOSFET 100V, 5A
Fault Trip Off
V.
25

Current [A] / Volt [V]

 Load current should be from 2.5 A to 8 A and the
fault current rating is 200%. 20
Gate Voltage
 To aim at fast-acting Semiconductor circuit break, 15

fault trip off time should be less than 20 µs. 10 Short Circuit
Trip off
5
B. Design for Transient overcurrent protection Load Current
Our prototype of switching device using Si Power 0

MOSFET will trip off the fault current within 20 µs and -5

elapsed time and current rating can be adjusted by the -600 -400 -200 0 200 400 600

capacitor and over current sensing resistance [8], [10]. Time [μsec]

The load voltage and current was selected from 100 V to

400 V, and 2.5 A to 8 A. Fig. 3 shows the typical fault trip
off waveform under the condition of 100 V, 2.5 A load
voltage and current. Overcurrent detection was adjusted to
200% rating current [8], [10].
However, at fault interruption, the rapid increasing
transient overcurrent or surge current was observed [8], [10].
This may cause severe overcurrent stress or damage to the
Power Semiconductor and sensitive device inside. The
prototype Circuit Breaker need to be improved for this
transient overcurrent. Then the following countermeasure
was implemented to the circuit shown in Fig. 11.
 Add line inductance to suppress rapid rise current.
 Add snubber circuit to suppress rapid rise current and
noise.
 Insert small inductance between power device and
current sensor resistance to suppress ringing noise.
As the result of these combination, the transient
overcurrent was suppressed shown in Fig. 2. However it was
successfully suppressed transient overcurrent, the snubber
design techniques are mainly for DC/DC switching
converter and it is not sure to be directly applied on Power
Semiconductor Circuit Breaker [9]. More detail analysis will
be requested.
Fig. 2. Fault trip off characteristics of Power MOSFET, 100 V, 5 A load
voltage and load current
III. EVALUATION FOR THE HARD SHORT CIRCUIT
AND FAULT TRIP OFF FUNCTION
For the designing of semiconductor circuit breaker in the
category of low bus voltage, Si Power MOSFET can be
operated at efficient switching frequency. With 500-V, 15-A
Si N-channel MOSFET designed and developed by
TOSHIBA , the dc bus voltage can be around 100 V to 250
V, which enables an extensive use of these Si Power
MOSFET devices in applications such as switching
regulator, DC-DC convertor, and motor drives. The drain to
source voltage (VDSS) for this device is 500 V, drain current
(ID) is 15 A, static on resistance (RDS(ON)) is 0.35Ω , gate
supply voltage is 15 V. Fig. 3 shows the block diagram for
overcurrent detection and fault trip off function in Gate
drive IC. RCS is the overcurrent sensing resistance and when
the voltage at the current sensing point (CS) reaches the
threshold voltage (230 mV), this IC detect over current
condition. To avid nuisance trip off, this circuit has blanking
time (500 ns) and wait to next switching action. After the
blanking time has elapsed if a CS voltage above the
threshold is still present, the output driver is switched into a
linear mode with a feedback amplifier controlling the output
gate drive voltage [8], [10]. The amplifier and the output
power switch from a negative feedback loop which controls
and settles the gate drive voltage to a lower value in order to 16
Power MOSFET 100V, 5A
keep the switch current limited to the rating preset value 14
Gate Voltage
determined by resistance RCS value.

Current [A] / Volt [V]

12
Fig. 6 is the zoom of the waveform for Fig. 2, load 10
voltage and current is 100 V and 2.5 A and Figure 10 is load
8
current 5 A. In Fig. 3, when overcurrent is detected at the Short Circuit

fault current rating, gate voltage is limited down from linear 6

region to saturation region. The gate threshold voltage (Vth) 4 Load Current
Trip off

for this Power MOSFET is 2 – 4 V and the operation is 2

performed from 4.5 A to 5.75 A in the saturation region.
0
After the overcurrent is detected at the fault current rating
value, the gate voltage will be kept this saturated region -2
-20 -10 0 10 20 30
voltage with a certain time and then trip to off 0 V [8], [10]. Time [μsec]

Fig. 6. Zoom of Fault trip off waveform, Power MOSFET, 100 V, 5 A

load voltage and load current.

The trip off, the sequence of these action was completed

approximately for 12 μs and gentle current overshoot or
surge current was observed in Fig. 4-6. A set of fault trip off
experiments were performed under the condition of that the
load voltage and current was selected 100 V, and 1 A to 5 A
this time.

IV. CURRENT LIMITING DESIGN

Considering the drain current, the Power MOSFET
Fig. 3. Block diagram for overcurrent detection and fault trip off function. typical I-V curve can be divided into two parts: the liner
region in which the drain current increase quickly with the
drain voltage and the saturation region in which the drain
16
current has a very weak dependence on the drain voltage.
Power MOSFET 100V, 1A Basically, a Power MOSFET is acting the drain current
14 Gate Voltage
controlled by the gate voltage driving. The current limiting
12 and trip off function is performed by the transfer from linear
Current [A] / Volt [V]

10 region to saturation region in I-V curve [2], [3], [7], [8], [10].
8 For the trip off evaluation in the previous section, the
6 sequence of the trip off action was completed approximately
Short Circuit
4 Trip off for 12 μs. This timing will be determined by the capacitor
CE shown in Fig. 3. In this block diagram, when the output
2
stage switches to linear mode due to an overcurrent status at
0 Load Current CS, the input of CE voltage is set to drive a 100 μA charging
-2 current into the capacitor CE. This charging current will be
-40 -30 -20 -10 0 10 20 30 40 50 60 terminated if the CS voltage disappears, and the driver turns
Time [μsec]
to the “normal switching mode”. However if the fault
Fig. 4. Zoom of Fault trip off waveform, Power MOSFET, 100 V, 1 A condition remains at CS and CE is charged to above 1.8 V,
load voltage and load current. then ERR trip comparator will be triggered and output is
turned off.

16
This function can be applied to the overcurrent limiting
Power MOSFET 100V, 2A design using this capacitor CE.
14 Gate Voltage
12
Fig. 7 shows 2.0 A circuit breaker output current to the
Current [A] / Volt [V]

load when an abrupt short circuit is generated at the output

10
using 100 V bus voltage. The active current limit point was
8 set for 4 A by resistance RCS selected 200 % of fault current
6 rating and expected trip off time is set by capacitance CE
Short Circuit
Trip off selected 0.56 μF as 10 ms current limiting time [8], [10].
4

2 During normal operation, the Power MOSFET driver

Load Current
drives the Power MOSFET gate to 15 V as shown in Fig. 7.
0
During the fault, Power MOSFET acts to limit to the load
-2
-20 -10 0 10 20 30
current to the fault current rating level. In this moment, the
Time [μsec] Power MOSFET gate input is instantly driven down in to
Fig. 5. Zoom of Fault trip off waveform, Power MOSFET, 100 V, 2 A
the saturation region, which is approximately 5 V as shown
load voltage and load current. in Fig. 7. During limiting the overcurrent, the power
dissipation in the Power MOSFET is becoming very large
and can only be maintained for a short time interval
because of the channel temperature limitation. This time
interval will be determined by current limiting value and
Power MOSFET junction temperature Tj in order to avoid
the Power MOSFET’s thermal breakdown [3], [7], [8], [10].
The combination of the circuit breaker which has
different current limiting level and current limiting time will
be effective in the dc power network, primary and secondary
distribution which include various type of loads. To avoid
the nuisance trip off and keep the coordination of system
protection in upstream and downstream, these combination
should be a global optimum solution in the future’s dc
microgrid [8], [10].
Fig. 8 shows 20 ms current limiting and fault trip off
waveform in case of 100 V bus voltage rated at 2.0 A circuit
breaker output current to the load.
In case of 100 V bus voltage rated at 5.0 A circuit
breaker, a thermal breakdown will be caused from 8 ms to
12 ms current limiting time from the thermal breakdown test
and analysis.
16
14 Gate Voltage
Current [A] / Volt [V]
V. STABILITY ANALYSIS FOR DC NETWORK
DC power networks systems will be required rapid
recovery and high reliability design for the survivability.
Basic dc power network has the architect of primary,
secondary, and tertiary distribution systems. DC power
network systems include the overcurrent protection device
such as circuit breaker and fuse.
A essential factor in design in design and
implementation of any DC power network using switching
converters is the stability of the system under all expected
conditions of load and transition perturbations. The
principles of the stability as it is called small signal stability
are applicable to the developments of distributed DC power
systems and load in the DC power network. For the small
signal stability requirements, a minimum gain and phase
margin is based on the complex load and source impedance
at the system interface.
The approach of stability analysis for the International
Space Station (ISS) which has large DC power systems
should be a good example.
A. Impedance ratio as a loop gain
Any part of the power distribution system can be
represented using two-port network. The same concept can
be extended and applied to the integration of various system
of a large DC power network. Various parts of the system
Power MOSFET 100V, 2A are broken into source and load blocks and source
Current Limiting: 10msec impedance ZS and load impedance ZL are defined for each
interface. Fig. 9 shows two system blocks connected in

12
series. The source network has an input-to-output transfer
10
function of TS, and load network has an input-to-output
8 transfer function of TL. The transfer function is described as
6 Current limiting follows.
4
Short Circuit
Trip off
2
Load Current
𝑉 𝑇 ∙𝑇 1
𝑇 = = =𝑇 ∙𝑇
0 𝑉 𝑉 ⁄𝑉 1 + (𝑍 ⁄𝑍 )
-2
-10 0 10 20 30 =𝑇 ∙𝑇 (1)
Time [msec]

Fig. 7. 10 ms Current limiting and fault trip off waveform, Power With 𝑇 = 𝑍 ⁄𝑍
MOSFET, 100 V, 2 A load voltage and load current.
Where, Tsys is the input-to-output transfer function of the
integrated DC power network.
Considering a feedback control system, closed-loop
16 transfer function is also described by equation (1). The
Power MOSFET 100V, 2A
14 Gate Voltage
characteristics equation of this system is simply
Current Limiting: 20msec
1+𝑇 =0 (2)
Current [A] / Volt [V]

12

10 and Tm is the ratio of source impedance and load impedance

8 and is defined as loop gain of the integrated system. It can
6
Current limiting be used to determine the system stability and load effect.
Short Circuit
4 If 𝑍 ≪ 𝑍 for all frequency, the equation (1) is as
2 Trip off follows.
Load Current
0 𝑇 ≅𝑇 ∙𝑇 (3)
-2
-10 0 10 20 30
Hence, the integrated DC electric power network will
Time [msec] be assured that the system is stable if 𝑍 ≪ 𝑍 for all
frequency and source/load network is stable independently.
Fig. 8. 20 ms Current limiting and fault trip off waveform, Power
MOSFET, 100 V, 2 A load voltage and load current. In considering these performances of source and load
network stability, electric power designer of components
and/or payload should not integrate entire network stability
with source network but own local stability.
In general, the source network in DC electric power
system is stable against constant-current load, and load
network is stable against constant-voltage source network
[X].
DC power source, the interface between primary and
secondary power distribution in DC power network, has
active role for the good impedance separation under the
condition of 𝑍 ≪ 𝑍 .
B. Impedance phase and gain margin
In DC power network, it is very ideal approach if
𝑍 ≪ 𝑍 , however it is impractical to have 𝑍 ≪ 𝑍 for all
frequencies.
Due to numerous possible system configurations and
other restrictions, source impedance separation cannot be
guaranteed at other interface. Even though this does not
imply directly that the DC electric power network is
unstable. In fact, the stability of the integrated system can be
evaluated by Bode plot or Nyquist plot of Tm.
The phase and gain margin of the loop gain, Tm can be
determined using Bode plot or Nyquist plot as major
example. To know the system stability from the actual
source and load impedance measuring data, it is easy to
evaluate by looking at the vector plot of |𝑇 | and ∠𝑇 as
the Nyquist plot of Tm. To know the system phase and gain
margin from the actual source and load impedance data
precisely, Bode plot of the Tm is applicable to evaluate the
system stability.
To ensure stability in all region of the secondary power
system, the requirement of the small signal stability for the
Users should be documented in “User Electric Power
Specification and Requirement”.
Generally the requirement will be designed to maintain
minimum of 3 dB gain margin and 20 degrees of phase
margin at its interface with DC electric power network.
These margins apply to the complex ratio of source
impedance divided by the load impedance at the interface.
The minimum margin requirement will be satisfied over the
range of impedance magnitude and phase values that can
occur in operation at the each User’s interface with DC
electric power network.
Fig. 10 shows the “Forbidden zone” on the Nyquist
diagram for a 3-dB and 20-degree minimum gain and phase
margin criterion.
Fig. 9. Electric Power Network Model
+Im
Tm = 1
+160 °
-3db (Tm = 0.707)
+Re
(-1 , 0)
-160 °
Fig. 10. Nyquist plot for gain and phase margin
VI. EVALUATION FOR DC ELECTRIC POWER
NETWORK STABILITY
Large scale simulation tool can simulate network
stability precisely collecting a thousand of circuit model.
But it is not feasible to apply this tool for all designer in
early design phase and not easy to handle and/or maintain
for all engineer. To evaluate the network stability instead of
using large scale simulation tool, general circuit simulation
tools can be expected and applied to the system stability
analysis if the system analysis model could be simplified.
In this paper, “PSIM”, circuit analysis and design tool,
was selected and applied to the DC electric power network
stability analysis approach.
Fig. 11 shows solid-sate current limiting circuit which is
described in previous section. From the stand point of the
DC network stability, when the transient overcurrent caused
by fault or short circuit will be observed, a solid-state
current limiting switch will act as overcurrent suppression as
a secondary role in DC power network. We replace this
solid-state current limiting switch with differential limiter or
nonlinear element as an equivalent circuit in PSIM shown in
Fig. 12. The current limiting function can be considered the
di/dt or dv/dt limiter for transient overcurrent suppression
and Power MOSFET is thought to be similar to voltage or
current differential limiter as nonlinear resistance element.
To observe the behavior reaction for transient suppression in
DC power network, this nonlinear element can be replaced
with Zener diode as a simple di/dt limiter PSIM model
shown in Fig. 13. In this paper, we show analysis result
using this simplified model.
Line Inductance 20µH
Power
MOSFET 0.1µF
Snubber
0.1~0.5µH
Circuit
Small Inductance
56 Ω
RCS
Fig. 11. Solid-state Current Limiting Switch Circuit
 20

15
Total Current

Current [A]
10

Fault Load・Adjacent Load

5
Inductive Load
0

Fig. 12. PSIM Model for Solid-state Current Limiting Switch -5

0 1 2 3
Time [ms]

Fig. 16. Transient overcurrent waveform with current limiting switch

In this waveform, large oscillatory waveform is observed

Fig. 13. Simplified PSIM Model for Solid-state Current Limiting Switch
using Zener diode
A. Transient analysis using solid-state current limiting
switch
To evaluate the transient analysis using solid-state
current limiting switch in DC electric power network,
simplified DC distribution model was developed shown as
Fig. 14. In this model, three different load models are
simply devised and one load should be assumed to be the
inductive load. Fig. 15 shows the transient overcurrent
waveform without solid state current limiting switch when
short circuit has occurred.
Fig. 14. Simplified DC distribution analysis model
and this waveform is occurred in adjacent load, not short
circuit load in DC power network. This kind of phenomenon
has sometimes happened in large DC electric power network
and this should cause “nuisance tripping” in DC power
distribution systems.
Fig. 15 shows the transient overcurrent waveform using
current limiting switch as a di/dt limiter. Large oscillatory
wave form is suppressed and another oscillatory waveform
caused by inductive load also is suppressed.
B. Loop gain analysis using solid-state current limiting
switch
The analysis of source and load impedance at the
interface of primary/secondary distribution should be
measured but skipped this process. The corresponding Bode
plot and Nyquist plot of the loop gain Tm are shown in Fig.
17 and Fig. 18 respectively. These are same condition on
Fig. 15.
In general, it was pointed out earlier time that response
is usually the information sought in the analysis of feedback
control system. However, analytically, the time response is
usually difficult to obtain because of amount of computation
involved. Therefore, the frequency response of feedback
control system is often obtain by means of the graphical
methods, such as the Bode plot and Nyquist plot, and then
interpretation on the time domain behavior of the system is
made on time domain-frequency domain relationship [11].

Total Current
20 100
Phase [deg] & Gain [V]

15 Adjacent Load 50
Current [A]

10
Gain
Inductive Load 0

5 Fault Load
-50

0
-100
Phase
-5
-150

0 1 2 3
Time [ms] -200
100 1k Frequency [Hz] 10k 100k

Fig. 15. Transient overcurrent waveform without current limiting switch

Fig. 17. Bode plot without current limiting switch
 VII. CONCLUSION
Nyquist Plot
[dB] 90 We are developing a solid state type of power switching
2.0
120 60
and distribution circuit breaker as a new power protection
1.5
technique for dc power network instead of
1.0
150 30 electromechanical circuit breaker. Our prototype switching
0.5
device using Power MOSFET will trip off the fault current
within 20 μs and elapsed time and current rating can be
0.0 180 0 adjusted by the capacitor and overcurrent sensing resistance.
0.5 During the first prototype circuit breaker designing and
developing in 2015 and 2016, at fault interruption, the rapid
1.0
210 330 increasing transient overcurrent was observed. As the result
1.5
Nyquist Plot of snubber circuit and line inductance insertion, the transient
2.0
240 300 overcurrent was suppressed successfully. To avoid nuisance
270
tripping, we successfully performed current limiting
function by extend the elapsed time using same control
Fig. 18. Nyquist plot without current limiting switch circuit. From these result, the combination of current
limiting time and level should be a global optimum solution
in the future’s low-voltage and medium-voltage dc
For precisely this reason, the analysis of feedback microgrid. As the second approach, from the stand point of
control system can be applied to the DC power network. In the DC power network stability, when the transient
feedback control system, loop gain of the system must be overcurrent caused by fault or short circuit will be observed,
infinite, must equal unity, at all frequency in the ideal a solid-state current limiting switch will act as overcurrent
situation. For the phase characteristics of frequency suppression as a secondary role in DC power network. We
response, the ideal situation is that the phase shit must be replace this solid-state current limiting switch with
linear function of frequency with the frequency band of the differential limiter or nonlinear element as an equivalent
input signal [11]. circuit in PSIM. From the stability analysis, current limiting
switch will make a solid contribution to the DC power
Fig. 19 and Fig. 20 show the Bode plot and Nyquist plot
network stability.
which has current limiting switch function in DC power
network. Compared to the Fig. 17 and Fig. 18, Fig. 19 and
Fig. 20 show very ideal flat gain response and linear ACKNOWLEDGMENT
function phase shift. This research was supported by Grants-in-Aid for
Scientific Research organized by Japan Society for the
Promotion of Science, JSPS KAKENHI Grant Number JP
200
15K13933.
150
Phase [deg] & Gain [V]

Gain
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100
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Fig. 20. Nyquist plot with current limiting switch