IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO.

2, FEBRUARY 2007 245

A Design Methodology for MOS Current-Mode

Logic Frequency Dividers
Roberto Nonis, Student Member, IEEE, Enzo Palumbo, Pierpaolo Palestri, Member, IEEE, and
Luca Selmi, Member, IEEE

Abstract—In this work, a methodology for the design of MOS

current-mode logic frequency dividers is presented. A mix of hand
calculations and circuit simulations is used to relate the power con-
sumption and the frequency of operation. Each latch in the dividers
is sized separately in order to minimize the overall power consump-
tion. Furthermore, the effect on the power consumption of circuit
parameters such as output swing and voltage gain of the input dif-
ferential pair is analyzed in detail. The methodology has been ap-
plied to dividers by two and dividers by three with 50% output
duty cycle.
Index Terms—CMOS integrated circuit, frequency dividers, low
power consumption, MOS current-mode logic, odd division ratio
with 50% duty cycle.
Fig. 1. Circuit schematic of the level sensitive latch in MOS current-mode
logic.

I. INTRODUCTION
REQUENCY dividers are extensively used for frequency
F synthesis in wireless transceivers, within or in cascade
to phase-locked loop (PLL) circuits, or as I/Q generators.
When frequency of operation is high and area is a concern,
dividers are commonly implemented in MOS current-mode
logic (MCML) [also refereed as source coupled logic (SCL)]
[1]–[9] and suffer from high power dissipation, which is a
critical point for portable applications. As an example, the first
stage of the divider in the feedback path of a PLL can drain
as much as half of the average current requested by the whole
frequency synthesizer.
Strategies for the optimization of MCML gates and latches
have been proposed in [10]–[12]. These approaches relate the
gate delay to the power consumption, with the constraint of a
given output swing and voltage gain of the differential pairs, in
order to satisfy the requirement on the noise margin. To this pur-
pose, analytical expressions are used for the current–voltage and
capacitance–voltage characteristics of the transistors. In partic-
ular, the square-law relation between the transconductance and
the current of the transistors is used to express the transistor
width as a function of the drain current. In [13] it is pointed
out that the accurate modeling of this relation may be crucial
for the optimum design of MCML gates, and an alternative ap-
proach based on circuit simulation has been proposed.
In this paper, we present a new methodology that extends that
of [13] to the design of complete frequency dividers. The main
Manuscript received July 22, 2005; revised March 14, 2006. This work was
supported in part by Infineon Technologies, Munich (D). This paper was rec-
ommended by Associate Editor G. Cauwenberghs.
The authors are with the DIEGM, University of Udine, Via delle Scienze 208,
33100 Udine, Italy (e-mail: roberto.nonis@uniud.it).
Digital Object Identifier 10.1109/TCSI.2006.885999
1057-7122/$25.00 © 2007 IEEE
features of our approach are: 1) each latch inside a divider is de-
signed based on its actual load, in order to minimize total power
consumption; 2) instead of being considered a project specifi-
cation, output swing and voltage gain are exploited as parame-
ters that can be adjusted in order to get further improvement in
power consumption. As shown in [12] [see (4) therein] this ad-
justment sometimes result in a degradation of the noise margin
of the differential pair, but this is not a major issue in frequency
division circuits for RF frequency generation, where the latch
toggles continuously and the possible loss of one edge is not as
critical as the loss of one bit when processing data.
The paper is organized as follows. Section II presents the
design methodology for the MCML level-sensitive latch to be
used as building block of the dividers. Section III applies this
method to the design of dividers by two, while Section IV de-
scribes the design methodology for dividers by 3 with 50%
output duty cycle. Both dividers are implemented in a standard
CMOS technology [14] whose key figures are nm,
nm, V, V. Conclusions are
drawn in Section V.
II. DESIGN METHODOLOGY FOR THE MCML LATCH
A. Basic Equations
The circuit schematic of the MCML latch is shown in Fig. 1.
We are considering a resistive load instead of the pMOS treated
in [11]. Assuming that both the input and clock signals driving
the latch are square waves, the operation of the latch is as fol-
lows. At the beginning of the half of the input period when the
clock signal is high, the bias current is instantaneously
steered through the input differential pair and the single-ended
outputs of the latch change status following a transient with time
constant , where is the total capacitance connected
246 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

pair in case of generic input waves is thus more realistically

approximated with the piecewise function in Fig. 2(b).
Define as the voltage gain of the input differential pair in
balanced conditions ( ).
It is known that

(3)
Fig. 2. Approximation of the static differential trans-characteristic of the input
differential pair of the MCML latch: (a) with infinitive voltage gain A (equiv-
alent to the assumption that the waves driving the latch are ideal square waves), where and are the intrinsic transconductance and the
and (b) with finite voltage gain A , needed for more accurate representation
in the case of the input waves with finite slew rate. I is the difference of the
output conductance of the MOS transistor, respectively.
current in the two branches of the differential pair. Proper operation of the regenerative memory cell demands
that , where is the voltage gain of the cross
coupled pair when the cell is in balanced conditions (
at the single-ended output node. When the clock signal becomes ). Due to positive feedback, any larger than
low, the current is instantaneously steered to the cross coupled unity is sufficient. Since will also be larger than unity, it
pair, which latches the output status. seems reasonable and convenient to choose . Note
Note that in this conditions (squared waves) the latch be- that the input differential pair and the memory cell operate al-
havior does not depend on the small-signal voltage gain of the ternatively with the same tail current ( ). Hence, the con-
differential pairs involved (input pair and clock-input pair). In dition implies . This choice is
other words, the voltage gain can be equivalently considered in- consistent with [13]. Moreover, extensive simulations show that
finity, as sketched in Fig. 2(a). any ratio between 1 to 5 is tolerable, i.e., it does
In order to minimize parasitic capacitances, the length of all not change the output swing even at high input frequency. The
the transistors is set to . Hence, the design of the latch choice guarantees robust design and low input
consists in the sizing of the load resistors ( ), the tail current capacitance. As a consequence, all transistors can be sized once
( ), the width of the transistors in the input differential pair, has been calculated.
in the memory cell and in the clock-driven differential pair ( ,
and respectively). The design specifications are: the B. Transistor Sizing
single-ended load capacitance ( ), the single-ended Equations (1) –(3) allow us to design the latch for given and
output voltage swing ( ) and the frequency of the clock signal , provided , , and are related to and (that
( ). Note that the value of the supply voltage is not di- are not known at this stage of the design). It must be pointed out
rectly involved in the design calculations. Nevertheless, it poses here that, for a given input frequency and output load, a divider
an upper limit to . does not work for an arbitrary choice of and . An investiga-
The choice of , , , and is guided by tion on the choice of these parameters for optimum design must
the following considerations. By inspection of Fig. 1, the output be performed separately for the divider by 2 and the divider by
voltage swing is 3 and will be presented in Sections III and IV, respectively.
With regard to the description of the and char-
acteristics, we use the numerical technique proposed in
(1) [13]. In a template transistor biased under saturation con-
ditions (e.g., ) whose width is larger than
For proper operation, the output time constant must be equal to the minimum, the channel current is swept to obtain
a fraction ( , with ) of the input period ( ) plots of and . For sufficiently
large width, both and are surely proportional to
. Thus, it is convenient to introduce the current den-
(2) sity and to define the normalized
and curves as ,
where is a function of the transistors’ widths, as it will be . Equation (3) can thus
discussed at the end of this section. be rewritten as
In real dividers working in the gigahertz range, signals
driving the latch are more similar to sinusoidal waves than (4)
square waves. Hence, the assumption that the output transient
depends only on the time constant does not hold. On the Equation (4) can be finally solved graphically to find the
contrary, a dependence of the output slope at rising and falling channel current density of the transistor in the differential
edge on the voltage gain of the differential pair is observed. pair needed to have the specified voltage gain and output
In other words, the voltage gain of the differential pair must swing . Fig. 3 exemplifies this solution for the technology
be taken into account and control of its value is needed for an that we use as a benchmark in this paper. Key figures of
effective design. The transcharacteristic of the input differential this technology [14] are nm, nm,
NONIS et al.: DESIGN METHODOLOGY 247

Fig. 4. Divider-by-2 topology. The circuit schematics of the master and slave
latch are as in Fig. 1.

As a consequence, (5) becomes a first-order equation which can

be solved for , that multiplied by gives

Fig. 3. Graphical solution of (4) for A = 1:4, V = 400 mV.

(9)

where
V, V. Once the current density, , is
known, the device sizing is carried out by solving (2) for
(10)

(5) is the maximum input frequency for which (5) has a valid
solution.
where we used from (1). The computation
of and is then obvious. III. DIVIDER BY 2

C. Capacitance Model A. Design Methodology

In solving (5), a model for is needed. is given by The topology of the MCML divider by 2 is reported in Fig. 4
and consists in two latches connected in a master–slave config-
uration. The design of the divider requires the determination of
(6) , and for both the master and the slave stages. It is
reasonable to design the two latches to have the same output
where is the parasitic capacitance due to the metal wires swing. Since the latches are mutually coupled, this implies that
and is the total capacitance due to the MOS transistors, they have the same input signals. Furthermore, the latches are
that depend on their width and on the instantaneous voltages. driven by the same differential clock signal. Thus, the voltage
Considering for example the output node in Fig. 1, we can gain requirement of the input differential pair is the same for
express master and slave. This means that the current density is the
same and, given and , it is computed once, as described
in Section II.
(7) An important observation has to be done at this stage: master
The factors 2 are due to the fact that is the single-ended and slave latches do not necessarily drive the same capacitive
capacitance connected to either one of the output nodes, while load, except when the divider is used as an I/Q generator. Hence,
and are connected between nodes and . We it is convenient to design the master and the slave with different
found adequate to use voltage independent average values for size of the transistors. The quantitative advantage of this choice
the drain–bulk, gate–drain and gate–source capacitance for unit in terms of current saving will be addressed at the end of this
width ( , and , respectively) calculated based on the paragraph.
BSIM4V4 [15] capacitance model ( ) of the The total capacitances connected to the master and the slave
considered technologies. are written consistently with (6), where the load of the master
An analysis of the parasites extracted from layout for various latch depends on the width of the transistors in the slave latch,
latches designed in the considered technology shows that and vice-versa. We obtain linear functions of and that
can be conveniently expressed as can be written as
, since the length of the wiring is somewhat proportional to
the transistor size. The total capacitance can thus be expressed
in the form

where we implicitly define and

(8) as the total capacitance per unit width connected to
248 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
the latch output due to the transistors and metal wires of the latch
itself and those of the other latch, respectively.
The design of the divider is thus accomplished by solving the
following linear equations for: and
(11)
(12)
The total divider current is finally given by
(13)
where the maximum input frequency is
(14)
Note that if the master and slave latches have the same sizing,
the limiting condition in the current reduction of both latches
would be given by (2) written for the slave. Hence, the master
would require a total current as if it were driving the same total
capacitance as the slave latch. This condition translates in an
additive term within the parenthesis at the numerator of
(13). Assuming fF and fF (reason-
able values for our technology), the design with different size of
the master and slave requires 37% lower current compared to the
case where master and slave have the same size, with no penalty
in phase noise performance, as the critical path from clock input
to divider output is trough the slave latch only [16].
B. Choice of the Design Parameters
The procedure presented in Sections II and III guides the de-
sign of dividers once the nominal output swing , the voltage
gain of the input differential pair and the factor are given.
These specs, if not chosen properly, do not guarantee divider
operation; in particular, the divider could either not work (when
the output swing of one latch is not large enough to unbalance
the input differential pair of the other latch) or the actual voltage
swing could be much lower than the nominal value used in the
design. This possible behavior can be due to either an insuffi-
cient factor or a too low voltage gain . Nevertheless, the
choice of and for proper operation is not obvious. With
help of Fig. 2, we see that in the case of ideal square waves at
the input of the divider, the current steering in the clock pair is
instantaneous. It is easy to demonstrate that, in such a case, the
time evolution of the voltage at the divider output follows an
transient. If we assume that the memory cell is able to restore
the output voltage level in (meaning that its voltage gain
is large enough), it is sufficient to require , choice of and
that corresponds to in (2). However, the assumption
of instantaneous current steering does not hold when the input
waves are sinusoids. Since the voltage gain is not infinite, during
a significant part of the transient, the effective bias current of the
input differential pair is lower than (see Fig. 2(b)), hence
Fig. 5. Simulated output swing normalized to the nominal swing as a func-
tion of the operation frequency of two dividers designed for a nominal input
frequency of 7.2 GHz, a nominal output swing of 500 mV, a representative
C = 20 fF and with two different arbitrary choice of the parameters a and
A . Note that, following the methodology described in this paper, once A , the
nominal frequency and the nominal swing are given, the size of the components
is univocally determined. The same considerations apply to the next figures.
a longer time is required to switch the output. This also means
that for higher values of the factor (i.e., small values)
low values of the voltage gain will be sufficient. It is thus
evident that proper divider operation depends on the choice of
the both parameters and , that are anyway not completely
independent.
In the following we define as proper operation of the divider
the actual division by two of the input frequency performed
with an output voltage swing that is 90% of the nominal value.
Consider, for instance, Fig. 5 that reports the simulated output
voltage swing (normalized to the nominal output swing) as a
function of the frequency of the clock signal (a pure sine-wave)
for two dividers designed in the benchmark technology. They
are both sized for a nominal input frequency of 7.2 GHz, but
with different choice of and . The differential output waves
at 7.2-GHz input frequency for both dividers are reported in
Fig. 6. As can be seen, the design with smaller and fails
to reach the target output swing at the design frequency, pro-
ducing a swing of no more than 270 mV. On the contrary, in
the case with larger and , the divider satisfies the swing
requirement for input frequency up to 9 GHz (Fig. 5), with con-
sequent waste of power when it is required to divide a 7.2-GHz
input. Note that the curve with is consistent with
[17], where it is shown that full switching of the differential
pair requires a minimum small-signal voltage gain of . The
curve shows, indeed, that even for really low input frequencies
the output voltage swing does not reach the nominal value, due
to the fact that the bias current is not completely steered among
the branches of the differential pair.
Optimum design of the divider is thus based on the optimum
.
In the following, we discuss the choice for the parameters
and with reference to the technology described before. We
verified that the numerical results change when a different tech-
nology is considered, but the trends are the same. Fig. 7 reports
the typical dependence of the simulated output swing and power
NONIS et al.: DESIGN METHODOLOGY
Fig. 6. Simulated differential output waveforms of the two dividers considered
in Fig. 5 with a 7.2-GHz input frequency, which is also displayed.
Fig. 7. Dependence of the simulated output swing (normalized to the nominal
output swing) and current consumption on the parameter a in the case of dividers
designed for 7.2-GHz input frequency, V = 500 mV, C = 20 fF and with
three different values of the voltage gain A . The horizontal line indicates the
90% of the nominal V . The intercept of this line with the curves at constant
A gives the optimum value of a corresponding to that specific A . V =
1:5 V.
consumption on the parameter for three different values of the
voltage gain . As expected, for increasing values of the
factor, the actual output voltage swing increases and tends to
saturate to the nominal value, due to the smaller constant
that speeds up the rising and falling edge at the output. This also
implies an increase in the current consumption, as from (13).
Fig. 7 allows us to find the minimum value of the factor needed
for proper operation (output swing equal 90% of the nominal
value) with a given voltage gain and thus corresponding to
the minimum . Note that, again, the curve with
is consistent with the fact that minimum voltage gain for full
switching of the bias current is . The curve shows, indeed,
that even for really high a factors, the output voltage swing does
not reach the nominal value.
In a similar way it is possible to select the factor and pro-
gressively increase until the actual output swing becomes
90% of the nominal swing. The value of found with this
methodology corresponds to minimum power consumption con-
sistently with the choice of . Results of this analysis are shown
249
Fig. 8. Voltage gain A needed to reach the wanted output swing (90% of
the nominal value) as a function of the parameter a, considering two different
design frequencies and two different values of the nominal swing. The current
consumption is also displayed and features a minimum for a = 3. The figure
has been obtained as follows. Given the values for a, f , and V , we have
designed dividers with different values of A (notice that, based on the design
procedure reported in the paper, once these four parameters are known, the size
of the circuit is unambiguous). The transients of these dividers are simulated as
in Figs. 6 and 7 and the values of A that give an output swing equal to 90%
of the nominal swing, have been reported on the top graph. The same procedure
has been repeated for all values of a, A and V . V = 1:5 V.
in Fig. 8, also reporting the corresponding current consump-
tion. We see that the optimum value of as well as the corre-
sponding current consumption depend on , and . How-
ever a minimum consumption exists for , meaning that the
time constant at the single-ended output of the latches
must be one third of the input period. This is not an isolated
result. A number of analyses performed on dividers designed
for different input frequency and load conditions gives the same
outcome, hence this value will be taken as a reference for low
power design.
On the other hand, it is clearly not possible to determine an
optimum value of the voltage gain valid for all design, since
the choice of is not only related to , as we said earlier in
this paragraph, but also to the input frequency and the nominal
output voltage swing. This is demonstrated in the left plot of
Fig. 9, which displays the required voltage gain as a func-
tion of the design frequency for different values of the nominal
voltage swing, considering and output swing 90% of the
nominal values.
The trend in the figure, that is based on the circuit simulation
of the dividers run with input sine waves, can be explained as
follows. Depending on the frequency of the sinusoidal input, the
input slope changes: higher frequency means higher slope. With
increasing slopes of the input, we progressively approach the
limit of instantaneous transitions. Since it can be easily shown
from Fig. 2(b) that the fraction of the transient where the dif-
ferential current is lower than is inversely proportional to
the product between and input slope, we have that at higher
frequencies, the higher slope allows for the use of lower .
Given a value for the factor (for example ), the voltage
gain needed for proper operation is progressively lower with in-
creasing input frequencies, since the input transitions are faster
250 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007

Fig. 10. Topology of the divider-by-3 with 50% output duty cycle. It is com-
posed by three phase-switchable level-sensitive latches.

In conclusion, in some particular cases, power consumption

can show a minimum as a function of the voltage swing that can
thus be used as a design parameter to minimize power.
To verify the consistency of our predictions we performed a
reverse engineering of the high performance divider working at
27 GHz reported in [4], which was built using the same tech-
nology considered in this paper. The published data indicates a
nominal output swing of mV (while the actual output
Fig. 9. On the left: voltage gain A needed to reach the wanted output voltage
swing (90% of the nominal one) as a function of the design frequency for dif- swing is 300 mV) and a total current consumption of 20 mA,
ferent output voltage swing, with a = 3. On the right: corresponding current which however includes the biasing circuits of the input signals.
consumption. V = 1:5 V. Since it is easy to estimate that those circuits drain 7.5 mA, the
actual consumption of the divider is mA, equally
split on master and slave latches.
and approaches the limit of square waves, where the voltage gain Using our methodology, we have designed a divider with
can be as low as 1. Note that a sinusoidal input is a realistic case, the same performances, i.e., the same nominal and actual ,
e.g., when the divider is driven by differential output of an LC and GHz. With , the voltage gain
voltage-controlled oscillator. needed to have GHz is lower than unity. However,
The plot in the right of Fig. 9 reports the current consump- choosing it was possible to achieve mA with
tion corresponding to the values of reported in the left plot. . Circuit simulation demonstrated agreement with
It can be seen that power consumption increases with frequency, results presented in [4]; in particular the actual output swing
while its dependence on the nominal voltage swing is not mono- was 300 mV. The reduction of with respect to the nominal
tonic, according to (13) and (14). In particular, in the figure the value is due to the low value of the factor compared to ,
power consumption is minimum for 500 mV. Based on this re- which would result in dividers designed with an actual swing in
sult, we can consider the voltage swing a project parameter that the order of 90% of the nominal value.
can be adjusted in order to minimize power consumption. This
nonintuitive trend of the current consumption with the voltage
IV. DIVIDER BY 3 WITH 50% OUTPUT DUTY CYCLE
swing deserves some more words. In our approach, an increase
in can be obtained by means of an increase of or via an
A. Design Methodology
increase of . However, increments of are allowed only
if (and thus the capacitive load) is reduced. If the increment In this section, the implementation in MCML of a divider
in can be made larger, in percentage, than the requested in- by three with 50% output duty cycle [18] is addressed. The
crement in , then can even be reduced. To under- topology of the divider is reported in Fig. 10; it consists of three
stand in which cases this may happen, consider again Fig. 3. phase-switchable level-sensitive (PSLS) latches. The instanta-
An increase in implies an increment of the current den- neous value of the phi input sets if the latch is transparent during
sity on the input differential pair, which, in either the high or the low level of the clock (ck). Since the in-
turn, implies a decrease of the width of the transistor under version of the sensitive level is equivalent to the inversion of
the hypothesis that does not increase. Lower also im- the clock signal, the PSLS latch can be implemented driving the
plies lower MOSFET parasitic capacitance, hence a lower clock inputs of a standard latch with the ex-or between the phi
and a higher value of , as the frequency is kept constant [see and ck inputs, as shown in Fig. 11. The output waveforms of
(2)]. In the cases where is dominated by the MOS capac- the three cells have 50% duty cycle and are shifted in phase by
itances, i.e., for low , an increase of implies a more 60 degrees, as shown in Fig. 12. The design of the divider re-
than proportional increase of , resulting in a large decrease quires the determination of , , , and the width
of and thus of . As a result, can increase, in percentage, , of the transistors for each of the three cells. Within a
more than . Note that for large values of , where the single cell, the latch is designed as described in Section II, hence
curve saturates, the increment of implies an increment of with and . The ex-or gate consist
of the same amount, which is obtained though an increase of two identical differential pairs connected in anti-parallel. The
of without a decrease of . design of these differential pairs does not differ from the design
NONIS et al.: DESIGN METHODOLOGY 251

three cells with different sizes of the transistors. The total ca-
pacitances connected to the single-ended outputs of the ex-or
gates and of the latches are written similarly to (6). The load on
the cell output depends on the transistor width of the latch and of
the ex-or gate in the other two cells, while the load of the ex-or
gate only depends on the transistor width of the latch within the
same cell. We obtain linear functions of the width of the
transistor in the latches, and of the width of the transistor in the
ex-or gates ,( )

(15)

where we implicitly define: as the capacitance per unit

Fig. 11. Phase-switchable level-sensitive (PSLS) latch implemented as a level-
sensitive latch (top) driven by an exor-or gate (bottom).
width connected to the output of the latch due to the transistors
of the latch itself; and as the capacitance per
unit width connected to the output of the latch due to the transis-
tors of the latch and ex-or gate respectively driven by its output;
and as the total capacitance per unit width con-
nected to the output of the ex-or gate due to the transistors of
the ex-or gate itself and the transistors of the latch driven by
its output (which is within the same cell) respectively. The ex-
pressions relating these capacitances to the capacitances of the
transistors are reported in Appendix.
The design of the latch is then accomplished by solving (5)
for and ( ), considering the three latches
and the three ex-or gates

Fig. 12. Input and output waveforms of the divider by 3 depicted in Fig. 10.
f = 8 GHz, a = 3, V = 800 mV, A = 1:2 The three available output
phases are shown.

of the input pair of the latch. The constraint on the output

time constant (2) must be applied to both the latch and the ex-or
gate. The inspection of the output waveform of the ex-or gate
and the latch during operation of the divider reveals that, in the
worst case, both outputs must be able to switch their state in half
a period of the clock signal. Hence, the factors for the latch and
the ex-or gate can be set to the same value. It is reasonable to de-
sign the three PSLS latches to have the same output swing. This
implies that the in and phi inputs are driven by similar waves,
thus the voltage gain requirement for the input differential pair
in the latches and the differential pair in the ex-or gates can be
set identical. Furthermore, for the sake of simplicity, the output
swing of the ex-or gate is set equal to the output swing of the
latch. Of course, it would be possible to extend the method and
choose a different output swing for the ex-or gates.
As in the divider by two, in principle the cells do not drive
the same external load. Hence, it is convenient to design the (16)
252 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 2, FEBRUARY 2007
Fig. 13. Voltage gain A needed to reach the wanted output swing (90% of
the nominal value) as a function of the parameter a, considering two different
design frequencies and two different values of the nominal swing. The current
consumption is also displayed and, as the case of the divider by 2 (Fig. 8) it
features a minimum for a = 3. V = 1:5 V.
We verified that optimized sizing of each cell can reduce
power consumption as much as 20% in typical divider designs
with respect to the case where the cells are identical.
B. Choice of the Design Parameters
Similarly to the previous case, the procedure presented in
Sections II and IV allows to design dividers by 3 sized to have
the nominal output swing and voltage gain . Neverthe-
less, the choice of the voltage gain and the factor for
proper operation is not obvious. The procedure for the choice
of the parameters has to be performed similarly to the case of
the divider by two. Results for the same benchmark technology
considered in the previous sections are reported in the following.
Fig. 13 plots the minimum voltage gain (of the differen-
tial pairs in the latches and in the ex-or gates) needed for proper
operation (as defined before) as a function of the factor. The
corresponding current consumption is also reported. As can be
seen, consistently with what we found for the divider by two,
the minimum consumption is achieved for . A number
of analyses performed on dividers designed for different input
frequency and load conditions gives the same result; thus, this
value will be taken as a reference for low power design. The
agreement of this result with what we found for the divider by
two is reasonable since the worst-case switching of the differ-
ential pair of the ex-or gates must be performed within half of
the period of the input clock, exactly as in the divider by two.
The plot in the left of Fig. 14 displays the minimum voltage
gain required for proper operation with as a function
of the design frequency, for different values of the voltage
swing. Again, simulations were run with input sine waves;
hence, lower frequency means lower slope at the zero crossing
of the input, requiring a larger voltage gain in the differential
pairs in order to amplify the input signal. The plot in the right
of Fig. 14 reports the current consumption corresponding to the
values in the left plot, that increases with and . amount of current required by the divider by 2.
Fig. 14. Left plot: minimum voltage gain, A , needed to reach the wanted
output voltage swing (90% of the nominal one) as a function of the design fre-
quency for different nominal voltage swing. Right plot: corresponding current
consumption. V = 1:5 V.
TABLE I
COMPARISON BETWEEN THE CURRENT CONSUMPTION OF A DIVIDER BY 2
AND A DIVIDER BY 3 DESIGNED FOR MINIMUM POWER CONSUMPTION (BY
VARYING A ) WITH V = 400 mV, a = 3 AND C = 20 fF. DIVIDERS
ARE DRIVEN BY A FULL-SWING SINE WAVE AND ARE DESIGNED IN THE
TECHNOLOGY CONSIDERED IN THE PREVIOUS SECTIONS
From a system-level point of view, it is interesting to compare
the current consumption required for a division by 2 and a divi-
sion by 3, that can be useful when planning a frequency synthe-
sizer. To this purpose, Table I summarizes the minimum current
consumption (obtained by varying with ) of the di-
vider by 2 and the divider by 3 for identical requirements (same
and ) at various design frequencies. The comparison
shows that the divider by 3, although made up of 6 MCML ele-
ments, requires, on average, only 25% more current then the di-
vider by 2. As mentioned before, the sensing phase of the latches
in the divider by 3 last half of the input period (exactly as the
sensing phase of the latches in the divider by 2), since the output
duty cycle of the ex-or gate is not 50%. On the other hand, the
latching phase of the same latches lasts one input period. This
facilitates the achievement of the nominal output swing in the
divider by 3 with respect to the divider by 2 when the slopes at
the zero crossing of the output waves are identical, i.e., when
the voltage gain of the differential pairs are identical. Since the
comparison in Table I is done for the same output swing (90%
of the nominal one), lower voltage gain can be used in the di-
vider by 3, which in turns means lower current consumption for
each MCML element. Note that, if identical voltage gains are
needed, the divider by 3 requires approximately three times the
NONIS et al.: DESIGN METHODOLOGY
It has finally to be pointed out that the dividers sized with
this procedure are designed for minimum power consumption.
Depending on phase noise requirements, it could be necessary
to increase the actual value of the factor (and thus the power
consumption), which means that the divider is designed for a
nominal frequency higher than the actual frequency at which it
will be operated, as can be demonstrated using the phase noise
model for MCML dividers proposed in [16].
V. CONCLUSION
In this work, a design methodology for the MCML latch is
presented and used as stepping stone to the design of frequency
dividers by two and by three with 50% output duty cycle. In
this approach, each latch inside a divider is designed separately
in order to minimize power consumption. Furthermore, output
swing, voltage gain and the ratio between the input period and
the time constant at the single-ended output node ( factor)
are exploited as free parameters to get further improvement in
power consumption. We found that for a broad range of di-
vider specifications, minimum power consumption is obtained
for . On the other hand, the choice of the voltage gain
strongly depends on the input frequency when the clock signal
is a pure sine-wave: high frequency of operation allows us to use
lower voltage gains, because of the higher value of the slope of
the clock signal at the zero crossing.
APPENDIX
EXPRESSIONS FOR CAPACITANCES USED IN (15)
The expression of the total capacitance connected at one of
the single-ended output of the ex-or gate in cell 1 (Fig. 11, see
also Fig. 10) is
where
is the ratio between and and has been chosen
equal to 1.5. These expression are used to obtain the following
parameters used in (15):
The expression for the total capacitance connected at one of the
single-ended output of the latch in cell 1 is
253
where
We thus define the following capacitive figures, valid for each
latch:
ACKNOWLEDGMENT
The authors would like to thank Z. Boos, U. Klepser,
M. Simon and N. Da Dalt for useful discussion and constant
support. The authors would also like to thank the reviewers for
useful suggestion to improve the quality of the manuscript.
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Roberto Nonis (S’04) was born in Udine, Italy, in
1977. He received the Laurea degree in management
engineering from the University of Udine, Udine,
Italy, in 2002. Since November 2003, he is working
toward the Ph.D. degree in electronics at the same
university.
His thesis concerned phase noise modeling in
PLL based frequency synthesizers. In 2003, he was
Visiting Student at Infineon Technologies, Villach
(Austria), where he worked on phase-locked loop
(PLL) design. His research interests are focused on
the design of RF frequency dividers.
Enzo Palumbo was born in Udine, Italy, in 1978.
He received the Laurea degree in electronic engi-
neering from the University of Udine, Udine, Italy,
in February 2005.
His thesis concerned the design strategies for the
MCML frequency dividers. Since 2005, he has been
with the Department of Electrical, Mechanical, and
Management Engineering (DIEGM), University of
Udine, working on frequency dividers.
Pierpaolo Palestri (M’05) received the Laurea
degree (summa cum laude) in electronic engineering
from the University of Bologna, Bologna, Italy, in
1998, and the Ph.D. degree in electronic engineering
from the University of Udine, Udine, Italy, in 2003.
In 1998, he joined the Department of Electrical,
Mechanical and Management Engineering of the
University of Udine as a Research Assistant in
the field of device simulation. From July 2000 to
September 2001 he held a Post-Doctoral position at
Bell Laboratories, Lucent Technologies (now Agere
Systems), Murray Hill, NJ, where he worked on high-speed silicon-germanium
bipolar technologies. In October 2001 he became Assistant Professor and in
November 2005 Associate Professor at the University of Udine. His research
interests include the modeling of carrier transport in nanoscale devices, and the
simulation of hot-carrier and tunneling phenomena in scaled MOSFETs and
nonvolatile-memory cells.
Luca Selmi (M’96) was born in Rome, Italy, in 1961.
He received the Doctorate degree in electronic en-
gineering from the University of Bologna, Bologna,
Italy, in 1992.
From April 1989 to June 1990, he was a Visiting
Scientist at Hewlett Packard Microwave Technology
Division, Santa Rosa, CA. Since 2000, he has been
a Full Professor of Electronics at the University of
Udine, Udine, Italy. His research interests are in the
field of electron device modelling and characteriza-
tion, with emphasis on CMOS scaling, nonvolatile
memories, and reliability. He held technical and coordination responsibility in
several national and European research projects (V and VI FP). His research
activities have been carried out in cooperation or under contract with the largest
semiconductor research laboratories and companies worldwide, including
Philips Research (Eindhoven and Leuven), Infineon Technologies (Villach and
Munich), IMEC, LETI, IBM T.J.Watson Res. Center, AT&T Bell Laboratories,
Hewlett Packard. He co-authored approximately 130 papers in refereed journals
and conference proceedings including more than 25 IEDM papers.
Dr. Selmi has been, or still is, member of the Technical program committees
of the major electron device conferences (IEDM – twice, ESSDERC, INFOS,
IRPS).