Prepared Questions

1. what is dft?
2. what is testing?
3. what is scan?
4. What is scan insertion?
5. What is boundary scan?
6. Tell me principals of boundary scan?
7. What is JTAG? How u will test?
8. 16 sate machines explain briefly?
9. What is data register?
10. Difference between flop and scan flop?
11. What is occ?
12. What is compression and ratio?
13. What is edt?
14. What is atpg and how you will test with atpg?
15. What are faults?
16. How you send the patterns through atpg?
17. What are the input and outputs of scan insertion?
18. What are the inputs and output of atpg?
19. What are transition faults, and how to test it?
20. Difference between loc and los and when launch pulse will occurs? how to detect the faults
with this?
21. What is simulation?
22. How to convert flop to scan flop?
23. Tell me about u r self?
24. You r dft guy, what r the topics u know?
25. Do u have idea about hdl, digital design?
26. How much do u rate for them
27. Task and function
28. Wire and reg
29. Case and casex
30. Full case and parallel case
31. Inter delay and intra delay
32. Latch and flip flop
33. Setup and hold time
34. What is the reason for these violations?
35. How to eliminate these violations
36. What will be the effect of output for these violations?
37. What is glitch
38. Lock up latch
39. Synchronous and asynchronous
40. Synchronous and asynchronous reset
41. $ monitor and $ finish
42. Scan design flow
43. Test coverage and fault coverage with examples
44. Difference b/w transition fault and stuck at faults with explanation with wave forms
45. About memory, simulation
46. What is occ
47. Explanation of transition fault with ckt diagram
48. Difference between ASIC and FPGA
49. Explain about named capture procedure
50. About EDT, compression, compression ratio
51. What u have done to increase test coverage from 99.43 to 99.8
52. Memory and types or RAM
53. Types of a simulation
54. Scan Insertion flow
55. Scan design methodologies
56. Scan cell designs
57. Adv and disadv of scan cell designs
58. Scan architecture
59. What happens if we partial?
60. Compression
61. Boundary scan
62. Why u r using SE in scan insertion instead of TE in the lab
63. Explain about combinational and sequential ATPG
64. Why u r using only muxed scan cell

1. What is sequential depth

2. How lock up latch is done in EDT logic
3. XOR conversion in compression logic of operation
4. At speed coverage is less compered to stuck at coverage why
5. Scan DRC rule and how to fix
6. In ATPG flow how DRC is changed
7. What is fault coverage and how to increase %?
8. Why DFT
9. Why scan
10. What happened when scan chain is balanced
11. DFT flow
12. What is DFT
13. Difference between fault coverage and test coverage
14. ATPG fault classes
15. Unstable faults and possible faults and undetected faults
16. What is the fault model? Different type of fault models
Random
Pseudo
17. Xor gate using mux
18. Scan cell replacement
 19. Type of simulation
20. Difference between transition fault and stuck at faults

Juntran technologies
1. What is DFT
2. what is simulation and ATPG
3. how to generate patterns in ATPG
4. differences between los and loc
5. serial simulation and parallel simulation
6. how to debug mismatch simulation
7. after doing stuck at why we go for transitions
8. how much coverage in stuck at and transition?
9. Types of faults
10. What is fault modal
11. D- Algorithm
12. What is the use encounter test?
13. What is use of simulation?
14. What is importance of scan
15. How to convert flop to scan flop
16. Will Scan work for analog ckts also?
17. What is the need of compression?
18. Types of compressions
19. Explain EDT architecture and how it will work and how it will compress the scan
chains
20. How ring generate decompress the patterns
21. What is the use of phase shifter?
22. What is the use of mask register?
23. What is the use of xor tree?
24. I have 100 flops, how many shift in and shift out and capture pulses
a. How you will implement compression for those 100 flops
b. After compression how many pulses are required (compression to 7 chains 1
channel)
c. How u will generate patterns for those flops
d. What will be the reduced time, data and memory?
25. Violations that you faced and how you debug them
26. Derived clock violation
27. What are the scan design types, which one is better and why?
28. How to insert test point and what are use of test points
29. What is boundary scan
30. Draw the architecture of boundary scan
31. What is INTEST and EXTEST
32. Inverter using mux
 33. Frequency divider by 3 ckt
34. What is MBIST

Test and Verification Solutions

1. What is noise margin
2. How many f/f for mod 32 counter
3. Mux using AND gate
4. Difference between synchronous and asynchronous design
5. What are the violations faced in scan insertion tool and ATPG;
6. Set up and hold
7. What will be the output if set up and hold violations?
8. Number of f/f required in moore state machine
9. What is jtag and why it is needed
10. What is use of ATPG?
11. Demorgans law
12. What is glitch
13. What is transition fault
14. Diff between combinational and sequential ckt and example
15. OR gate using mux
16. Diff b/w latch and flip flop
17. If the input of 4bit synchronous counter is 16mhz what is the frequency of output
18. ASIC and FPGA
19. Convert jk to D f/f
20. How u realize AND gate by using NAND gate
21. Tap controller
22. Diff b/w stuck at and transition fault
23. Type of faults
24. How many ff are required for MOD 16
25. Scan insertion
26. What is implicit even controller
27. Blocking and nonblocking
28. Task and function
29. Parameter
30. Test bench for 2X1 mux
31. What is use of testbench?
32. Intrinsic delay
33. What is 1149.7
34. 16 state fam and name of each state
35. Difference b/w exit 1 and exit 2
36. Speciality of tap controller
37. What is the simple technique to arrange the 350 bits as 1?