Experiment 12

Aim:- Verilog HDL Design examples of Moore machine and Mealy machine.
Software Used:-
 HDL Designer (version 2017.1a)
 Precision RTL Synthesis (version 2012b.10)
Important Concepts/Theory:-
Mealy State Machine
A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states. The block diagram of Mealy state machine is shown in the following
figure.

Figure 12.1 Block diagram of Mealy state

Figure 12.2 State diagram of Mealy state
machine
machine

As shown in figure, there are two parts present in Mealy state machine. Those are
combinational logic and memory. Memory is useful to provide some or part of previous
outputs presentstatespresentstates as inputs of combinational logic.
So, based on the present inputs and present states, the Mealy state machine produces outputs.
Therefore, the outputs will be valid only at positive ornegativeornegative transition of the
clock signal.In the above figure, there are three states, namely A, B & C. These states are
labelled inside the circles & each circle corresponds to one state. Transitions between these
states are represented with directed lines. Here, 0 / 0, 1 / 0 & 1 / 1 denotes input / output. In
the above figure, there are two transitions from each state based on the value of input, x.
In general, the number of states required in Mealy state machine is less than or equal to the
number of states required in Moore state machine. There is an equivalent Moore state
machine for each Mealy state machine.
Moore State Machine
A Finite State Machine is said to be Moore state machine, if outputs depend only on present
states. The block diagram of Moore state machine is shown in the following figure.
Figure 12.3 Block diagram of Mealy state Figure 12.4 State diagram of Moore state
machine machine

As shown in figure, there are two parts present in Moore state machine. Those are
combinational logic and memory. In this case, the present inputs and present states
determine the next states. So, based on next states, Moore state machine produces the
outputs. Therefore, the outputs will be valid only after transition of the state.

Design Analysis:-

Moore FSM

Codes:-
module else
moore(sequence_in,clock,reset,detector_out)
current_state <= next_state; // otherwise,
;
next state
input clock; input reset; input sequence_in
end
output reg detector_out;
// combinational logic of the Moore FSM
parameter Zero=3'b000, // "Zero" State
// to determine next state
One=3'b001, // "One" State
always @(current_state,sequence_in)
OneZero=3'b011, // "OneZero" State
begin
OneZeroOne=3'b010, // "OnceZeroOne"
case(current_state)
State
Zero:begin
OneZeroOneOne=3'b110;//
"OneZeroOneOne" State if(sequence_in==1)
reg [2:0] current_state, next_state; // current next_state <= One;
state and next state
else
always @(posedge clock, posedge reset)
next_state <= Zero;
begin
end
if(reset==1)
One:begin
current_state <= Zero;
if(sequence_in==0) next_state <= OneZero;

next_state <= OneZero; else

else next_state <= OneZeroOneOne;

next_state <= One; end

end OneZeroOneOne:begin

OneZero:begin if(sequence_in==0)

if(sequence_in==0) next_state <= OneZero;

next_state <= Zero; else

else next_state <= One;

next_state <= OneZeroOne; end

end default:next_state <= Zero;

OneZeroOne:begin endcase

if(sequence_in==0)

Results/Discussion:-
1.Waveform:

Figure 12.5 Moore FSM simulation

2.Report Results
a.RTL Schematic:

Figure 12.6 RTL Schematic of Moore

FSM
b. Tech Schematic:

Figure 12.7 Tech Schematic of Moore

FSM
c. Area Report

Figure 12.8 Area report of Moore FSM

Mealy FSM
Codes:-
module mealy(out, in, rst, clk); input clk, rst;

output out; reg out;

input in; reg[1:0] state;

parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3; s2: if(in==0) begin out=0; state=s3; end

always @(posedge clk or negedge rst) else begin out=0; state=s0; end

if(rst==0) begin state=s0; out=0; end s3: if(in==0) begin out=0; state=s1; end

else begin else begin out=1; state=s2; end

case (state) default: state=s0;

s0: if(in==0) begin out=0; state=s1; end endcase

else begin out=0; state=s0; end end

s1: if(in==0) begin out=0; state=s1; end endmodule

else begin out=0; state=s2; end

Results/Discussion:-
1.Waveform:

Figure 12.9 Mealy FSM simulation

 c. Area Report
2.Report Results
a.RTL Schematic:

Figure 12.10 RTL Schematic of Mealy

FSM

b. Tech Schematic:

Figure 12.12 Area report of Mealy FSM

Figure 12.11 Tech Schematic of Mealy

FSM
Conclusion:
Verilog HDL code for mealy and moore FSM has been implemented and their simulation
with signals has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6