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EXPERIMENT 8 Verilog
EXPERIMENT 8 Verilog
2-bit Comparator:
Logical Equations:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’
Fig.1: Logic Circuit of 2-bit Comparator A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 +
Table 1: Truth Table for 2-bit Comparator A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 +
A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A1’B1 + A0’B1B0 + A1’A0’B0
4-bit Comparator:
Logic Equation:
Design Analysis:
Codes:
1. 2-bit Comparator:
2. 4-bit Comparator:
3. 8-bit Comparator:
Results/Discussions:
Simulation (Waveforms)
1. 2-bit Comparator:
2. 4-bit Comparator:
3. 8-bit Comparator:
RTL Schematic:
1. 2-bit Comparator:
2. 4-bit Comparator:
3. 8-bit Comparator:
Tech Schematic:
1. 2-bit Comparator:
2. 4-bit Comparator:
3. 8-bit Comparator:
Area Report:
1. 2-bit Comparator:
2. 4-bit Comparator:
3. 8-bit Comparator:
Conclusion:
Verilog HDL code for 2-bit, 4-bit & 8-bit comparator has been implemented and their
simulation with signals has been tested.
Criteria Total Marks Marks Obtained Comments
Concept (A) 2
Implementation (B) 2
Performance (C) 2
Total 6