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  • Aim:-Verilog Implementation of 8 To 3 Priority

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    The document describes an experiment to implement an 8 to 3 priority encoder in Verilog. An 8 to 3 priority encoder prioritizes 8 inputs and encodes the position of the highest priority active input using 3 output bits. The experiment includes developing Verilog code for the priority encoder design, simulating the code to test the output signals against a truth table, and analyzing the design using area reports. The goal of experiment was to successfully implement and test an 8 to 3 priority encoder in Verilog.

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    7

    Original Title

    Experiment 7 Verilog

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    The document describes an experiment to implement an 8 to 3 priority encoder in Verilog. An 8 to 3 priority encoder prioritizes 8 inputs and encodes the position of the highest priority active input using 3 output bits. The experiment includes developing Verilog code for the priority encoder design, simulating the code to test the output signals against a truth table, and analyzing the design using area reports. The goal of experiment was to successfully implement and test an 8 to 3 priority encoder in Verilog.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    12 views5 pages

    Aim:-Verilog Implementation of 8 To 3 Priority

    Uploaded by

    uday
    The document describes an experiment to implement an 8 to 3 priority encoder in Verilog. An 8 to 3 priority encoder prioritizes 8 inputs and encodes the position of the highest priority active input using 3 output bits. The experiment includes developing Verilog code for the priority encoder design, simulating the code to test the output signals against a truth table, and analyzing the design using area reports. The goal of experiment was to successfully implement and test an 8 to 3 priority encoder in Verilog.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 5

    EXPERIMENT 7

    Aim:- Verilog Implementation of 8 to 3 Priority


    Encoder

    Important
    Concepts/Theory:-
    Priority Encoder: A priority encoder provide n bits of binary coded output representing the
    position of the highest order active input of 2 n inputs. If two or more inputs are high at the
    same time, the input having the highest priority will take precedence. Its applications includes
    used to control interrupt requests by acting on the highest priority request and to encode the
    output of a flash analog to digital converter.
    8 to 3 Priority Encoder

    Table 1: Truth table for 8 to 3 Priority


    Encode
    r

    Fig.1: Logic circuit of 8 to 3 Priority


    Encoder

    Output
    Expressions:
    Q0 = D1 + D3 + D5 +
    D7
    Q1 = D2 + D3 + D6 +
    D7
    Q2 = D4 + D5 + D6 +
    D7
    Design Analysis:-
    Codes:-

    Waveform: -

    RTL Schematic: -
    Tech Schematic:

    Area Report: -

    Conclusion:
    Verilog HDL code for 8 to 3 Priority Encoder has been implemented and their simulation with
    signals has been tested.

    Criteria Total Marks Marks Obtained Comments

    Concept (A) 2
    Implementation (B) 2

    Performance (C) 2

    Total 6

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