Experiment 10

Aim:- Verilog Implementation of Clock divider

Important Concepts/Theory:-

A clock divider is usually a device takes an input clock that is used to produce an output
clock. The output clock frequency is function of the input clock frequency where the output
clock frequency is the result of the input frequency divided by an integer. It is an electronic
device that is capable of dividing the frequency of a given digital input pulse train by a fixed
integer value, n. It often consists of an n-stage counter, the output frequency at the nth stage
of counting being an nth submultiple of the input frequency.

Clock divider by 2:

Fig.1: Circuit diagram of Clock Divider by 2

Fig.2: Output Waveform of Clock Divider

by 2
Design Analysis: -

Code: -

Clock Divider By N: -

Results: -

Simulation (Waveform)

Fig. 3: Simulated Waveform of Clock Divider by 2

 Fig. 4: Simulated Waveform of Clock Divider by 4

Report Results: -

RTL Schematic: -

Fig. 5: RTL Schematic of Clock divider

Tech Schematic: -
 Fig. 6: Tech Schematic of Clock divider

Area Report: -

Fig. 7: Area Report of Clock divider

Conclusion:
Verilog HDL code for Clock Divider has been implemented and their simulation with signals
has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6