Experiment 11

Aim:- Verilog implementation of binary multiplier and pulse counter.

Important Concepts/Theory:-
Binary multiplier:- A binary multiplier is a combinational logic circuit or digital device used
for multiplying two binary numbers. The two numbers are more specifically known
as multiplicand and multiplier and the result is known as a product. The multiplicand &
multiplier can be of various bit size. The product’s bit size depends on the bit size of the
multiplicand & multiplier. The bit size of the product is equal to the sum of the bit size of
multiplier & multiplicand. Binary multiplication method is same as decimal multiplication.
Binary multiplication of more than 1-bit numbers contains 2 steps. The 1 st step is single bit-
wise multiplication known as partial product and the 2 nd step is adding all partial products
into a single product.
Partial products or single bit products can be obtained by using AND gates. However, to add
these partial products we need full adders & half adders.

Fig. 1: Logic diagram of 4x4 multiplier using 4 bit full adder

Pulse counter:-
Counters, consisting of a number of flip-flops, count a stream of pulses applied to the
counter’s CK input. The output is a binary value whose value is equal to the number of pulses
received at the CK input.
Design Analysis:-
Codes:-
1. Binary Multiplier:

2. Pulse counter:
Results/Discussion:-
Simulation (Waveform):
1. Binary Multiplier:

Fig.2: Simulation of Binary multiplier

2. Pulse counter:

Fig.3: Simulation of pulse counter

Report Results:
1. Binary multiplier:
RTL Schematic:

Fig.4: RTL Schematic of binary multiplier

 Tech Schematic:

Fig.5: Tech Schematic of binary multiplier

Area Report:

Fig.6: Area Report of binary multiplier

 2. Pulse Counter:
RTL Schematic:

Fig.7: RTL Schematic of pulse counter

Tech Schematic:

Fig. 8: Tech Schematic of pulse counter

Area Report:

Fig. 9: Area report of pulse counter

Conclusion:
Verilog HDL code for binary multiplier and pulse counter has been implemented and their
simulation with signals has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6