EXPERIMENT 2

AIM: To implement Verilog HDL code for combinational circuits like Half adder, full adder
and full subtractor.
Important Concept/ Theory:

Combinational Logic Circuits are memoryless digital logic circuits whose output at any
instant in time depends only on the combination of its inputs. Combinational Circuits are
circuits made up of different types of logic gates. The outputs of Combinational Logic
Circuits are only determined by the logical function of their current input state, logic “0” or
logic “1”, at any given instant in time. The result is that combinational logic circuits have no
feedback, and any changes to the signals being applied to their inputs will immediately have
an effect at the output. In other words, in a Combinational Logic Circuit, the output is
dependant at all times on the combination of its inputs. Thus, a combinational circuit is
memoryless.

 Half Adder: The half adder adds two binary digits called as augend and addend and
produces two outputs as sum and carry; XOR is applied to both inputs to produce sum
and AND gate is applied to both inputs to produce carry. 

A S

HALF ADDER

B C

Fig.1 – Logic Circuit of Half Adder Fig.2 – Block Diagram of Half Adder

Table 1– Truth Table for half Adder

 Full Adder: The full adder adds 3 one-bit numbers, where two can be referred to as
operands and one can be referred to as bit carried in. And produces 2-bit output, and
these can be referred to as output carry and sum. A full adder can be constructed from
two half adders by connecting A and B to the input of one-half adder, connecting the
sum from that to an input to the second adder, connecting Ci to the other input and OR
the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B,
and Ci, and Co could be made the three-bit majority function of A, B, and Ci.

A S

B
FULL ADDER Cout

Cin

Fig.3 – Logic Circuit of Full Adder

Fig.4 – Block Diagram of Full Adder
Table 2- Truth Table For Full Adder

 Full Subtractor: Full subtractor is an electronic device or logic circuit which performs
subtraction of two binary digits. A full subtractor is formed by two half subtractors,
which involves three inputs such as minuend, subtrahend and borrow, borrow bit
among the inputs is obtained from subtraction of two binary digits and is subtracted
from next higher order pair of bits, outputs as difference and borrow.
 A D

B FULL SUBTRACTOR
Bout
Bin

Fig.6 – Block Diagram of Full Subtractor

Fig.5 – Logic Circuit of Full Subtractor

Table 3 – Truth Table for Full Subtractor

Design Analysis:
 Codes:
1. Half Adder Code:
2. Full Adder Code:

3. Full Subtractor Code:

Results/ Discussion :-
Simulation (waveforms):
 Half Adder:

 Full Adder: Fig.7 – Simulated Waveform for Half Adder

 Fig.8 – Simulated Waveform for Full Adder

 Full Subtractor:

Fig.9 – Simulated Waveform for Full Subtractor

Report results:
RTL Schematic:
 Half Adder:
 Fig.10 – RTL Schematic for Half Adder

 Full Adder:

Fig.11 – RTL Schematic for Full Adder

 Full Subtractor:

Fig.12 – RTL Schematic for Full Subtractor

Tech Schematic:
 Half Adder:
 Fig.13 – Tech Schematic for Half Adder
 Full Adder:

 Full Subtractor:
Fig.14 – Tech Schematic for Full Adder

Fig.15 – Tech Schematic for Full Subtractor

Area Report:
 Half Adder:

Fig.16 – Area Report for Half Adder

 Full Adder:
 Fig.17 – Area Report for Full Adder
 Full Subtractor:

Fig.18 – Area Report for Full Subtractor

Missing constraint report:

 Half Adder:

Fig.19 – Missing Constraints Report for Half Adder

 Full Adder:
 Fig.20 – Missing Constraints Report for Full Adder

 Full Subtractor:

Fig.21 – Missing Constraints Report for Full Subtractor

Conclusion:
Verilog HDL code for half adder, full adder & full subtractor has been implemented and their
simulation with signals has been tested.
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6