EXPERIMENT 4

Aim: Verilog Implementation of 2 to 4 and 3 to 8 decoders

Important Concept/ Theory:

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output lines.
One of these outputs will be active High based on the combination of inputs present, when
the decoder is enabled. That means decoder detects a particular code. The outputs of the
decoder are nothing but the min terms of ‘n’ input variables lines, when it is enabled.
 2 to 4 Decoder:

Fig. 1: Logic Diagram of 2 to 4 Decoder Fig. 2: Symbol of 2 to 4 Decoder

Table No. 1: Truth Table for 2 to 4 Decoder

 3 to 8 Decoder:
 Fig. 3: Logic Diagram of 3 to 8 Decoder Fig. 4: Symbol of 3 to 8 Decoder

Table No. 2: Truth Table for 3 to 8 Decoder

Minterm Equations:
O0 = C’B’A’; O1 = C’B’A; O2 = C’BA’; O3 = C’BA;
O4 = CB’A’; O5 = CB’A; O6 = CBA’; O7 = CBA;

Design Analysis:
Codes:
1. 2 to 4 Decoder:
 2. 3 to 8 Decoder:

Results/ Discussion:-
Simulation (waveforms):
2 to 4 Decoder:
 Fig. 5: Simulated Waveform of 2 to 4 Decoder

3 to 8 Decoder:

Fig. 6: Simulated Waveform of 3 to 8 Decoder

Report Results:
RTL Schematic:
2 to 4 Decoder:

Fig. 7: RTL Schematic of 2 to 4 Decoder

 Fig. 8: RTL Schematic of 3 to 8 Decoder
Tech Schematic :
2 to 4 Decoder:

Fig. 9: Tech Schematic of 2 to 4 Decoder

Fig. 10: Tech Schematic of 3 to 8 Decoder

Area Report:
2 to 4 Decoder:

3 to 8 Decoder:

Conclusion:
Verilog HDL code for 2 to 4 & 3 to 8 decoder has been implemented and their simulation
with signals has been tested.
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6