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Assignment 4 - CML - Mon - A
Assignment 4 - CML - Mon - A
Task : Design NMOS Common Gate Amplifier whose output is connected to another Common
Gate Amplifier having PMOS current mirror as load (second CGA is load for first CGA). The bias
current is 300 µA and total output voltage swing is 1.25 V. Assume channel length of 1 µm. VDD =
2 V. Assume equal overdrrive voltage for all transistors. What is the gain of this amplifier?
1. Calculate the width of all transistors and bias voltage for NMOS transistors.
3. Perform transient analysis with sinusoidal input (small signal) to find out gain from simulation.