EE457

Homework#4
Due April 11, 2016

Note:
 Read Chapters 4&5.
 100 points maximum, 20 points per problem.
Problem 1:
You should watch other videos as needed. Watch Videos #10, 11, 12, and 13. Write some key salient features
about these videos. A few sentences are fine.

Problem 2:
(a) Compute resistance of a copper interconnect where the thickness t = 2x10-4cm. length L=4mm and the
width W=800x10-6cm. Be careful with corners.
(b) Using the same sheet resistance, Rs, from part (a), find the resistance of the following layout metal
trace by calculating straight and corner squares.

155um
50um

5um

45um

30um

Problem 3:
(A)Calculate line capacitance of a chip interconnect that sits on top of silicon dioxide layer on a silicon
substrate. The interconnect is a copper trace where the thickness t = 2x10-4cm. length L=4mm and the
width W=800x10-6cm. The thickness of the silicon dioxide is 200 Angstroms. Note: 1Angstrom = 10-10m.
(B)Compute the fringe capacitance of part (A).

Problem 4
a) Using Electric, draw the schematic of F  AB  CD .
b) Using Euler’s path, find the optimum input permutation.
c) Layout in Electric. Run DRC check.
d) Extract the layout.
e) Do SPICE transient analysis of the layout. Put A=0, B=1, C=1 and D shown below.

0 5ns 10ns 20ns 25ns 35ns 45ns time

Timing Diagram for D Input

Problem 5:
For a TG circuit shown in class with 3 TG’s, calculate the final voltage, Vf, if your initial states were A=1, B=0,
C=0 and final states changed to A=1, B=1, C=1. The output capacitor is initially uncharged. Now change states
from previous A=1, B=1, C=1 to A=0, B=0, C=1. Find the final voltage at Vf.