EE537- Spring 2020

Digital Integrated Circuit Design

Instructor: Dr. Nasir Mohyuddin
Homework # 2 Solution

Due Date: 12/03/2020 at the beginning of the class

Problem 1
Consider a complex OAI432 gate which implements f  A1 A2 A3 A4  B1B2 B3  C1C2 .
a) Draw the transistor level diagram of this complex gate.
b) Assume (W/L)n=60 and (W/L)p=30. Calculate the W/L of an equivalent inverter
with the weakest pull-down and pull-up.
c) Do the Sticks layout of this gate with the minimal diffusion breaks to reduce the
number of polysilicon column pitches.

Solution
(a) The gate-level and transistor-level diagram of the OAI432 are shown bellow.
Vdd

A1 A2 A3 A4

B1 B2 B3

C1 C2

A1 B1 C1

A2

B2

A3

A4 B3 C3

(b) It can be seen that

W  1 W  1
       60  15
 L  eq, N 4  L  n 4
W  1 W  1
       30  10
 L  eq, P 3  L  p 3
(c) Euler’s path for N-net: A1, A2, A3, A4, B1, B2, B3, C1, and C2
Problem 2
In this problem you will size the decoder for a small memory.
Memories are organized as a two-dimensional array of memory cells. The decoder selects
one row from the memory by activating the row's wordline (a wire that runs across the
entire row). The decoder is split into two sections—a predecoder that combines some of
the inputs and a final stage that combines the outputs from the predecoders to select a
wordline. In this design the memory size will be 64 rows and 32 columns. As a result 6
address bits are required to identify the row to access. The decoder will be structured
such that the predecoder combines pairs of address lines and the final stage combines the
output of three predecode stages.
Use the following parameters:
Cg  C p  2 fF /  m
You are given the address and its complement (ie. A and ~A). The load presented by a
wordline and all memory cells connected to the wordline is 40fF. The capacitance of a
vertical wire connecting the predecoders to the final stages is 25fF. In the first parts of the
problem we will ignore the capacitance of these vertical wires, and solve the problem
assuming the only wire load is at the final decoder output.

a) Draw a diagram of this decoder. Assume that you have 3-input NAND gates, 2-
input NAND gates, and inverters. (Hint: use 2-input NAND gates for a pre-decoder
part.)

Solution:
 DECODER MEMORY CELL

Word Line[0]

Word Line[1]

Word Line[63]
~A[0]

~A[4]
~A[5]
A[0]
A[1]

A[1]

b) Each address input, both the true and the complement can each drive 5fF. Ignoring
the wire capacitance of the vertical lines, what is the total Path Effort from an input
to a wordline? Remember that in the problem there is a branching factor – each
output drives many identical gates. You need to work out (or read the text) about
how to account for this effect in this problem.

Solution:
F  BGH
B  26 2  16
4 5 20
G   1  1 
3 3 9
40 fF
H 8
5 fF
20
F  BGH  16   8  284.44
9
 c) Size the gates in the decoder for optimal performance (continue to ignore the
capacitance from the vertical wires).

Solution:
^
f  F 1/ 4  284.441/ 4  4.11
^
f  g1 h1  g 2 h2  g3 h3  g 4 h4  4.11
^
4 f
g1  , h1   3.08 , size of gate 2 = 3.08  5 fF  15.40 fF
3 g1
^
f
g 2  1, h2   4.11 , size of gate 3 = 4.1115.40 fF /16  3.96 fF
g2
^
5 f
g3  , h3   2.46 , size of gate 4 = 2.46  3.96 fF  9.73 fF
3 g3
^
f 40 fF
g 4  1, h4   4.11 ,  4.11 Correct!
g4 9.73 fF

5fF 15.40fF
3.96fF 9.73fF

Stage 1 Stage 2 Stage 3 Stage 4

Actually, size of each transistor should be n   , where n is an integer number, but

we ignore this at this problem for simplification.

Problem 3 (15pts)
In this problem assume that µn/µp=2 and all gates have equal rise and fall delays. Consider
the following circuit: The input capacitance of each input of the NAND4 gate is 10C.
a) You are free to scale each gate, except the 4-input NAND gate. Scale them in a
proper way to get the minimum worst-case delay. How much is the delay in this
case?
b) Now you are free to add as many as buffers that you want. How many buffers do
you need to make this circuit work faster? How much is the new delay after adding
buffers to this circuit?
 10C

192C

Solution:
a) G=2(4/3)(4/3)(5/3)=160/27
B=4×2=8
H=192/10
P=4+2+2+3=11
Delay = N(GBH)1/N+P= 4[(160/27) ×8× (192/10)]1/4+11=32.97
g1h1= g2h2= g3h3= g4h4=(GBH)1/N=5.49
Begin from load and go backward and calculate the input capacitance for each
gate.
Cin4=58.29C Cin3=28.31C Cin2= 6.87C

b) Nopt=log(GBH)/log3.59= 5.33
For N=6  delay = 31.46
We have to add two inverters (one buffer).

Problem 4
In this problem, assume µn/µp=2. Compute the logical and parasitic efforts of the following
gates using 2-input NOR as the reference template. Assume diffusion and gate
capacitances are equal.
a) Inverter
b) Two input NAND
c) Two input NOR

Solution:
For equal rise and fall delays, NAND2 has two NMOS and two PMOS transistors
each with size 2.
For equal rise and fall delays, Inverter has one NMOS transistor with size 1 and
one PMOS transistor with size 2.
For equal rise and fall delays, NOR2 has two NMOS transistors with size 1 and two
PMOS transistors with size 4.

Cin inv=3Cg Cin nand2= 4Cg Cin nor2= 5Cg

 Ri inv=R Ri nand2= R Ri nor2= R
Cp inv=3Cd Cp nand2=6Cd Cp nor2=6Cd

Cd=Cg
ginverter= 3CgR/5CgR=3/5 gnand2=4CgR/5CgR=4/5 gnor2=5CgR/5CgR=1
pinverter=3CdR/5CgR=3/5 pnand2=6CdR/5CgR=6/5 pnor2=6CdR/5CgR=6/5

Problem 5
Design an 8-input OR function. Explore all different architectures by using different input
NOR and NAND gates. You can also use inverters in your designs. Then, optimize each
one of your designs to have the minimum worst case delay. The input capacitance for each
input is 10C and the load capacitance is 1000C. Report the size of each gate for your
optimum design.
Hint: To find the minimum worst case delay, you have to find the optimum number of
stages.
Solution:
Architecture 1:

G=3×1×5/3=5 H=1000C/10C=100 B=1

Nopt=log(500)/log3.59=4.86
For N=4, D=4×(500)1/4+8=26.91
For N=6, D=6×(500)1/6+10=26.90  add two inverters.
Hence, Nopt=6 and the size of the gates from left to right are: 354C, 125C, 44C,
26C, 9C, 10C.
Architecture 2:

G=1× (4/3)×1×(4/3) ×1×(4/3)=64/27 H=100 B=1

Nopt=log(6400/27)/log3.59=6.86
For N=6, D=6×(6400/27)1/6+9=23.92
For N=8, D=8×(6400/27)1/8+11=26.84
Hence, Nopt=6 and the size of the gates from left to right are: 537C, 216C, 116C,
46C, 25C, 10C.
Architecture 3:
G=(5/3)×1×(5/3) ×1×(5/3) ×1=125/27 H=100 B=1
Nopt=log(12500/27)/log3.59=7.38
For N=6, D=6×(12500/27)1/6+9=25.68
For N=8, D=8×(12500/27)1/8+11=28.23
Hence, Nopt=6 and the size of the gates from left to right are: 359C, 215C, 77C,
46C, 16C, 10C.
The other architectures which can be used to implement an 8-input OR function:
NOR8-INV
INV-NAND8
NOR4-NAND2
NOR2-NAND4
NOR2-NAND2-NOR2-INV
NOR2-INV-NOR4-INV
INV-NAND2-INV-NAND4
INV-NAND4-INV-NAND2

You may find other architectures as well.