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Add R: Outline
Add R: Outline
Outline
• Prev Class
– Understanding an existing architecture
CISC to RISC • CISC : 8085 Example
– Analyze and Identify the difficulty or problem with
and CISC
MIPS Instruction Set
MIPS Instruction Set – Works division of some 8085 instruction
Works division of some 8085 instruction
• Listing of works done in executing instructions
A. Sahu • Simplifying instruction to make it RISC
CSE, IIT Guwahati – Simpler hardware : Data Path + Control
– Low power consumption
Please be updated with
http://jatinga.iitg.ernet.in/~asahu/cs222/ • MIPS
– ISA and Assembly Language Programming
8085 Microprocessor Architecture Instruction Size, Work and Timing
Bus 8 Bit
MUX
ADD R
ACC tmp R
IR W Z • Operation : ACC = ACC + R
B C
Flag
I D E • SIZE : 1 byte, 8 bit
Decode
H L
& • Time : 3 T Cycle
ALU M/C
Encodin
SP
g
PC
Inc/Dec. ter
/
• Work : Read R, Read ACC, Add, Write
Add latch
Result to ACC
Timing and Control Add Buff Data/Add
/
Buff
Instruction Size, Work and Timing Instruction Size, Work and Timing
ADD M INC M
• Operation : ACC = ACC + M[HL] • Operation : M[HL] = M[HL]+1
• SIZE : 1 byte, 8 bit • SIZE : 1 byte, 8 bit
• Time : 7 T Cycle • Time : 10 T Cycle
• Work : Read H, Read L, Put HL to Add • Work : Read H, Read L, Put HL to Add
Buff, Read M, Put Buff to Temp A, Buff, Read M, Put Buff to Temp A,
Read ACC, Add, Write Result to ACC Put 1 to TempB, Add, Write M
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Instruction Size, Work and Timing Instruction Size, Work and Timing
MVI A 34H LDA A 2000H
• Operation : ACC = ACC+37 • Operation : ACC = ACC+M[2000]
• SIZE : 2 byte 16 bit • SIZE : 3 byte, 24 bit
• Time : 7 T Cycle • Time : 13 T Cycle
• Work : Read I from IR, Read ACC, • Work : Read NextPC, Put to Add Buff,
Add, Write Result to ACC Read Next PC, add to Add Buff, Read
ACC, Add, Write Result to ACC
Instruction Size, Work and Timing Instruction Size, Work and Timing
PUSH D JMP 5000H
• Operation : M[SP] = D, SP‐‐, M[SP]=E, SP‐‐
• SIZE : 1 byte, 8 bit • Operation : PC = 5000
• Time : 12 T Cycle • SIZE : 3 byte, 24 bit
• W k R d SPH P
Work : Read SPH, Put to Add Buff, Read SPL, add
Add B ff R d SPL dd
to Add Buff, Read D, Put to Data Buff, Write to • Time : 12 T Cycle
Mem, Read SP,Put Temp1 1, ALU Sub, Write to
SP, Read SPH, Put to Add Buff, Read SPL, add to • Work : Read NextPC, Put to PCH,
Add Buff, Read D, Put to Data Buff, Write to
Mem, Read SP,Put Temp1 1, ALU Sub, Write to Read Next PC, Put to PCL
SP
Comparison Table
INS Size Work TCycle
ADD R 1 Byte A=A+R 3
ADD M 1 Byte A = A+M[HL] 7
INC M 1 Byte M[HL]=M[HL]+1 10 Instruction Set Design
MVI A 34H 2 Byte A=34 7
LDA 2000H 3 Byte A=M[2000] 13
PUSH D 1 Byte M[SP‐‐]=D,M[SP‐‐]=E 12
JMP 5000H 3 Byte PC=5000 10
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Instruction Set Design Instruction Set
• Keep all the instruction simple
– Number of work is upto 1 to 4 • How many different types instruction
– Size of instruction are almost same • Example
– Load store are separated from arithmetic INS, no • RISC : Around 80
combination of load and store
– No complex instruction
• CISC : Around 3000
CISC : Around 3000
– Controller and Data path simpler • OISC : 1
• Instructions are: mixed of complex and simple • ASIP : 100, N/W processor, DSP
instruction
– Number of work is upto 1 to 20 RISC ASIP
CISC
OISC X86
– CISC
Instruction Set Size
Instructions
• Cost of Hardware, Power, Area
• Language of the Machine
• Design time (of Hardware)
• Primitive compared to HLLs
• Code Size (CISC smaller, OISC bigger)
• Compile time
Compile time
• Easily interpreted by hardware
– CISC : Huge, may not take advantage of all the Instruction set design goals
hardware
• Execution time (Performance) • Maximize performance
• Minimize cost,
• Reduce design time
Type of Instructions Example: Instruction Set Architecture
MIPS
• Instructions for arithmetic • Representative of architectures developed since
• Instructions to move data the 1980's
• Used by NEC, Nintendo, Silicon Graphics, Sony
y , , p , y
• Instructions for decision making
I i f d i i ki • Real architecture but easy to understand
• Handling constant operands
MIPS: Microprocessor without Interlocked
Pipeline Stages : ISA
MIPS: Millions Instructions Per Sec: Measure
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MIPS Arithmetic MIPS Arithmetic
• Simplicity favors regularity
• All instructions have 3 operands • Operands must be registers, only 32 registers
• Operand order is fixed (destination first) provided (smaller is faster)
• Expressions need to be broken
Example:
C code: A = B + C C code MIPS code
MIPS code: add $s0, $s1, $s2 A = B + C + D; add $t0, $s1, $s2
E = F ‐ A; add $s0, $t0, $s3
(associated with variables by compiler) sub $s4, $s5, $s0
A mapped to $s0, B mapped to $s1 and C mapped to $s2 A mapped to $s0, B mapped to $s1 , C mapped to $s2
D mapped to $s3, E mapped to $s4, F mapped to $s5
Registers vs. Memory Memory Organization
0 8 bits of data
• Scalars mapped to registers 1 8 bits of data
• Viewed as a large, single‐
• Structures, arrays etc in memory dimension array, with an 2 8 bits of data
address. 3 8 bits of data
8 bits of data
Control Input • A memory address is an 4 8 bits of data
index into the array
Memory 5 8 bits of data
Datapath Output
• "Byte addressing" means
that the index points to a 6 8 bits of data
Register Names and Purpose Words and Bytes
Register
Name Usage
number
$zero 0 the constant value 0 • 232 bytes : byte addresses from 0 to 232‐1
$v0-$v1 2-3 values for results • 230 words : byte addresses 0, 4, 8, ... 232‐4
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries Bi
Big endian
di byte order
b t d 0 1 2 3
4 5 6 7
$s0-$s7 16-23 saved
$t8-$t9 24-25 more temporaries Little endian byte 3 2 1 0
$gp 28 global pointer order 7 6 5 4
$sp 29 stack pointer 3 2 1 0
$fp 30 frame pointer Non‐aligned word 7 6 5 4
$ra 31 return address
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Instructions to access memory
• Load and store instructions
• Example:
C code:
C code: A[8] = h + A[8];
A[8] = h + A[8];
MIPS code: lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 32($s3)
&A mapped to $s3 and h mapped to $s2