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Vol. 36, No. 11 Journal of Semiconductors November 2015

The single-event effect evaluation technology for nano integrated circuits

Zheng Hongchao(郑宏超)1; Ž , Zhao Yuanfu(赵元富)1 , Yue Suge(岳素格)1; 2 , Fan Long(范隆)1 ,
Du Shougang(杜守刚)1 , Chen Maoxin(陈茂鑫)1 , and Yu Chunqing(于春青)1
1 Beijing Microelectronics Technology Institute, Beijing 100076, China
2 Beijing University of Aeronautics & Astronautics, Beijing 100191, China

Abstract: Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-
event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and
classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test tech-
nology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser
irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present
understanding of the mechanisms for SEEs, which have been well verified experimentally.

Key words: single-event effect; heavy ion test; radiation evaluation method
DOI: 10.1088/1674-4926/36/11/115002 EEACC: 2570

1. Introduction However, the definition of the failure standards for mixed-

With the progress of semiconductor technology, the proba-
bility of single-event transients (SETs) and single-event upsets
(SEUs) in nanometer-scale integrated circuits has increased.
The critical charge threshold for single event effects (SEEs) is
reduced, while the probability of single-event-induced charge
sharing has increased due to the reduction of cell area. This
has led to a new class of SEE called multi-bit/multi-cell upset
(MBU/MCU)Œ1 .
Therefore, the evaluation methods of single-event effects
should increase in number for nanometer-scale circuits since
the SEE sensitivity has increased. Furthermore, it is difficult
to configure and test complex circuits such as a mixed-signal
system on a chip (SOC) with tens of millions of logic gates.
Novel circuit structures of a design for test (DFT) nature
have been investigated and designed for the SEE evaluation of
various circuit modules. Novel evaluation methods of single
event function interrupt (SEFI) in complex applications have
also been explored, as well as high frequency and high speed
online test technology. In this paper, the SEE evaluation tech-
nology of nanometer-scale circuits is divided into four parts:
assessment standard, evaluation method, testing technology,
and radiation testing.
2. Evaluation standards
Currently, the existing standards for single-event test-
ing are ESCC-25100, MIL-STD750E, ASTM-F1192, JESD57,
and JESD89Œ2 6 . A common feature of the above standards is
that the operation procedure of single-event testing is described
in detail and the number of samples in heavy-ion radiation, ion
energy, dose rate, total ionizing dose, and other requirements
are clearly defined. The standards are suitable for evaluating a
circuit (such as SRAM and A) for a single function or structure
and for radiation tests of a class of single-event effects (such
as SEU and SEL).
signal, large-scale integrated circuits, is not given in these stan-
dards. The classification methods for error statistics and the
traditional approach for evaluating the single-event effect in-
dex of sub-modules are not suitable for evaluating the single-
event performance in all applications. Therefore, experimental
schemes for each test program are customized.
There is no uniform standard specified in the functional
evaluation, so it is difficult to compare the performance of dif-
ferent circuits. Furthermore, the definitions of Weibull fitting,
LET threshold, saturated cross section, and evaluation of error
rates on-orbit are different across different standards. In the ac-
tual operation, there is a large statistical error for some defini-
tions (e.g., it is difficult to perform a Weibull fit on the actual
test data if the fitting degree of the actual test data is not high,
or the deviation for extracting the saturation section and LET
threshold is great). In addition, there is no uniform prescription
for the fitting software and error rate evaluation software in the
standards, which causes deviation during the processing of test
data.
In summary, the existing standard and specification system
is not fully applicable to nanometer-scale radiation hardened
ICs, and the single-event effects at all possible levels of nano
technology need further study. In order to meet the require-
ments for single-event effects evaluation of nanometer IC, a
more detailed evaluation method of the test needs to be devel-
oped on the basis of the existing standard and specification.
The test flow for heavy-ion-induced SEUs is shown in Fig-
ure 1Œ1 . The first test should be performed at a high LET in
order to establish limits for the basic cross section range of
the device under test (DUT). In the measurement of the SEU
cross section, the bias voltage is chosen according to the cir-
cuit technology types (such as minimum voltage of standard
bulk-silicon devices) to ensure that the DUT operates under the
worst-case conditions. The particle fluencies should reach 1 
107 cm 2 or the number of upsets achieved should be 100. The
fluence should be increased to 5  107 cm 2 in cases where

† Corresponding author. Email: hongchao_zheng@163.com

Received 11 June 2015, revised manuscript received 23 July 2015 © 2015 Chinese Institute of Electronics

115002-1
J. Semicond. 2015, 36(11)
Figure 1. Test flow of heavy-ion SEUs.
there are no SEUs measured to determine the LET threshold of
the DUT. The DUT current must be monitored in real time dur-
ing the experiment to determine whether an SEL happens and
the current suddenly increases and cannot recover. SEL eval-
uation should be performed under the worst-case condition of
high temperature at 125 ıC, the highest LET, and the maxi-
mum bias voltage. The SEU data will be enhanced by chang-
ing ion types and LETs and repeating the experiment. Further-
more, angle tests at 30ı and 45ı can be carried out to obtain
the MBU/MCU sensitivity of the DUT. It is worth mentioning
that the irradiation angle of horizontal and vertical direction
can have differing MBU/MCU sensitivity. The total ionizing
dose of DUT should be calculated at the last stage of the ex-
periment and should not exceed 80% of the DUT maximum
TID to ensure that the DUT can work properly for accuracy
of the SEU test. According to the specification, the test should
include at least 5 different LETs and the number of samples
should be 3 or more. The experiment test data are fitted to a
Weibull curve to obtain the saturation error cross section and
LET threshold. The LET threshold is defined as the maximum
LET at which no SEUs are detected, while another definition is
the LET value of the 1% (or 10%) of the saturation error cross
section on the Weibull curve. Proton SEE testing is suggested
when the LET threshold of the DUT used on the LEO track is
less than 40 MeV
cm2 /mg and especially if the LET threshold
is less than 15 MeV
cm2 /mg. Proton tests are generally per-
formed below 200 MeV, and the test procedure and method
are the same as with heavy-ions, except that the metric used is
not LET but MeV.
3. Evaluation method
When high-energy particles pass through the critical re-
gions of a phase-locked loop (PLL) circuit, the ion strike de-
posits energy and generates electron-hole pairs. These gener-
ated charge carriers can then be collected at the device termi-
nals, leading to a transient current pulse on the struck node.
The current pulses have a negative impact on the function of
the PLL and can disrupt the system. A PLL system consists of
many sub-circuits, so there are many sensitive nodes in a sin-
gle PLL circuit. However, not all nodes sensitive to ion strikes
will cause a serious impact on the output of the PLLŒ2 .
The research for single-event effects in single func-
115002-2
Zheng Hongchao et al.
Figure 2. SEU/SET test system diagram of nano-scale IC.
tion/structure circuits (such as SRAM, FLASH, ADDA,
FPGA, and CDC) is relatively mature internationally. Based
on the fact that the types of SEEs indifferent circuits
have been thoroughly studied, the SEE test schedules for
SEU, SET, SEFI, SEL, SEB, and SEGR effects are well-
established. When the technology is scaled to the nanome-
ter level, the single-event evaluation method for a single
function/structure of the circuit is still applicable, but the
LET threshold of circuits is lower. Therefore, the number
of single-event effects will be higher. For a variety of func-
tions/structure of nano-scale complex mixed-signal integrated
circuits (such as SOC, ASIC)Œ7 9 , a system can feature large-
scale, multi-module, complex-functions for the integration of
the analog/digital IP, PLL, high-speed interface, memory units
(DFF/SRAM/CACHE/REG), and other circuit structures. This
type of circuit tends to have a variety of single-event effects and
different programs show different sensitivity to single-event
effects. In recent years, the study of SEE evaluation methods on
complex, mixed-signal circuits can be divided into two ways:
(1) The test method of SEU/SET is executed based on the
built-in-self-test. Figure 2 shows the SEU/SET test system di-
agram.
This method is mainly used to evaluate the characteris-
tics of SET and SEU inside sensitive cells by sub-module.
The built-in-self-test usually contains a scan chain test method,
which strings the internal trigger as a chainŒ10; 11 , and the SET
and SEU occurring in flip–flops can be evaluated through real-
time statistics from the output errors. In order to ensure the
accuracy of SET testsŒ12; 13 , the focus of current study is on
improving the clock tree structure of the scan chain, which im-
proves the operating frequency of the scan chain toward the
maximum operating frequency of the circuit. A memory built-
in-self-test (MBIST) methodŒ14 using MARCH algorithms to
write/read all the RAM cells traversing the entire address and
the number of errors, which is shown in the forms of pulse, is
counted automatically. The focus of the current study is to lo-
cate the address where SEU occurs, in order to distinguish be-
tween the SBU (single-bit upsets) and MBU (multi-bit upsets);
the method of capturing SET by pulse width detection circuit is
to connect the output of combinational logic to a custom latch
chain. When an SET occurs in the combinational logic circuit,
J. Semicond. 2015, 36(11)
Figure 3. The evaluation method of single event effects under a certain application.
it is transmitted to the latch chain with a delay function. Based
on the output value of the latch, the pulse width of SET can
be estimated and the statistics of the number of SET can be
obtained.
The method for the read and return instructions of register
(REG)/cache is to compile program instructionsŒ15 . Fixed data
is written to register and cache, and then read back in real time
during irradiation to determine if SEUs occur. In the end, a sta-
tistical number of SEUs is obtained. The evaluation of a single
module with one SEE can be easily achieved by the built-in-
self-test described above and then the intrinsic sensitivity of
each individual memory cell can be determined.
(2) The evaluation method for the target circuit in the ap-
plication state.
It has been proposed that the usage of internal resources
is determined by the software executed on the target cir-
cuitŒ16; 17 . The SEE sensitivity of complex, large scale inte-
grated circuits varies greatly across different test programs and
different operating modes. All these phenomena can be due to
the impact of the duty cycle of the program. The duty cycle
is the percentage of time that the resource is active. The us-
ages of the functional units are different in the implementation
of the application test programs but are less than 100%. The
SEUs that occur in unused registers and memory will have no
effect on the device. In order to evaluate the SEE sensitivity of
devices overall, the discrepancy of single-event effects sensi-
tivity caused by different test programs is considered. An eval-
uation method to predict the applied cross section of complex
integrated circuits under different test programs is determined,
which is based on the duty cycle. Different test programs call
for different resources at different times. Through the design
of different test programs, the instructions for each functional
unit are separately controlled by the test programs. By combin-
ing the intrinsic cross section and the duty cycle, the applied
cross section under different test programs can be predicted.
Further, the intrinsic cross section of each functional unit can
be determined by the test results of SEE under different test
programs. Therefore, the error rate of the target circuit under
any test program can be obtained. The test mode which gen-
erated the largest error rate is the worst-case test mode. The
evaluation method of single-event effects under a certain ap-
plication is illustrated in Figure 3.
During the evaluation of single-event effects, two effects
between functional interrupt and instantaneous functional er-
ror should be distinguished. The former refers to an interrup-
tion that occurs due to the program runaway, and an external
reset is needed to recover; the latter refers to an instantaneous
functional error which can resume normal operation automat-
ically after a period of abnormal operation of the circuit. Both
of the two belong to the single-event functional error but have
115002-3
Zheng Hongchao et al.
differing degrees of impact. The latter can be corrected by pro-
gramming a detection mechanism, or operation errors can be
avoided by regular updates. Therefore, the statistics of these
two phenomena require their respective tests to be done sepa-
rately. When measuring the indicators of a single-event func-
tional error in a circuit, the total number of errors or interrup-
tions should be chosen according to the application require-
ments.
Based on the evaluation method of duty cycle, the func-
tional evaluation of a CPU with PERM and TOWER programs
is carried out to get the single event cross section under differ-
ent applications, which is compared with the results of heavy-
ion irradiation. The results of Cl and Ti ions are shown in Table
1, in which the duty cycle is equal to the application cross sec-
tion divided by the intrinsic cross section. It can be seen that
the maximum deviation of the duty cycle is no more than 20%,
which means the evaluation method of the duty cycle can be
used effectively to evaluate the single-event cross section on
complex large-scale integrated circuits under different appli-
cations.
4. Testing technology
SEE experiments using heavy-ion accelerators generally
require the development of a specialized SEE test system. The
test system requires remote control and real-time data collec-
tion, and the test board size and the size of the test equipment
is limited by the available space at the test siteŒ17 19 . There-
fore, the board-level embedded test system set up combined
with small-scale measurement equipment, high speed data ac-
quisition boards, and real-time data acquisition are used during
experiments and data is stored in the control computer. The
problems of the nano circuits test are shown in Figure 4.
Nanoscale digital VLSI circuits operating frequencies can
reach 300 MHz or more. The data bus transfer is rated up to
400 Mbps and the number of test pins is over 400. The FPGAŒ7
and ARM-based embedded systems can only operate at a fre-
quency of about 200 MHz when monitoring 100 pins. It is dif-
ficult to meet the multi-pin test, while maintaining high-speed
control.
The hardware of the test system needs to focus on high-
speed SEE error test technology and functional application
test miniaturization technology. We can design and build a
dedicated high-speed data acquisition card combining multi-
ple systems into a hybrid test system. The FPGA-based multi-
distribution mode test systems can also be applied. For a nano-
circuits SEE test board, the requirements of anti-surge, ground
bounce, and signal reflection of electromagnetic interference
will be higher than micro-circuitry regardless of what kind of
speed the test system is capable of. For the evaluation of the ac-
J. Semicond. 2015, 36(11)
Table 1. Comparison of evaluation and experiment cross section results.
ICON LET Mode Intrinsic cross Experiment
(MeV
cm2 /mg) section application
(cm2 /dev) cross section
(cm2 /dev)
Cl 13.6 PERM 2.13  10 4 1.55  10
Cl 13.6 TOWER 2.13  10 4 2.33  10
Ti 22.2 PERM 2.03  10 4 1.87  10
Ti 22.2 TOWER 2.03  10 4 2.35  10
Figure 4. The problems of nano circuits test.
curacy of single-particle test data results, signal lines of equal
length and the opposite signal canceling interference meth-
ods need to be considered in order to avoid disturbance rejec-
tion caused by system abnormalities. Additionally, more high-
speed ether net protocol needs to be developed because of the
low transfer rate of the RS232/485 and the transmission dis-
tance limit of USB.
The signal will be affected by routing and layout in nano-
scale circuits test board because of the signal arrival time in-
consistency in each node and the reflected signal also reaching
a node inconsistently, resulting in deterioration of signal qual-
ity. In general, the same number of multi-node branches can
be controlled by star topology where signal transmission and
reflection time delay are equal, which improves signal quality.
Power supply stability contributes to the increasingly-
strict requirements of nano integrated circuits. The high-speed
switching of circuit will inevitably produce power line volt-
age drop and electromagnetic interference with high-frequency
components. Multiple methods are used to reduce the inter-
ference from the power supply system. First, the analog and
digital power supply in a nano-circuit test board will be sepa-
rated and connected together at the input to the power supply.
Second, power lines will be kept in parallel with the ground
line as far as possible, and at the same time, the power wire,
ground wire, and the direction of data transmission must be in
the same direction. Lastly, decoupling capacitors on one side of
the power line will reduce the power line voltage fluctuations.
The higher demands for signal bandwidth would also be
implemented in the nanoscale integrated circuits by utilizing
the application of multi-channel transmission. The traditional
point-to-point physical layer interface is clearly not suitable for
increasing data transmission rates, due to its slow speed slow,
power consumption, noise and other performance factors. With
115002-4
Zheng Hongchao et al.
Soft Experiment Soft Deviation
application duty factor duty factor (%)
cross section (fi-e) (%) (fi-s) (%)
(cm2 /dev)
5 1.66  10 5 7.28 7.8 6.67
5 2.42  10 5 10.94 11.37 3.78
5 1.58  10 5 9.21 7.8 18.1
5 2.31  10 5 11.58 11.37 1.85
the development of LVDS technology, the above problems
have been alleviated to some extent. LVDS can achieve low
supply voltage and small voltage swing. For a difference sig-
nal bias of 1.2 V, a 400 mV swing can be achieved, and the
most extreme contributions to noise are eliminated. LVDS can
work under any power supply voltage, which can realize the
stability of the power supply system. The power supply sys-
tem can be changed little when the power supply voltage of
the power supply voltage dependence is lower.
In the test system software design, the low-efficiency of
the code in test vectors and state control should be resolved in
order to ensure that SEE errors can be captured as quickly as
possible by optimizing data storage structures and algorithms,
control code size, and software delay. Then we can build a
more complete state control to meet different application fea-
tures and switching conditions at a variable configuration, and
errors can be traced back to determine the time and area of SEE
errors. Additionally the common state control and high-speed
data transmission IP modules need to be established to meet the
engineering requirements of different test circuits in the same
platform control.
5. Radiation test
Three methods can be used for experimental investigation
of SEEs: heavy-ion, proton and laser irradiation. Obviously
particle irradiation tests require access to an adequate accel-
erator facilityŒ20 . Laser testing at a pulsed laser facility can
be used in SEE evaluation and sensitivity analysis without the
need for access to expensive accelerator facilities.
Five ion species with varying LET would be used to evalu-
ate the threshold of latch up and SEE saturation cross section in
the heavy ion experiment, which requires a maximum ion LET
of more than 75 MeV
cm2 /mg. The remaining four species de-
termine the SEE threshold and Weibull curve. The LET thresh-
old of nanoscale digital circuits would be 20 MeV
cm2 /mg or
less. Since accelerators only generate specific LET values, in
order to reduce the statistical error LET threshold value, one
kind of ion LET with a threshold of more than 20 would be ap-
plied, with the remaining three species around the SEE thresh-
old and having one ion species with LET below the SEE thresh-
old.
The effective LET of energetic nuclear recoils induced by
high-energy proton collisions in Si material is calculated to be
about 15 MeV
cm2 /mg. Therefore, the proton SEE cannot be
neglected for nano-circuits with the SEE threshold of no more
than 15 MeV
cm2 /mg, especially for the crafts applied on the
LEO orbit. Thus, the proton experiment should be considered
for nano-circuits. The proton SEE test procedures and require-
J. Semicond. 2015, 36(11)
ments are the same as in the heavy-ion experiment, except that
the use of proton energy (MeV) is used as a metric instead of
LET.
Habing first suggested that unfocused pulsed-laser light
could be used to simulate electron and gamma-ray dose rate
effects because both photons and particles ionize matter by
liberating electrons from their constituent atomsŒ21 . Several
groups in radiation research have focused on the issues of
pulsed-laser induced SEEs. The increased use of the pulsed
laser for SEE studies in recent years may be attributed to the
confluence of several factors, including: the scaling of transis-
tors to the point where they are becoming highly sensitive to
SEEs, the availability of commercially manufactured picosec-
onds pulsed-lasers in the required wavelength range, the cost
and limited time available at accelerators for testing, and the
lack of spatial and temporal information obtained from broad-
beam accelerator testing.
A popular time-domain, laser-based SEE research is pre-
sented in Reference [22], where the authors developed a time-
domain, laser-based SEE test approach for nanoscale high-
speed SerDes and phase lock loop (PLL) devices, which al-
lows the oscilloscope and laser to each run at its own char-
acteristic frequency. These approaches are applicable to other
high-speed circuits including analog, mixed-signal, and digital.
Advantages of the time-domain approach include the ability
to characterize the full range of SETs, even varying program-
to-program requirements, and to gather a data set that al-
lows significant flexibility in terms of post-processing of the
data beyond error identification and characterization. A space-
domain, laser-based SEE research is presented in Reference
[21], and is based on the advantages of the adjustability of the
laser focal panel and the penetrability through the silicon sub-
strate, and irradiation from the backside; the depth of sensitive
volume in the longitudinal direction and the sensitive mapping
in the transverse direction can be determined using this method.
These methods can provide essential physical-structure-level
information for layout-level radiation hardness and the estab-
lishment of SEE sensitive volume.
6. Conclusion
In summary, the single-event effect evaluation of a nano-
radiation-hardened integrated circuit is a hot topic in the
field of radiation effects and reliability of electronic devices.
Nanoscale technology circuits present functional complexity
and a diversity of single-event effects. Thus, further study of
the radiation effects assessment methods is required, and en-
hancement of existing SEE test systems to solidify and unify
the forms of verification is required in order to meet nano cir-
cuits radiation-hardened evaluation requirements.
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