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The Single EVent Effect Evaluation Technology For Nano Integrated Circuits PDF
The Single EVent Effect Evaluation Technology For Nano Integrated Circuits PDF
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Abstract: Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-
event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and
classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test tech-
nology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser
irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present
understanding of the mechanisms for SEEs, which have been well verified experimentally.
Key words: single-event effect; heavy ion test; radiation evaluation method
DOI: 10.1088/1674-4926/36/11/115002 EEACC: 2570
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J. Semicond. 2015, 36(11) Zheng Hongchao et al.
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J. Semicond. 2015, 36(11) Zheng Hongchao et al.
Figure 3. The evaluation method of single event effects under a certain application.
it is transmitted to the latch chain with a delay function. Based differing degrees of impact. The latter can be corrected by pro-
on the output value of the latch, the pulse width of SET can gramming a detection mechanism, or operation errors can be
be estimated and the statistics of the number of SET can be avoided by regular updates. Therefore, the statistics of these
obtained. two phenomena require their respective tests to be done sepa-
The method for the read and return instructions of register rately. When measuring the indicators of a single-event func-
(REG)/cache is to compile program instructionsŒ15 . Fixed data tional error in a circuit, the total number of errors or interrup-
is written to register and cache, and then read back in real time tions should be chosen according to the application require-
during irradiation to determine if SEUs occur. In the end, a sta- ments.
tistical number of SEUs is obtained. The evaluation of a single Based on the evaluation method of duty cycle, the func-
module with one SEE can be easily achieved by the built-in- tional evaluation of a CPU with PERM and TOWER programs
self-test described above and then the intrinsic sensitivity of is carried out to get the single event cross section under differ-
each individual memory cell can be determined. ent applications, which is compared with the results of heavy-
(2) The evaluation method for the target circuit in the ap- ion irradiation. The results of Cl and Ti ions are shown in Table
plication state. 1, in which the duty cycle is equal to the application cross sec-
tion divided by the intrinsic cross section. It can be seen that
It has been proposed that the usage of internal resources
the maximum deviation of the duty cycle is no more than 20%,
is determined by the software executed on the target cir-
which means the evaluation method of the duty cycle can be
cuitŒ16; 17 . The SEE sensitivity of complex, large scale inte-
used effectively to evaluate the single-event cross section on
grated circuits varies greatly across different test programs and
complex large-scale integrated circuits under different appli-
different operating modes. All these phenomena can be due to
cations.
the impact of the duty cycle of the program. The duty cycle
is the percentage of time that the resource is active. The us-
ages of the functional units are different in the implementation 4. Testing technology
of the application test programs but are less than 100%. The
SEUs that occur in unused registers and memory will have no SEE experiments using heavy-ion accelerators generally
effect on the device. In order to evaluate the SEE sensitivity of require the development of a specialized SEE test system. The
devices overall, the discrepancy of single-event effects sensi- test system requires remote control and real-time data collec-
tivity caused by different test programs is considered. An eval- tion, and the test board size and the size of the test equipment
uation method to predict the applied cross section of complex is limited by the available space at the test siteŒ17 19 . There-
integrated circuits under different test programs is determined, fore, the board-level embedded test system set up combined
which is based on the duty cycle. Different test programs call with small-scale measurement equipment, high speed data ac-
for different resources at different times. Through the design quisition boards, and real-time data acquisition are used during
of different test programs, the instructions for each functional experiments and data is stored in the control computer. The
unit are separately controlled by the test programs. By combin- problems of the nano circuits test are shown in Figure 4.
ing the intrinsic cross section and the duty cycle, the applied Nanoscale digital VLSI circuits operating frequencies can
cross section under different test programs can be predicted. reach 300 MHz or more. The data bus transfer is rated up to
Further, the intrinsic cross section of each functional unit can 400 Mbps and the number of test pins is over 400. The FPGAŒ7
be determined by the test results of SEE under different test and ARM-based embedded systems can only operate at a fre-
programs. Therefore, the error rate of the target circuit under quency of about 200 MHz when monitoring 100 pins. It is dif-
any test program can be obtained. The test mode which gen- ficult to meet the multi-pin test, while maintaining high-speed
erated the largest error rate is the worst-case test mode. The control.
evaluation method of single-event effects under a certain ap- The hardware of the test system needs to focus on high-
plication is illustrated in Figure 3. speed SEE error test technology and functional application
During the evaluation of single-event effects, two effects test miniaturization technology. We can design and build a
between functional interrupt and instantaneous functional er- dedicated high-speed data acquisition card combining multi-
ror should be distinguished. The former refers to an interrup- ple systems into a hybrid test system. The FPGA-based multi-
tion that occurs due to the program runaway, and an external distribution mode test systems can also be applied. For a nano-
reset is needed to recover; the latter refers to an instantaneous circuits SEE test board, the requirements of anti-surge, ground
functional error which can resume normal operation automat- bounce, and signal reflection of electromagnetic interference
ically after a period of abnormal operation of the circuit. Both will be higher than micro-circuitry regardless of what kind of
of the two belong to the single-event functional error but have speed the test system is capable of. For the evaluation of the ac-
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J. Semicond. 2015, 36(11) Zheng Hongchao et al.
Table 1. Comparison of evaluation and experiment cross section results.
ICON LET Mode Intrinsic cross Experiment Soft Experiment Soft Deviation
(MeVcm2 /mg) section application application duty factor duty factor (%)
(cm2 /dev) cross section cross section (fi-e) (%) (fi-s) (%)
(cm2 /dev) (cm2 /dev)
Cl 13.6 PERM 2.13 10 4 1.55 10 5 1.66 10 5 7.28 7.8 6.67
Cl 13.6 TOWER 2.13 10 4 2.33 10 5 2.42 10 5 10.94 11.37 3.78
Ti 22.2 PERM 2.03 10 4 1.87 10 5 1.58 10 5 9.21 7.8 18.1
Ti 22.2 TOWER 2.03 10 4 2.35 10 5 2.31 10 5 11.58 11.37 1.85
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J. Semicond. 2015, 36(11) Zheng Hongchao et al.
ments are the same as in the heavy-ion experiment, except that [4] American Society for Testing and Materials (ASTM). ASTM-
the use of proton energy (MeV) is used as a metric instead of F1192-11: Standard Guide for the Measurement of SEP Induced
LET. by Heavy Ion Irradiation of Semiconductor Devices, 2011
Habing first suggested that unfocused pulsed-laser light [5] Joint Electronics Device Engineering Council (JEDEC).
could be used to simulate electron and gamma-ray dose rate JESD57-1996: Test Procedures for the Measurement of Single-
Event Effects in Semiconductor Devices from Heavy Ion
effects because both photons and particles ionize matter by
Irradiation, 1996
liberating electrons from their constituent atomsŒ21 . Several [6] Joint Electronics Device Engineering Council (JEDEC).
groups in radiation research have focused on the issues of JESD89-1A: Test Method for Real-Time Soft Error Rate
pulsed-laser induced SEEs. The increased use of the pulsed Heavily used for SER testing for ground level applications, 2007
laser for SEE studies in recent years may be attributed to the [7] Evans A, Alexandrescu D, Ferlet-Cavrois V, et al. Techniques
confluence of several factors, including: the scaling of transis- for heavy ion microbeam analysis of FPGA SER sensitivity.
tors to the point where they are becoming highly sensitive to IEEE International Reliability Physics Symposium (IRPS), 2015:
SEEs, the availability of commercially manufactured picosec- SE.6.1
onds pulsed-lasers in the required wavelength range, the cost [8] Chen C H, Knag P, Zhang Z. Characterization of heavy-ion-
and limited time available at accelerators for testing, and the induced single-event effects in 65 nm bulk CMOS ASIC test
lack of spatial and temporal information obtained from broad- chips. IEEE Trans Nucl Sci, 2014, 61(5): 2694
[9] Evans A, Alexandrescu D, Ferlet-Cavrois V, et al. New tech-
beam accelerator testing.
niques for SET sensitivity and propagation measurement in flash-
A popular time-domain, laser-based SEE research is pre- based FPGAs. IEEE Trans Nucl Sci, 2014, 61(6): 3171
sented in Reference [22], where the authors developed a time- [10] Namba K, Ikeda T, Ito H. Construction of SEU tolerant flip–
domain, laser-based SEE test approach for nanoscale high- flops allowing enhanced scan delay fault testing. IEEE Trans
speed SerDes and phase lock loop (PLL) devices, which al- Very Large Scale Integration (VLSI) Systems, 2010, 18(9): 1265
lows the oscilloscope and laser to each run at its own char- [11] Yanagawa Y, Kobayashi D, Hirose K, et al. Experimental veri-
acteristic frequency. These approaches are applicable to other fication of scan-architecture-based evaluation technique of SET
high-speed circuits including analog, mixed-signal, and digital. and SEU soft-error rates at each flip–flop in logic VLSI systems.
Advantages of the time-domain approach include the ability IEEE Trans Nucl Sci, 2009, 56(4): 1958
to characterize the full range of SETs, even varying program- [12] Hofbauer M, Zimmermann H. Pulse shape measurements by
to-program requirements, and to gather a data set that al- on-chip sense amplifiers of single event transients propagating
lows significant flexibility in terms of post-processing of the through a 90 nm bulk CMOS inverter chain. IEEE Trans Nucl
data beyond error identification and characterization. A space- Sci, 2012, 59(6): 2778
[13] Chen C H, Knag P. Characterization of heavy-ion-induced single-
domain, laser-based SEE research is presented in Reference
event effects in 65 nm bulk CMOS ASIC test chips. IEEE Trans
[21], and is based on the advantages of the adjustability of the Nucl Sci, 2014, 61(5): 2694
laser focal panel and the penetrability through the silicon sub- [14] Agarwal A, Bhatia G, Chakraverty S. State model for scheduling
strate, and irradiation from the backside; the depth of sensitive built-in self-test and scrubbing in FPGA to maximize the system
volume in the longitudinal direction and the sensitive mapping availability in space applications. India International Conference
in the transverse direction can be determined using this method. on Power Electronics (IICPE), 2011: 1
These methods can provide essential physical-structure-level [15] Martin M, Summers J, Lyke J. AFRL plug-and-play space-
information for layout-level radiation hardness and the estab- craft avionics experiment (SAE). IEEE Aerospace Conference,
lishment of SEE sensitive volume. 2012: 1
[16] Asenek V, Underwood C, Velazco R, et al. SEU induced errors
observed in microprocessor systems. IEEE Trans Nucl Sci, 1998,
6. Conclusion 45(6): 2876
[17] Chipana R, Kastensmidt F L, Tonfat J, et al. SET susceptibility
In summary, the single-event effect evaluation of a nano-
estimation of clock tree networks from layout extraction. 13th
radiation-hardened integrated circuit is a hot topic in the Latin American Test Workshop (LATW), 2012: 1
field of radiation effects and reliability of electronic devices. [18] Venkatram H, Guerber J, Gande M, et al. Detection and correc-
Nanoscale technology circuits present functional complexity tion methods for single event effects in analog to digital convert-
and a diversity of single-event effects. Thus, further study of ers. IEEE Trans Circuits Syst I: Regular Papers, 2013, 60(12):
the radiation effects assessment methods is required, and en- 3163
hancement of existing SEE test systems to solidify and unify [19] Touloupis E, Flint J A, Chouliaras V A, et al. Study of the effects
the forms of verification is required in order to meet nano cir- of SEU-induced faults on a pipeline protected microprocessor.
cuits radiation-hardened evaluation requirements. IEEE Trans Computers, 2007, 56(12): 1585
[20] Zanchi A, Buchner S, Lotfi Y, et al. Correlation of pulsed-laser
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