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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC
With Incremental Converting Algorithm for
Energy Efficient Applications
Yan Song, Zhongming Xue, Yi Xie, Shiquan Fan, Student Member, IEEE, and Li Geng, Member, IEEE
Abstract—This paper proposes a fully differential 10-bit energy
efficient successive approximation register (SAR) analog-to-digital
converter (ADC) by using incremental converting method. The
voltage difference of the input between two successive samples is
acquired and resolved. A judge window is properly designed, and
several conversion steps of significant bits could be skipped when
the voltage difference is within the preset window. Thus, the power
consumptions of the digital-to-analog converter (DAC), logic cir-
cuit, and comparator are greatly saved. Moreover, the differential
structure also helps to suppress common mode noise and even har-
monic noise. The design is implemented with a standard 0.18-μm
CMOS technology. Test results show that the power consumption
of the ADC with the proposed algorithm is reduced by at least
42.8% comparing to the conventional structure. The measured
DNL and INL are within 0.29 LSB and 0.80 LSB, respectively. At
a 0.6-V supply and a 200-kS/s sampling rate, the ADC achieves an
ENOB of 9.34 and a figure-of-merit of 8.87 fJ/conv.-step.
Index Terms—Analog to digital converter, differential incremen-
tal converting, low power, low voltage, successive approximation.
I. I NTRODUCTION
I MPLANTABLE neural signal acquisition systems attract
more interests in modern society. Analyzing the action
potentials of neurons can help to find the relationship between
neural activities and movement behaviors of primates, and
understand the pathology of various nervous diseases [1], [2].
Usually, a biomedical signal acquisition system consists of sev-
eral channels. Each channel may have a band-pass filter, a low
noise amplifier and an analog-to-digital converter (ADC) [3],
[4]. ADCs in these systems usually need about 10-bit resolution
and hundreds kHz sampling rate. Power consumption is the
main consideration in these systems since most of them are
battery or wireless powered [5], [6]. It should achieve microwatt
power consumption or even lower to prolong the battery’s life
[7]–[9]. Therefore, energy efficient ADC design is very critical
in such applications.
Manuscript received September 24, 2015; revised December 13, 2015;
accepted January 1, 2016. This work was supported in part by the National
Natural Science Foundation of China under Grant 61271089 and the Key
Science and Technology Innovation Team of Shaanxi Province, China Grant
2013KCT-03. This paper was recommended by Associate Editor N. Maghari.
The authors are with the Department of Microelectronics, Xi’an Jiaotong
University, Xi’an 710049, China (e-mail: syfire@stu.xjtu.edu.cn; gengli@mail.
xjtu.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2016.2528080
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
Successive approximation register (SAR) ADC is a better
choice for neural signal acquisition systems compared with
other ADC architectures. Due to its digital-like structure with
seldom analog opamp, SAR ADC hardly has static current,
which makes it high power efficiency. Moreover, advanced
technology could bring benefits of low supply voltage and low
area for SAR ADC.
Power consumption of SAR ADC mainly comes from three
parts: capacitive digital-to-analog converter (DAC), dynamic
comparator and control logic. Since the power of DAC occupies
nearly one third of the total energy dissipated by the ADC,
some methods have been proposed to reduce the switching
energy of DAC, such as split-capacitor switching [10], energy-
saving method [11], monotonic switching [12] and Vcm-based
switching [13], which reduce the switching energy by 37%,
56%, 81%, and 87%, respectively. Usually, n conversion steps
are needed to resolve n-bit resolution for these designs. How-
ever, when the voltages of two successive samples are close,
several conversion results of the significant bits could be the
same. These conversion steps are not necessary and reduce the
conversion efficiency.
Some methods have been presented in previous works to
solve the redundant switching problem. In [14], bypass window
is proposed to avoid switching-back transition when the input
amplitude is small. It saves several bitcycles of the most-
significant-bits (MSBs) when the input resides in a small
window. The skipped steps are related to the input ampli-
tude, and the energy efficiency varies with the input. In [15],
voltage difference between two adjacent samples is digitalized
by input-tracking technique. It starts converting from middle
bits and reduces bitcycles for slowly varied inputs. In that
ADC, the varied input should be limited to the binary-weighted
voltage of the starting bit to avoid converting error. A delta-
modulated SAR ADC with single-ended structure is described
in [16], in which the input amplitude is judged after sampling
to determine the skipped bitcycles. Different bitcycles are saved
for different input range, which improves conversion efficiency.
For the LSB-first algorithm proposed in [17], the range of
input voltage from the least-significant-bit (LSB) to upper bits
is firstly searched. When the range is determined, it resolves
the input by using conventional successive approximation (SA)
logic. It achieves high conversion efficiency when the input is
close to dc level. However, more bitcycles are needed for one
sample than conventional SA logic when the input variation
rate increases.
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 1. Conventional conversion procedure of SAR ADC.
This work proposes an incremental converting algorithm,
which is realized in a fully differential SAR ADC to reduce
redundant conversion steps. The input variation between two
successive samples is stored by DAC during sampling period.
A judging procedure is adopted to distinguish the value of
the voltage difference. If it is smaller than the judge window,
several conversion steps of MSBs could be skipped, and thus
switching energy is saved. When the variation is larger than the
judge window, it turns back to convert from the MSB, avoiding
the conversion error. It keeps high conversion efficiency among
full input range for slowly varied inputs. Moreover, the dynamic
range of ADC is enlarged by using the differential structure, and
the even harmonic noise is suppressed.
The paper is organized as follows. Section II introduces
the incremental converting concept of the differential SAR
ADC, and the switching method of the DAC array is also
given. In Section III, power consumptions of the SAR ADC
are analyzed to show the advantage of the proposed algorithm.
Section IV presents the detailed circuit implementation of the
ADC. The measurement results are shown in Section V. Finally,
Section VI draws the conclusions.
II. I NCREMENTAL C ONVERTING A LGORITHM
OF D IFFERENTIAL SAR ADC
In conventional charge-redistribution SAR ADC, the input
voltage is sampled in the DAC and converted to digital codes
using binary searching algorithm. The DAC is switched from
the MSB to the LSB in sequence according to the output of
comparator. Fig. 1 shows a conventional switching procedure
of a 10-bit SAR ADC using top-plate sampling. VP and VN are
the differential inputs of the comparator. When two successive
 
samples of VPN and VPN are close, the first three conversion
steps, which resolving the first four bits, are the same. Thus,
switching energy from phase 9 to phase 7 is wasted. Since the
switching energy of the MSBs accounts for most of the total
power consumption of DAC, conventional switching procedure
is power inefficient.
The incremental converting SAR (ICSAR) ADC presented

here samples the voltage difference between VPN and VPN , input-tracking technique [15]. For the input-tracking ADC at
i.e., ΔVP + ΔVN , as shown in Fig. 1. When ΔVP + ΔVN is
smaller than a preset window, only some lower bits need to
be resolved. Bitcycles of several MSBs could be skipped. As
the result, the energy consumption is reduced. If the voltage
difference is larger than the window, the ADC converts from
the MSB, which is the same as that of conventional SA logic.
Fig. 2. Conversion processes of proposed incremental converting SAR ADC
with (a) Vinc < Vwin ; (b) Vinc > Vwin .
The proposed algorithm achieves high energy efficiency when
the variation rate of input signal is low. Comparing to [14] and
[15], the designed ADC possesses low power consumption for
full-scale inputs and avoids converting errors when the variation
of input is large.
A. Algorithm Description
Fig. 2 depicts the conversion process of the proposed in-
cremental converting procedure for a fully differential SA
structure. As an example, a judge window (Vwin ) of 64 LSBs
is adopted here to illustrate the principle. Vwin is equal to the
binary-weighted voltage of phase 7, i.e., VDD /8. There are three
phases, including “Sampling,” “Judging,” and “Converting.”
Sampling: In the sampling phase, the difference voltage

between VPN and VPN is sampled by the DAC array. It can be
expressed as Vinc = ΔVP + ΔVN , where ΔVP and ΔVN are
the varied voltages of VIP and VIN , respectively. When Vinc is
positive, the sign bit of Flag is set to 1, which means VPN is

larger than VPN . The quantization code of VPN is equal to the
sum of conversion result of Vinc and the code of VPN . On the

contrary, if Vinc is negative, Flag is set to 0, which means VPN

is smaller than VPN . To achieve the quantization code of VPN ,
conversion code of Vinc should be subtracted from VPN .
The sampling procedure in this work is similar to that of the
the same situation described above, it converts the input from
phase 7 after sampling. The conversion result is correct if Vinc is
smaller than the binary-weighted voltage of phase 7. However,
if Vinc is larger than that, the voltage increment could not be
resolved through the switching steps of lower bits. To avoid
this problem, the variation rate of input must be limited, as
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SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM
Fig. 3. Conversion flowchart of incremental converting algorithm.
described in [15]. In this paper, a judging procedure is added
after sampling period according to the value of Vinc , which
determines the following conversion process.
Judging: In the judging phase, i.e., phase 7 for the situation
described above, the DAC is switched to add or subtract Vwin
from Vinc , which is determined by the polarity of Vinc . For
example, if Vinc is positive, the differential output of DAC is
set to Vinc − Vwin . The comparator is used to make a decision
to determine the relationship between Vinc and Vwin . If the
comparison result is “0,” it means Vinc < Vwin and no capacitor
switching is needed from phase 9 to phase 8. Then, the DAC
goes straightly to phase 6 performing B5 conversion, as shown
in Fig. 2(a). The energy consumed by the capacitor switching,
control logic, and comparator from phase 9 to phase 8 could be
saved. On the other hand, if Vinc > Vwin , upper bit conversions
are needed to encode the voltage increment. In this case, the
DAC turns back to phase 9 to convert from the MSB, as shown
in Fig. 2(b).
When Vinc is negative, the judging procedure operates in the
opposite direction. The output of DAC is set to Vinc + Vwin
after switching phase 7. Then, the comparator makes a decision
to detect the value of Vinc . When the comparison result is “1,”
it means Vinc > −Vwin . Since Vinc is negative, this leads to the
result that |Vinc | < Vwin and conversion steps from phase 9 to
phase 8 can be skipped. Otherwise, the comparison result of “0”
indicates |Vinc | > Vwin , and the ADC goes back to phase 9 to
convert from the MSB.
For the bypass window algorithm [14], the input voltage is
judged by using two comparators. Conversion steps of signifi-
cant bits are skipped if the input amplitude is within the bypass
window. Energy saving is limited by the input amplitude. For
the proposed algorithm, the voltage difference between two
adjacent samples, which usually maintains a small value for
slowly varied inputs, is converted. Thus, the ADC could skip
bitcycles even though the amplitude of input is large. The ADC
could achieve high energy efficiency among full input range.
Converting: In this phase, ADC starts its normal conversion
process, converting from phase 9 or phase 6, which is deter-
mined by the judging result. It behaves as conventional binary
searching process until the LSB is determined. The converting
results are stored in data registers. Then the data will be added
or subtracted from the previous output code, according to Flag,
to achieve the coding result of current sample.
The flowchart of this algorithm is shown in Fig. 3.
3
Fig. 4. Coding method of incremental voltage Vinc .
B. Coding Method
For differential structure, the comparison result (Comp) of
the comparator represents the quantization value of Vinc with
monotonic coding method, as shown in Fig. 4. The first bit of
Comp is the sign bit, which is equal to Flag in the algorithm.
Compi−1∼0 represents the absolute value of Vinc , and can be
directly added to the previous output code when Vinc > 0.
However, when Vinc < 0, Compi−1∼0 does not represent |Vinc |.
Directly subtracting it from the previous code will make error. It
should be modified for arithmetic calculation convenience. An
example of 3-bit coding for the proposed algorithm is given
in Fig. 4. Comp2 is the sign bit stored in Flag. An XNOR
gate is designed here to generate the proper code of |Vinc |. For
example, if Vinc is 4 LSBs lower than zero, the comparison
result is Comp2∼0 = 000. To get the modified output code,
XNOR operation is done with each bit of Comp1∼0 according
to Flag. Then the output code “11” is stored in B1∼0 . Normally,
this operation can be expressed as
Bi = Flag  Compi , i = 0 − 8. (1)
C. DAC Switching Procedure
The DAC structure adopted here is similar to that used in the
merged-capacitor switching method [18]. There is no additional
capacitor or switch. The incremental converting algorithm is re-
alized by properly designed control logic. Fig. 5 gives an exam-
ple of the capacitor switching method with a judge window size
of 64 LSBs. There are four steps to complete one conversion cy-
cle. A holding phase is added to realize incremental sampling.
Sampling: Before each sampling phase, the previous con-
version results of Comp9∼0 are left on the bottom plates of
capacitors of DAC. To sample the incremental voltage of the
input signal, the output codes of D9∼0 are loaded to the
switches of DAC capacitors through MUX by the control logic.
The bottom plate of Ci (i = 9 − 1) in DACp is connected to
VDD or GND, when Di is “1” or “0,” respectively. Meanwhile,
the bottom plate of Ci (i = 9 − 1) in DACn is connected to
GND or VDD when Di is “1” or “0.” Here, D0 is loaded to the
tail capacitor, C0 . Since C0 is equal to C1 , if the bottom plate
of C0 is switched between VDD and GND, the output voltage of
DAC will have a gain error. Thus, in this algorithm, the bottom
plate of C0 in DACp is connected to VCM or GND when D0
is “1” or “0,” respectively. The bottom plate of C0 in DACn is
connected to GND or VCM when D0 is “1” or “0,” respectively.
Then, the top plates of the capacitors in DACp and DACn are
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 5. Switching method of the DAC with judge window of 64 LSBs.

connected to the differential input voltage. The input charge is GND and VDD , respectively. The differential output voltage of
stored in the capacitors of DAC. DAC is decreased by 64 LSBs, which is Vinc − Vwin . Vinc and
Holding: After sampling, the sampling switches turn off Vwin are compared by the comparator and then a decision is
first to disconnect the input signal from the DAC array. Then, made. If the comparison result is “0,” it means Vinc is within
all the bottom plates of the capacitors are switched to VCM . the judge window. The skipping logic is triggered, and there
Since the total charge on the top plates of the capacitors is is no need for C9 ∼ C7 switching since the conversion result
constant, the differential outputs of the DAC array can be can be predicted to be zero. The following step begins from C6
expressed as switching to determine B5 . However, if the comparison result

9 is “1” and Vinc > Vwin , the control logic goes back to phase 9
Di · Ci · VDD + D0 · C0 · 12 VDD to resolve the MSB. If Vinc < 0, the switching procedure goes
VP = VIP − i=1
 + VCM to the opposite side. The corresponding procedure is illustrated
Ci in Fig. 5. Optimum widow size could be set by the analysis of

= VIP − VIP + VCM (2) energy consumption.

9 Converting: After the judging phase, the DAC executes the
Di · Ci · VDD + D0 · C0 · 12 VDD conventional binary searching process from phase 9 or phase 6
VN = VIN − i=1
 + VCM according to the judging result until the LSB is resolved.
Ci

= VIN − VIN + VCM (3)
III. A LGORITHM A NALYSIS

where VIP and VIN are the current sampled voltages, and VIP A. Bitcycle Saving for Different Window Size

and VIN are the previous quantized voltages. The differential
To prove that the proposed incremental converting algorithm
output of the DAC is the increased input voltage, which is
reduces redundant switching steps efficiently when the input
  variation is small, full-scale sine waves with different frequen-
Vinc = (VIP − VIN ) − (VIP − VIN ). (4)
cies were input to the ADC at a sampling rate of 200 kS/s. The
 
Note that in (2) and (3), |VIP − VIP | and |VIN − VIN | should average bitcycles at each input frequency could be calculated
not be larger than 1/2VDD . Otherwise, the voltages on top from the simulation results. Fig. 6 shows the simulated curves
plates of the capacitors of DAC will exceed the supply rail. of bitcycles scaling down with the input frequency. At low
If the full-scale (VDD ) signal is input to the ADC, the input input frequency, the input variation is smaller than the judge
frequency should be limited to one quarter of the sampling window for most samples. Thus, the average bitcycles for each
rate. Actually, in real applications, the sampling rate of ADC conversion are less than those of conventional SA logic.
is usually set to several times of the input frequency for good If more bitcycles are expected to be skipped during the con-
conversion results. In this way, this problem could be avoided. version, the judge window should be narrowed down. However,
Judging: Suppose Vinc > 0, during the judging phase, the the input variation needs to be small enough to trigger the
bottom plates of C7 in DACp and DACn are connected to skipping process. As shown in Fig. 6, although five bitcycles are
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SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM
Fig. 6. Bitcycles per sample for full-scale sinusoid inputs with different
frequencies. Different sizes of judge window were simulated comparing to the
conventional SA logic.
saved with the window size of 8 LSBs comparing to conven-
tional SAR ADC, the input frequency is limited to several
hundred Hz to achieve small input variation. At high input fre-
quency, less sampled voltage would fall into the judge window,
and the average bitcycles increase. For biomedical applications,
the frequency of the signal is around 1 kHz [20]. According to
the theoretical analysis and simulation results, the window size
of 16 LSBs is more suitable.
B. Power Scaling for Different Window Size
In SAR ADC, since the capacitor array is binary-weighted,
the energy consumed by each bitcycle during a conversion is
not the same. Thus, to fairly compare the energy saving with
different sizes of judge window, energy per bitcycle should be
calculated. Three building blocks contribute the main power
consumption of the SAR ADC, including DAC capacitors,
control logic, and comparator. We assume that the power of
control logic, Edig , and the power of comparator, Ecomp , for
each bitcycle do not change. The power of DAC switching
varies with the switching sequence in each step. Edac represents
the power consumption of unit capacitor switching between
GND and VDD .
For a conventional n-bit SAR ADC, the power consumption
of the comparator and the control logic are n · Ecomp and
n · Edig , respectively. Based on the conventional switching
method of [18], the output code for each step is assumed to
be equiprobable, the switching energy dissipated by the DAC is
presented as
 n−1  is p, the total average power consumption of ADC can be
2 + 2−n 1 derived as
EDAC,conv = − · Edac . (5)
3 2
Assuming that Ck is switched for judging in the SAR ADC
with the proposed algorithm, the size of the judge window
will be 2k−1 LSBs. According to the analysis above, for the
situation that Vinc is within the window, the switching steps of
Cn−1 ∼ Ck are skipped. In this circumstance, the power con-
sumption of ADC consists of two parts: the energy consumed
by the judging phase and the normal switching energy con-
sumed from phase k − 1 to phase 1. The skipped capacitors,
which maintain connecting to VCM , still consume energy during
5
Fig. 7. Normalized power of Eoutwin , Einwin , and p at different window size.
converting [21]. As a result, the power of the comparator,
control logic, and DAC switching can be derived as
ECOMP,inwin = (1 + k) · Ecomp (6)
EDIG,inwin = (1 + k) · Edig (7)
 
1 2 2·k−n
− 2 2−2·k
EDAC,inwin = 2k−1 − − · Edac . (8)
2 3
On the other hand, if Vinc is out of the window, the power
consumption of ADC comprises the dissipations of judging
phase and the conversion steps from phase 9 to phase 1. Then,
the power consumption of each block can be derived as
ECOMP,outwin = (1 + n) · Ecomp (9)
EDIG,outwin = (1 + n) · Edig (10)

9
EDAC,outwin = (2k−2 − 22·k−2−n ) · Edac + Edac,i (11)
i=1
where Edac,i is the DAC switching power of the i-th phase. The
first part of (11) is the judging energy consumed by Ck , and the
second part is the switching energy of DAC from phase 9 to
phase 1.
The total average power consumption of ADC when Vinc
is inside or outside the judge window, Einwin or Eoutwin ,
is the sum of (6)–(8), or the sum of (9)–(11), respectively.
Simulation results of a 10-bit SAR ADC are obtained, and then
the normalized power of Ecomp , Edig , and Edac are calculated.
As a consequence, Einwin and Eoutwin , changing with the size
of the judge window, are achieved, as shown in Fig. 7.
Suppose the probability of Vinc falling into the judge window
Eavg = p · Einwin + (1 − p) · Eoutwin . (12)
Actually, p is closely related to the input signals. For real
applications, p is calculated according to the features of input
signals and a proper window size could be determined to obtain
the lowest switching power consumption. Normally, biomedical
signals have a bandwidth ranging from 1 Hz to 10 kHz [20].
Here, we use a full-scale sine wave with frequency of 1 kHz,
which is the middle frequency among the biomedical signal
bandwidth, as an input to the ADC for power estimation.
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 8. Normalized ADC power with different window size at 200 kS/s and
1 kHz full-scale sinusoid input.
Fig. 9. Simulated ADC power with a full-scale sine wave input at different
input frequency for different SAR ADC structures.
Vinc of each sample is calculated by using MATLAB at a sam-
pling rate of 200 kS/s. Then, by comparing each Vinc with Vwin ,
the probability of |Vinc | < Vwin with different window sizes are
achieved. The calculated probability p is shown in Fig. 7.
By using the estimated value of p, the total average power
consumption of ADC with different window size is calculated.
The results are shown in Fig. 8. A large window leads to a wide
range of Vinc falling into it, but fewer conversion steps will
be skipped. For example, with the window size of 128 LSBs,
only the conversion step of the MSB is skipped. The power
reduction is 25.67% comparing to that of the ADC without
judge window. On the contrary, a small window makes the DAC
skipping several conversion steps when |Vinc | < Vwin , but the
probability of this situation is small. According to Fig. 8, with
the window size of 16 LSBs, the power consumption of ADC
has a maximum reduction of 65.28%. Thus, a judge window of
16 LSBs is selected in this design.
C. Power Scaling of Different Input Frequency
Once the judge window is settled, the energy dissipation of
the ADC with different input variation rate could be estimated.
Full-scale sinusoids with different frequencies were input to the
ADC. If the sampling rate is 200 kS/s and the judge window is
16 LSBs, the normalized power of ADC is shown in Fig. 9.
Small difference between two successive samples, i.e., small
Vinc , is obtained if the frequency of input signal is low. Thus,
Fig. 10. Architecture of the proposed fully differential SAR ADC with incre-
mental converting algorithm.
the sampled values have large probability falling into the judge
window. When the input frequency is lower than 1 kHz, all
samples are within the window. The ADC has a power reduction
of 70% comparing to that no judge window is used. If the
input frequency increases to 10 kHz, no Vinc falls into the judge
window and full conversion steps are processed for all samples.
Because of the extra judging step, the total power consumption
of the DAC will be larger than that of conventional structure.
Simulated power consumption of the conventional SAR
ADC [13] and bypass window SAR ADC [14] with different
input frequency are also presented in Fig. 9. Comparing to
conventional SA structure, bypass window algorithm has a
constant reduction of power consumption. Since it is designed
to save power for small amplitude inputs, this algorithm does
not appear power efficient here with full-scale sinusoids. Power
reduction has no relation with the input variation rate. The pro-
posed incremental converting algorithm presents lower power
than conventional SA logic when the input frequency is lower
than 5 kHz. It is also much lower than the bypass window
algorithm at low input frequency. When the input frequency
decreases to 1 kHz, the ADC of this work has a maximum
power reduction since each sample of the voltage difference
is within the judge window. SAR ADC with the proposed
algorithm is very suitable for biomedical applications because
the biomedical signals express low activity in most of the
period. For other applications, size of the judge window could
be adjusted to a proper value for optimal power reduction.
IV. C IRCUIT I MPLEMENTATION
Fig. 10 shows the top-level design of the proposed SAR
ADC. The main structure is fully differential to better suppress
common mode noise, which commonly exists in biomedical
signals. It also helps to inhibit even harmonic noise, thus
improving the dynamic performance of ADC. The key building
blocks are the DAC array, comparator, control logic, 10-bit
adder, and memory register. The 10-bit adder is realized by
combinational logic gates and the memory register is formed
by a series of DFFs.
A. Capacitive DAC
The top plate sampling method is used in this work and a
9-bit DAC meets the requirement of 10-bit conversion. Thus,
there are 10 binary-weighted capacitors in both p-type and
n-type DAC arrays. C5p and C5n are switched in the judging
phase to realize the judge window of 16-LSB.
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SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM
Fig. 11. (a) Schematic and (b) timing diagram of the improved energy efficient
comparator.
The capacitive DAC is implemented by using metal-
insulator-metal (MIM) capacitors. The unit capacitor is about
28 fF. As a consequence, the total capacitance is 14 pF in each
side of the DAC array. The mismatch effect can be minimized to
meet 10-bit resolution requirement by properly designed layout
and routed capacitor array.
B. Comparator With Improved Energy Efficiency
Dynamic latch comparator is commonly used for low-voltage
and low-power applications. It operates like a digital circuit,
thus no bias current is needed. The two-stage dynamic com-
parator [22] is widely used in many low-power SAR ADCs.
It has no static current, thus achieves low power. One stage
latch comparator [14] is also commonly used because of its
simple structure. However, this structure is bothered by the
static current after finishing comparison, which will reduce the
power efficiency. In this work, self-shutdown logic is designed
for the one-stage comparator to turn off it after comparison is
done. Fig. 11(a) shows the schematic of the improved com-
parator. The self-shutdown logic could be found in right part
of the figure.
When CLK is low, trig keeps low to reset the comparator.
VOP and VON are reset to VDD . When CLK changes to high,
trig goes to high voltage making the comparator regenerate.
For the conventional structure, when comparison is completed,
node A or B keeps high voltage and the other one turns to low.
Suppose VOP < VON , then M3 keeps open and there is a static
current flowing through M3 , M1 , and M7 until external CLK
turns M7 off. Thus, the energy is wasted. In this work, an XOR
gate is added to detect if the comparison has finished. Once the
comparison has done, the XOR gate generates a high voltage to
turn on M9 . Then, node D goes down to GND and pulls trig
to low. Thus, the comparator turns off automatically without
waiting for CLK. No current will flow through the comparator
before the next regeneration phase comes. Meanwhile, VALID
is generated as an asynchronous timing clock to drive the
control logic and trigger the next comparison phase. The timing
diagram of the presented comparator is shown in Fig. 11(b).
7
Fig. 12. Schematic of the control logic for conversion from bit-6 to bit-4.
Simulation result shows that the total power consumption of
the comparator is reduced by one fourth comparing to the
conventional structure. In fact, energy consumption is related
to the asynchronous time delay. Much power could be saved
when the time delay is large.
By properly designing the size of transistors, the comparator
has a mean input offset voltage of 0.08 mV. The standard
deviation of the input offset voltage is 3.2 mV based on Monte
Carlo simulations. Take 3σ into consideration, the total input
offset voltage is about 9.7 mV, decreasing the SNR by 0.07 dB.
It has little negative effect for the precision of a 10-bit SAR
ADC. In addition, input offset voltage does not bring much
influence on the output codes. The linearity of the ADC will
not be affected. Thus, no calibrating or offset-cancelling circuit
is needed.
C. Incremental Converting Control Logic
The control logic consists of two series connected DFF
arrays, combining with logic gates. Fig. 12 shows the schematic
of the control logic for the conversions from bit-6 to bit-4.
All the DFF registers are reset during sampling phase when
SAMPLE is high. Meanwhile, the previous output codes D9∼0
are selected by the MUX to control the switches for incre-
mental sampling. CSWi and RSWi are combined to decide
the connection of the bottom plate of Ci between different
reference voltages. The Flag signal is generated according to
the first comparison result after sampling. It is stored in a
register until the end of the conversion cycle. Then, a Judge
signal is generated by the phase generator to trigger the judge
procedure. If |Vinc | < Vwin , a Skip signal is generated to bypass
the conversion steps from bit-9 to bit-5. Then the DAC begins
converting from bit-4 in the following steps.
The proposed SAR ADC is driven by an asynchronous
timing sequence to avoid external high frequency synchronous
clock [23]. Once-triggered DFF [14] is adopted to generate
the asynchronous time phase of Phi to save energy. When
SAMPLE triggers a conversion cycle, the following steps are
managed by the asynchronous controller. The self-timed logic
is similar to a positive feedback loop, and it is sensitive to the
transmission delay. A time-delay block for VALID is imple-
mented before the controller to ensure that COMP is properly
settled before VALID is arriving. Otherwise, the errors might
appear during the switching operation of the DAC.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 13. Die micrograph.

Fig. 15. Measured output spectrum at 200 kS/s with 10 kHz input.

Fig. 14. Measured DNL and INL at 200 kS/s. Fig. 16. SFDR and SNDR versus input frequency at 200 kS/s.

V. M EASUREMENT R ESULTS
The ADC is implemented with a 1P6M 0.18- μm standard
CMOS process. The die micrograph of the SAR ADC is shown
in Fig. 13. The active area of the ADC is 0.154 mm2 . The
supply voltage is 0.6 V. The maximum sampling frequency is
200 kS/s. The reference voltage of the DAC is set to VDD to
realize rail-to-rail sampling. Because of the differential struc-
ture adopted in this work, the input range is enlarged to 1.2-Vpp
comparing to the single-ended structure of 0.6-Vpp . It brings
benefits to the designing and signal processing of front-end am-
plifiers. However, due to the gain error of the capacitive DAC,
the real input range of the ADC is limited to 1.17-Vpp when
the input frequency is lower than 30 kHz. As describes above,
when the input frequency is larger than fs /4, where fs is the
sampling rate, the ADC fails to get the right result. Thus, to test
the performance of this ADC, the input amplitude is attenuated
when the input frequency is larger than fs /4. However, for real
applications, the sampling frequency is always several times
larger than the input frequency. Thus, converting error could
be avoided.
Fig. 14 shows the measured DNL and INL of the presented
ADC. The sampling rate is 200 kS/s. The peak DNL and INL
are +0.29/−0.26 LSB and +0.36/−0.80 LSB, respectively.
Fast Fourier transform (FFT) has been performed with a con-
stant sampling rate of 200 kS/s. Since most neural signals have
a bandwidth limit of 10 kHz, the frequency of the input signal is
set to 10 kHz. Fig. 15 shows the 32 768-point FFT spectrum of
the ADC output. The measured spurious-free dynamic range
(SFDR) and signal-to-noise and distortion ratio (SNDR) are
Fig. 17. ADC power versus input frequency at 200 kS/s with 0.6-V supply.
72.27 dB and 57.86 dB, respectively. The even harmonic noise
is inhibited to −73.23 dB due to the differential structure.
It is much better than that of the single-ended ADCs [24],
[25], which have max even harmonic noise of −64.2 dB and
−58.9 dB, respectively.
Fig. 16 plots the measured SFDR and SNDR versus the
frequency of input signal with sampling rate of 200 kS/s. The
SFDR and SNDR change little when the input frequency is be-
low 10 kHz. At 140 Hz input frequency, the SAR ADC achieves
a best SNDR of 58.00 dB and the resultant ENOB is 9.34.
Fig. 17 plots the relationship between total power consump-
tion of the SAR ADC and the frequency of sinusoid input at
a sampling rate of 200 kS/s. With the biomedical signal band-
width frequency of 10 kHz, the power consumption of ADC is
2.01 μW. The DAC switching, control logic, and comparator
account for 56%, 30%, and 14%, respectively. In this case, no
sampled voltage falls into the judge window. When the input
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
SONG et al.: A 0.6-V 10-BIT 200-kS/s FULLY DIFFERENTIAL SAR ADC WITH INCREMENTAL CONVERTING ALGORITHM
Fig. 18. ADC power versus sampling frequency at 0.6-V supply with dc input.
TABLE I
S PECIFICATION S UMMARY
frequency decreases to 100 Hz, all the sampled voltages fall into
the judge window, and the power consumption is only 1.15 μW.
The DAC switching, control logic, and comparator account for
48%, 35%, and 17%, respectively. The total power of ADC is
reduced by 42.8% comparing to that with 10 kHz input. When
the input frequency reaches to the Nyquist frequency of 90 kHz,
the power consumption of ADC increases to 2.4 μW.
Fig. 18 shows the power consumption of the ADC versus
sampling rate with a dc input at 0.6-V supply. When sampling
frequency is 100 Hz, the core ADC only consumes about
6.8 nW. Thus, for low frequency input with a long duration
time, the sampling rate can be lowered to further save the power
dissipation of ADC efficiently by using the proposed technique.
Table I summarizes the performance of the proposed SAR
ADC. The figure-of-merit (FoM) is used to compare the perfor-
mance of this work with other state-of-the-art SAR ADCs. The
FoM is defined as
Power
FoM =
2ENOB × fs
where Power is the power consumption of the ADC.
Table II compares the proposed SAR ADC with prior art
of low power SAR ADCs [16], [17], [26], [27]. This ADC
achieves a high ENOB of 9.3 bits at 0.6 V supply voltage. The
power consumption of the ADC varies from 1.15 to 2.01 μW at
200 kS/s, depending on the variation rate of the input signal. It
maintains a low FoM ranging from 8.87 to 15.51 fJ/conv.-step,
when the input is within the biomedical signal band.
9
TABLE II
P ERFORMANCE C OMPARISON W ITH O THER R ELATED W ORKS
VI. C ONCLUSION
This work has presented a fully differential SAR ADC with
incremental converting procedure, which is aimed at reducing
the power consumption of DAC switching, dynamic comparator
and control logic. Bitcycle savings and power reduction of
the ADC with the proposed algorithm are discussed in detail.
A proper size of judge window is selected according to the
theoretical analysis. The power consumption of this ADC has
a maximum reduction of 43%. The energy efficient comparator
with improved self-shutdown logic and incremental converting
control logic are designed. The fully differential structure can
suppress common mode noise which is serious for biomedical
signals, thus improving the dynamic performance. The pro-
posed method can also be applied to acquire other signals with
low magnitude or low frequency variation.
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Yan Song received the B.Sc. degree in micro-
electronics from Xi’an Jiaotong University, Xi’an,
China, in 2011. He is currently working toward the
Ph.D. degree in the Department of Microelectronics,
Xi’an Jiaotong University.
His research interests include the low-voltage and
low-power ADCs and other mixed-signal circuits for
implantable biomedical applications.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Zhongming Xue received the B.Sc. degree in micro-
electronics from Xi’an Jiaotong University, Xi’an,
China, in 2010. He is currently working toward the
Ph.D. degree in the Department of Microelectronics,
Xi’an Jiaotong University.
His research interests include wireless power
transmission systems for biomedical implants and
switching capacitor convertor.
Yi Xie received the B.Sc. degree in microelectron-
ics from Xi’an Jiaotong University, Xi’an, China,
in 2011. He is currently working toward the M.S.
degree in the Department of Microelectronics, Xi’an
Jiaotong University.
His research interests include low-voltage and
low-power SAR ADCs with digital calibration.
Shiquan Fan (S’13) received the B.Sc. degree,
the M.Sc. degree and the Ph.D. degree in micro-
electronics from Xi’an Jiaotong University, Xi’an,
China, in 2003, 2009, and 2014, respectively, where
he is currently an assistant professor in the Depart-
ment of Microelectronics.
From Spring 2003 to Winter 2006, he was work-
ing as an R&D Engineer for power management
product design and development. His research in-
terests include analog and mixed-signal integrated
circuit design and power management circuit and
system design.
Dr. Fan was the recipient of the Science and Technology Improvement
Award, by the Shaanxi municipal government in 2015.
Li Geng (M’06) received the B.Sc. degree in physics
and M.Sc. and Ph.D. degrees in electrical engineer-
ing from Xi’an University of Technology, Xi’an,
China, in 1990, 1998, and 2001, respectively.
From November 1999 to June 2000, she was
a Visiting Scholar with the Department of Electri-
cal Engineering, Ilmenau University of Technology,
Germany. From August 2007 to August 2008, she
was a Visiting Professor with the Department of
Electrical Engineering, Stanford University, CA,
USA. She is currently a Professor in the Department
of Microelectronics, Xi’an Jiaotong University, Xi’an, China. She also serves as
the director of the Department of Microelectronics, Xi’an Jiaotong University.
Her current research interests include power management integrated circuits,
low-voltage low-power analog and mixed-signal integrated circuits, RF inte-
grated circuit, and bio-implant systems.
Dr. Geng was a Technical Program Committee Member of ASSC from 2010
to 2015. She was the recipient of the Science and Technology Improvement
Award, by Ministry of National Mechanical Industry, China, in 1999, and the
recipient of the Science and Technology Improvement Award, by the Shaanxi
municipal government in 2000, 2001, 2010, and 2015, respectively.