EXPERIMENT NO – 04

DATE:
AIM:
To implement DTL as 2 input NAND gate using NPN BJT having β=20, Vcc=5V, R1=2k,
R2=20k, R3=4k and Vbb=0V.
i) Verify its functionality of DTL NAND gate and
ii) Calculate the propagation delay and frequency of operation.
iii) Plot VTC plot and calculate the noise margin.
iv) Calculate the theoretical and practical fan-out and compare them.
THEORY:
Diode-Transistor Logic, or DTL, refers to the technology for designing and fabricating digital
circuits wherein logic gates employ both diodes and transistors. DTL offers better noise margins
and greater fan-outs than RTL, but suffers from low speed, especially in comparison to TTL.
In a DTL circuit, the collector output of the driving transistor is separated from the base resistor
of the driven transistor by several diodes. Circuit analysis would easily show that in such an
arrangement, the differences between Vil and Vol, and between Voh and Vih, are much larger than
those exhibited by RTL gates, wherein the collector of the driving transistor is directly connected
to the base resistor of the driven transistor. This is why DTL gates are known to have better
noise margins than RTL gates.

One problem that DTL doesn't solve is its low speed, especially when the transistor is being
turned off. Turning off a saturated transistor in a DTL gate requires it to first pass through the
active region before going into cut-off. Cut-off, however, will not be reached until the stored
charge in its base has been removed. The dissipation of the base charge takes time if there is
no available path from the base to ground. This is why some DTL circuits have a base resistor
that's tied to ground, but even this requires some trade-offs. Another problem with turning off
the DTL output transistor is the fact that the effective capacitance of the output needs to charge
up through Rc before the output voltage rises to the final logic '1' level, which also consumes a
relatively large amount of time.

CIRCUIT DIAGRAM:
CODE:

1) VERIFICATION OF DTL NAND GATE

*dtl
.model trans npn bf=20
.model diode D Vj=0.7

Da 3 1 diode
Db 3 2 diode
D1 3 4 diode
D2 4 5 diode
q 6 5 0 trans
r2 8 5 20k
r1 7 3 2k
rc 7 6 4k
vcc 7 0 5
vbb 0 8 0
va 1 0 pulse(0 5 1n 1n 1n 500n 1000n)
vb 2 0 pulse(0 5 1n 1n 1n 250n 500n)

*analysis

.tran 0.1n 1500n

.control
run

plot v(1)
plot v(2)
plot v(6)

.endc
.end

2) TRANSIENT ANALYSIS:

*Transient analysis

.model trans npn bf=20

.model diode D Vj=0.7

Da 3 1 diode
Db 3 2 diode
D1 3 4 diode
D2 4 5 diode
q 6 5 0 trans
r2 8 5 20k
r1 7 3 2k
rc 7 6 4k
vcc 7 0 5
vbb 0 8 0
va 1 0 pulse(0 5 1n 1n 1n 500n 1000n)
vb 2 0 pulse(0 5 1n 1n 1n 250n 500n)

*analysis

.tran 0.1n 1500n

.control
run

plot v(2) v(6)

.endc
.end

3) VTC plot

*dtl
.model trans npn bf=20
.model diode D Vj=0.7

Da 3 1 diode
Db 3 1 diode
D1 3 4 diode
D2 4 5 diode
q 6 5 0 trans
r2 8 5 20k
r1 7 3 2k
rc 7 6 4k
vcc 7 0 5
vbb 0 8 0
vin 1 0 dc 5

*analysis

.dc vin 0 5 0.01

.control
run

plot v(1) v(6)

.endc
.end
4) FAN OUT:
*dtl x15 6 out15 7 0 load
.model trans npn bf=20 x16 6 out16 7 0 load
.model diode D Vj=0.7 x17 6 out17 7 0 load
Da 3 1 diode .control
Db 3 1 diode run
D1 3 4 diode plot v(1) v(6)
D2 4 5 diode
q 6 5 0 trans .endc
r2 8 5 20k .end
r1 7 3 2k
rc 7 6 4k
vcc 7 0 5
vbb 0 8 0
vin 1 0 dc 5

*analysis

*SubCircuit
.subckt load a1 a2 a3 0
Da b1 a1 diode
Db b1 a1 diode
D1 b1 b2 diode
D2 b2 b3 diode
q a2 b3 0 trans
r2 b3 0 20k
r1 a3 b1 2k
rc a3 a2 4k

.ends

.dc vin 0 5 0.01

x1 6 out1 7 0 load
x2 6 out2 7 0 load
x3 6 out3 7 0 load
x4 6 out4 7 0 load
x5 6 out5 7 0 load
x6 6 out6 7 0 load
x7 6 out7 7 0 load
x8 6 out8 7 0 load
x9 6 out9 7 0 load
x10 6 out10 7 0 load
x11 6 out11 7 0 load
x12 6 out12 7 0 load
x13 6 out13 7 0 load
x14 6 out14 7 0 load
1) Verification of NAND gate:
U17EC077

2) Propagation Delay:

U17EC077
3) Voltage Transfer Characteristics: U17EC077

4)Fan Out:
U17EC077
RESULTS:

CONCLUSION:
Thus, we have successfully verified the functionality of a DTL NAND (using NPN BJT) by
performing transient analysis of the circuit. We have also plotted the voltage-transfer
characteristics (VTC) of the circuit and calculated its noise margin and maximum fan-out
values.