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CHAPTER 4

FLC BASED PWM CONTROL SCHEMES FOR FACTS DEVICES


IN 13 BUS WECS

4.1 INTRODUCTION

The earlier chapters reveal that FACTS devices and controllers are
not efficient enough in solving problems inherent in WECS. This may be due
to drawbacks in control algorithms i.e. they are not able to cope up with
dynamic conditions arising during disturbance period. Hence it is decided to
employ powerful algorithm like FLC based PWM algorithm for FACTS
controllers.

In this chapter, FLC based PWM control for various FACTS


controllers is implemented and their performance is evaluated when subjected
to disturbance. The performance results are compared and the best among
them is adapted as the FACTS controller.

4.1.1 Implementation of FLC Based PWM Controller for FACTS


Devices

4.1.1.1 Fuzzy logic control

Perturbation and observation (P and O) method is one of the most


efficient methods among all the MPPT strategies. In general, P and O
algorithm uses a fixed step size that is determined by the accuracy and
tracking speed requirements. However, if the step size is increased for
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tracking speed-up, the accuracy is decreased. Also P and O fails to track the
power under fast varying atmospheric conditions resulting in a comparatively
low efficiency. These drawbacks of traditional P and O algorithm can be
eliminated by varying the step size under various operating conditions. It will
effectively reduce the power losses in the system and operate the WES system
close to MPP. In this research, FLC based maximum power tracking method
is proposed and is dedicated to find a simple, effective way to improve
tracking accuracy and to overcome the drawbacks in traditional methods.
Fuzzification includes the design of input and output membership functions.
These functions are designed based on the prior knowledge. The two input and
one output membership functions are illustrated in Fig.4.1, in which the firing
angle of the converter is automatically varied according to operating point of a
WECS.

Figure 4.1 Fuzzified input and output functions


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Table 4.1 Rules for the Fuzzy Algorithm

CE\E NB NS ZE PS PB
NB NB NB NS NS ZE
NS NB NS NS ZE PS
ZE NS NS ZE PS PS
PS NS ZE PS PS PB
PB ZE PS PS PB PB

The rule base defines the relationship between input and output
membership functions. The control rules are evaluated by the inference
mechanisms. Table 4.1 shows the rule base of FLC. The linguistic variables
used are NB-Negative Big NS – Negative Small ZE- Zero PS- Positive Small
PB -Positive Big.

4.1.1.2 Fuzzy Logic System (FLS)

Major numbers of probabilistic estimation are possible in Fuzzy


logic that leads to various mappings. In general, a FLS is a nonlinear mapping
of an input data (feature) vector into a scalar output data. The richness of the
FL is that, there are enormously good number of possibilities that lead to large
number of different mappings. This richness does require a careful
understanding of FL and the elements that comprise FLS.

FLS contains four components: fuzzifier, rules, inference engine,


and defuzzifier. Once the rules have been established, a FLS can be viewed as
a mapping from inputs to outputs, and this mapping can be expressed
quantitatively as y = f(x).
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Fuzzy inference is the process that maps the given input into the
output using Fuzzy logic. Any Fuzzy inference system can be simply
represented in four integrating blocks:

1. Fuzzification: The process of transforming any crisp value to the


corresponding linguistic variable (Fuzzy value) based on the
appropriate membership function.

2. Knowledge base: Contains membership functions definitions


and the necessary IF-THEN rules.

3. Inference engine: This simulates human decision making


through using implication and aggregation processes.

4. Defuzzification: The process of transforming the FLC output


into a crisp numerical value.

Rules may be provided by experts or can be extracted from


numerical data. In either case, engineering rules are expressed as a collection
of IF – THEN statements, e.g. “IF u 1 is very warm and u 2 is quite low,
THEN turn v slightly to right”. This rule reveals that it needs an understanding
of:

1. Linguistic variables versus numerical values of a variable (eg..


very warm versus 40° C);

2. Quantifying linguistic variables (eg. u 1 may have a finite


number of linguistic terms associated with it, ranging from
extremely hot to extremely cold), which is done using FLC
membership functions;
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3. Logical connections for linguistic variables (eg. “and”, “or”


etc.,); and Implications, i.e., “IF A THEN B”. Additionally the
comprehension of combining more than one rule is required.

The fuzzifier maps crisp numbers into Fuzzy sets. It is needed in


order to activate rules which are in terms of linguistic variables, which have
Fuzzy sets associated with them. The inference engine of the FLS maps input
Fuzzy sets into output Fuzzy sets. In many applications, crisp number must be
obtained at the output of an FLS. The defuzzifier maps output sets into crisp
numbers.

4.1.1.3 Fuzzy If-Then Rules

There are three inputs and each input is represented by three


linguistic variables. Therefore there are 27 rules in the Fuzzy Logic Based
Representative Quality Power Factor (FRQPF) module. The Fuzzy inference
rules are stated below.

1) If (DPF is L) and (TEPF is L) and (OSCPF is L) then (RQPF is L)

2) If (DPF is L) and (TEPF is L) and (OSCPF is M), then (RQPF is ML)

3) If (DPF is L) and (TEPF is L) and (OSCPF is H), then (RQPF is SL)

4) If (DPF is L) and (TEPF is M) and (OSCPF is L), then (RQPF is ML)

5) If (DPF is L) and (TEPF is M) and (OSCPF is M) then (RQPF is SL)

6) If (DPF is L) and (TEPF is M) and (OSCPF is H), then (RQPF is M)

7) If (DPF is L) and (TEPF is H) and (OSCPF is L), then (RQPF is SL)

8) If (DPF is L) and (TEPF is H) and (OSCPF is M), then (RQPF is M)


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9) If (DPF is L) and (TEPF is H) and (OSCPF is H) then (RQPF is SH)

10) If (DPF is M) and (TEPF is L) and (OSCPF is L), then (RQPF is ML)

11) If (DPF is M) and (TEPF is L) and (OSCPF is M), then (RQPF is SL)

12) If (DPF is M) and (TEPF is L) and (OSCPF is H), then (RQPF is M)

13) If (DPF is M) and (TEPF is M) and (OSCPF is L) then (RQPF is SL)

14) If (DPF is M) and (TEPF is M) and (OSCPF is M), then (RQPF is M)

15) If (DPF is M) and (TEPF is M) and (OSCPF is H), then (RQPF is SH)

16) If (DPF is M) and (TEPF is H) and (OSCPF is L), then (RQPF is M)

17) If (DPF is M) and (TEPF is H) and (OSCPF is M) then (RQPF is SH)

18) If (DPF is M) and (TEPF is H) and (OSCPF is H), then (RQPF is MH)

19) If (DPF is H) and (TEPF is L) and (OSCPF is L), then (RQPF is SL)

20) If (DPF is H) and (TEPF is L) and (OSCPF is M), then (RQPF is M)

21) If (DPF is H) and (TEPF is L) and (OSCPF is H) then (RQPF is SH)

22) If (DPF is H) and (TEPF is M) and (OSCPF is L), then (RQPF is M)

23) If (DPF is H) and (TEPF is M) and (OSCPF is M), then (RQPF is SH)

24) If (DPF is H) and (TEPF is M) and (OSCPF is H), then (RQPF is MH)

25) If (DPF is H) and (TEPF is H) and (OSCPF is L) then ( RQPF is SH)

26) If (DPF is H) and (TEPF is H) and (OSCPF is M), then (RQPF is MH)

27) If (DPF is H) and (TEPF is H) and (OSCPF is H), then (RQPF is H)


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Fuzzy If-Then Rules

By using Mamdani‟s FIM, the FRQPF module has three inputs and
each input is represented by three linguistic variables. Therefore there are 27
rules in the FRQPF module. The Fuzzy inference rules are stated below.

1) If (FPSPF is L) and (TEPF is L) and (OSCPF is L) then(RQPF is L)

2) If (FPSPF is L) and (TEPF is L) and (OSCPF is M), then(RQPF is ML)

3) If (FPSPF is L) and (TEPF is L) and (OSCPF is H), then(RQPF is SL)

4) If (FPSPF is L) and (TEPF is M) and (OSCPF is L), then(RQPF is ML)

5) If (FPSPF is L) and (TEPF is M) and (OSCPF is M) then(RQPF is SL)

6) If (FPSPF is L) and (TEPF is M) and (OSCPF is H), then(RQPF is M)

7) If (FPSPF is L) and (TEPF is H) and (OSCPF is L), then(RQPF is SL)

8) If (FPSPF is L) and (TEPF is H) and (OSCPF is M), then(RQPF is M)

9) If (FPSPF is L) and (TEPF is H) and (OSCPF is H) then(RQPF is SH)

10) If (FPSPF is M) and (TEPF is L) and (OSCPF is L), then(RQPF is ML)

11) If (FPSPF is M) and (TEPF is L) and (OSCPF is M), then(RQPF is SL)

12) If (FPSPF is M) and (TEPF is L) and (OSCPF is H), then(RQPF is M)

13) If (FPSPF is M) and (TEPF is M) and (OSCPF is L) then(RQPF is SL)

14) If (FPSPF is M) and (TEPF is M) and (OSCPF is M), then(RQPF is M)

15) If (FPSPF is M) and (TEPF is M) and (OSCPF is H), then(RQPF is SH)


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16) If (FPSPF is M) and (TEPF is H) and (OSCPF is L), then(RQPF is M)

17) If (FPSPF is M) and (TEPF is H) and (OSCPF is M) then(RQPF is SH)

18) If (FPSPF is M) and (TEPF is H) and (OSCPF is H), then(RQPF is MH)

19) If (FPSPF is H) and (TEPF is L) and (OSCPF is L), then(RQPF is SL)

20) If (FPSPF is H) and (TEPF is L) and (OSCPF is M), then(RQPF is M)

21) If (FPSPF is H) and (TEPF is L) and (OSCPF is H) then(RQPF is SH)

22) If (FPSPF is H) and (TEPF is M) and (OSCPF is L), then(RQPF is M)

23) If (FPSPF is H) and (TEPF is M) and (OSCPF is M), then(RQPF is SH)

24) If (FPSPF is H) and (TEPF is M) and (OSCPF is H), then(RQPF is MH)

25) If (FPSPF is H) and (TEPF is H) and (OSCPF is L) then(RQPF is SH)

26) If (FPSPF is H) and (TEPF is H) and (OSCPF is M), then(RQPF is MH)

27) If (FPSPF is H) and (TEPF is H) and (OSCPF is H), then(RQPF is H)

4.1.1.4 Design of FLC control strategy for HRB and MLI

FLC control scheme (FCS) for the 13 Bus test system is considered
with hybrid resonant boost (HRB) converter and multilevel inverter. The
proposed system is implemented for 225 kW WECS power plant model. HRB
control has been implemented using FLC. FLC algorithm reduces the output
power oscillation and operates the wind system at maximum operating point.
The HRB feeds a DC power to a new 9-level inverter to ensure the quality of
sinusoidal output. This nine level inverter reduces the harmonics in the system
to the standard level. HRB and 9-level Inverter has been simulated using
MATLAB. The simulation results are presented to validate the function of
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FLC.The block diagram of FLC control strategy for HRB and MLI is shown
in Figure 4.2.

Figure 4.2 Generalized block diagram of FLC Control Strategy For HRB
and MLI

The proposed HRB regulates the output of WES about its


maximum level, by tracking the operating point using FLC algorithm. This
FLC identifies the suitable duty cycle required by the converter to deliver the
DC output with very low voltage ripple. The proposed converter also
improves the overall conversion ratio and also reduces the switching losses of
the converter.

4.1.1.5 Implementation of FLC control strategy

In FLC control strategy, digital control of HRB and MLI are


implemented in a single low cost digital controller. The implementation of
boost converter topology is achieved using separate digital controller. Also the
implementation of MLI topologies has been done using separate controller
and has been explained in earlier. The main objective of the FLC is to
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minimize the number of controllers used in the hardware for effective control
operation. The speed of the controller is also taken much care while
implementing Fuzzy control logic. Because the control logic contains the FLC
for HRB converter as well as the Modified PWM signals to the 9-Level
inverter that runs parallel for the entire control operation.

Maximum power point tracking in WECS is a sensitive process,


because the output of WECS is affected by various factors like wind velocity,
tip speed ratio etc. These effects may be for few micro seconds, but the output
of the WECS system becomes very low or zero during this period. During low
voltage, traditional power conditioners fail to maintain the operating point of
WECS apart from generating output voltage oscillation in the DC to DC
converter output. Hence the power to the Inverter or MLI is varied
continuously. These factors have been considered while selecting the control
algorithm and suitable controller for the real time implementation. The speed
of the algorithm and its controller should be more. FLC algorithm has the
ability to meet the above said requirements. It maintains the power for few
micro seconds and also adjusts the duty cycle according to the power variation
from the WES. Simultaneously the control of the 9-Level inverter topology
has been carried out using Modified PWM technique. The operating speed of
this controller is about 5μS. Hence the variation of power from the WES is
identified and controlled within short time.

The simulation study is carried out for HRB and 9-level inverter for
different operating conditions. Finally the FLC for the HRB and 9-level
inverter topology is simulated using MATLAB simulink environment. The
output of the HRB converter with FLC is verified for the various input
conditions like temperature and irradiation levels. While comparing with other
resonant converter topologies like Zero voltage switching (ZVS) and Zero
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current switching (ZCS), the output of the HRB is improved to the maximum
level.

4.2 IMPLEMENTATION OF FLC BASED PWM


CONTROLLER FOR FACTS DEVICES

Simulation of FLC

FLC control of modified 9-level inverter and proposed HRB is


analyzed using MATLAB simulation. The speed of the controller has been
analyzed for the various parameter variations like wind speed and output
voltage changes in the HRB. The performance of the FLC is analyzed from
the simulation results.

Figure 4.3 MATLAB Simulink Diagram of FLC


91

The FLC for the HRB and 9-level inverter has been considered and
shown in fig.4.3. The FLC provides low THD, switching losses and improves
overall efficiency of the converter to 97.9%. This modified nine level inverter
topology also increases the output voltage level with reduced power rating of
the switches. This FLC can be implemented in a low cost digital controller.

4.2.1 Implementation of FLC based VSC with STATCOM, UPQC


and IPQC for Integrating 13 Bus WECS

This section considers adding FLC based VSC with FACTS


devices namely STATCOM, UPQC and IPQC for integrating 13 Bus WECS.
Disturbance to the system may be introduced by random wind speeds and by
external means. In simulation, disturbance is assumed to exist from 0.8 sec to
1.5 sec. It will affect the WECS output voltage during this period. The
STATCOM connected to buses TL 8-11, identified as weak buses will
compensate the change in bus output voltage. Further the variables, voltage,
current THDs of voltage and current are observed from the simulation during,
before and after the disturbance conditions. These results will be presented in
terms of plots and in the tabular form. The evaluation and discussion over this
result will be presented in section 4.4.

The above simulation is repeated with UPQC now. Here IPQC is


connected between the buses TL 8-11 and TL 7-13.

4.3 IMPLEMENTATION OF HEXAGRAM BASED FACTS


DEVICES WITH FLC

The Hexagram is composed of six three phase, two level voltage


source inverter modules, with separated capacitive DC buses. The modules are
interconnected through the coupling inductors wound on one common
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magnetic core. According to the Hexagram phase to phase voltages are


composed of eight equal steps presenting the nine level waveforms and each
step is formed by the corresponding phase to phase voltage of a three phase
VSC module. The Hexagram and CMC requires the least number of total
components. The cost of an MC monotonically increases with the number of
components. Moreover the reliability of a system is inversely proportional to
the number of its components. In a Hexagram STATCOM, STATCOM
current reflects the active current component corresponding to the STATCOM
active power which is necessary to cover the active power losses and stabilize
DC Bus voltage, ie., the equivalent STATCOM resistance will be adjusted by
duty cycle during each switching cycle of converter.

4.3.1 Implementation of FLC based Hex-STATCOM, Hex-UPQC


and Hex-IPQC for Integrating 13 Bus WECS

This section demonstrates adding FLC based Hexagram with


FACTS devices namely Hex-STATCOM, Hex-UPQC and Hex-IPQC for
integrating 13 Bus WECS. Disturbance to the system may be introduced by
random wind speeds and by external means. In simulation disturbance is
assumed to exist from 0.8 sec to 1.5 sec. It affects the WECS output voltage
during this period. The Hex-STATCOM connected to buses TL 8-11, identified
as weak buses will compensate the change in bus output voltage. Further the
variables, voltage, current THDs of voltage and current are observed from the
simulation during, before and after the disturbance conditions. These results
will be presented in terms of plots and in tabular form. The evaluation and
discussion over this result will be presented in section 4.4.

The above simulation is repeated with Hex-UPQC now. Here Hex-


IPQC is connected between the buses TL 8-11 and TL 7-13.
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4.4 RESULTS AND DISCUSSION

4.4.1 Results of FLC Based VSC-STATCOM System

The results are available in the simulation output shown in


Figure 4.4 – 4.6. The THD of voltages and THD of current can be observed
from the simulation covering the three periods,

i. Pre disturbance period

ii. The disturbance period

iii. Post disturbance period.

Corresponding voltage THDs for Bus 7 are:

(i) 12.09 % (ii) 19.21% and (iii) 12.14%.

Similarly the current THDs are:

(ii) 24.05% (ii) 13.09% and (iii) 26.64%.

During disturbance, voltage distortion increases to 19.21% from


12.09%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 13.09% during disturbance period from 24.05%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period it is increased to 26.64%.

Similar analysis is carried out for Bus 8 (Generator Bus). The


corresponding voltage THD values are:

(i) 12.95% (ii) 15.73% and (iii) 16.89%.


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The current THD values are:

(i) 24.05% (ii) 13.1% and (iii) 26.65%.

With regard to load bus,12 the voltage THD values are:

(i) 12.09% (ii) 19.21% and (iii) 12.14%.

The current THD values are:

(i) 12.09% (ii) 19.21% and (iii) 12.14%.

It is interesting to note that voltage THDs show an increase during


disturbance whereas with regard to current THD it is just the reverse.
95

FLC based VSC-STATCOM


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.4 BUS 7 Voltage and Current waveforms with THDs from FLC
based VSC –STATCOM Control
96

FLC based VSC-STATCOM


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.5 BUS 8 Voltage and Current waveforms with THDs from FLC
based VSC –STATCOM Control
97

FLC based VSC-STATCOM


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.6 Bus 12 Voltage and Current waveforms with THDs from
FLC based VSC –STATCOM Control
98

4.4.2 Results of FLC Based VSC -UPQC System

The results are available in the simulation output shown in


Figure 4.7 – 4.9. The voltage THDs for Bus 7 are:

(i) 12.08 % (ii) 19.47% and (iii) 12.01%.

Similarly the current THDs are:

(i) 23.94% (ii) 17.08% and (iii) 23.06%.

During disturbance, voltage distortion increases to 19.47% from


12.08%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 17.08% during disturbance period from 23.94%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period, it is increased to 23.06%.

Similar analysis is carried out for Bus 8 (Generator Bus). The


corresponding voltage THD values are:

(i) 25.09% (ii) 24.65% and (iii) 22.1%.

The current THD values are:

(i) 10.99% (ii) 18.04% and (iii) 13.07%.

With regard to load bus 12, the voltage THD values are:

(i) 12.08% (ii) 19.47% and (iii) 12.01%.

The current THD values are:

(i) 12.08% (ii) 19.47% and (iii) 12.01%.


99

FLC based VSC-UPQC


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.7 BUS 7 Voltage and Current waveforms with THDs from FLC
based VSC –UPQC Control
100

FLC based VSC-UPQC


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.8 BUS 8 Voltage and Current waveforms with THDs from FLC
based VSC –UPQC Control
101

FLC based VSC-UPQC


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.9 Bus 12 Voltage and Current waveforms with THDs from FLC
based VSC –UPQC Control
102

4.4.3 Results of FLC Based VSC -IPQC System

The results are available in the simulation output shown in


Figure 4.10 – 4.12. The voltage THDs for bus 7 are:

(i) 12.58 % (ii) 19.72% and (iii) 12.53%.

Similarly current THDs are:

(i) 23.81% (ii) 12.82% and (iii) 26.22%.

During disturbance, voltage distortion increases to 19.72% from


12.58%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 12.82% during disturbance period from 23.81%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period it is increased to 26.22%.

Similar analysis is carried out for Bus 8 (Generator Bus). The


corresponding voltage THD values are:

(i) 13.16% (ii) 16.07% and (iii) 16.88%.

The current THD values are:

(i) 23.82% (ii) 12.82% and (iii) 26.23%.

With regard to load bus12, the voltage THD values are:

(i) 12.58% (ii) 19.72% and (iii) 12.53%.

The current THD values are:

(i) 12.58% (ii) 19.72% and (iii) 12.53%.


103

FLC based VSC-IPQC


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.10 BUS 7 Voltage and Current waveforms with THDs from
FLC based VSC –IPQC Control
104

FLC based VSC-IPQC


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.11 BUS 8 Voltage and Current waveforms with THDs from
FLC based VSC –IPQC Control
105

FLC based VSC-IPQC


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.12 Bus 12 Voltage and Current waveforms with THDs from
FLC based VSC –IPQC Control
106

4.4.4 Results of FLC Based Hex- STATCOM System

The results are available in the simulation output shown in


Figure 4.13 – 4.15. The voltage THDs for bus 7 are:

(i) 3.06 % (ii) 7.10% and (iii) 4.41%.

Similarly current THDs are:

(i) 8.16% (ii) 6.14% and (iii) 9.32%.

During disturbance, voltage distortion decreases to 7.10% from


3.06%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 6.14% during disturbance period from 8.16%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period it is increased to 9.32%.

Similar analysis is carried out for Bus 8 (Generator Bus). The


voltage THD values are:

(i) 3.11% (ii) 8.37% and (iii) 9.38%.

The current THD values are:

(i) 8.14% (ii) 6.58% and (iii) 8.72%.

With regard to load bus,12 the voltage THD values are:

(i) 3.06% (ii) 7.54% and (iii) 4.41%.

The current THD values are:

(i) 6.76% (ii) 8.73% and (iii) 7.94%.


107

FLC based Hex-STATCOM


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.13 BUS 7 Voltage and Current waveforms with THDs from FLC
based HEX –STATCOM Control
108

FLC based HEX-STATCOM


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.14 BUS 8 Voltage and Current waveforms with THDs from FLC
based HEX –STATCOM Control
109

FLC based HEX-STATCOM


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.15 Bus 12 Voltage and Current waveforms with THDs from
FLC based HEX –STATCOM Control
110

4.4.5 Results of FLC Based Hex- UPQC System

The results are available in the simulation output shown in


Figure 4.16 – 4.18. The voltage THDs for bus 7 are:

(i) 4.23 % (ii) 8.99% and (iii) 5.12%.

Similarly current THDs are:

(i) 7.89% (ii) 3.28% and (iii) 8.37%.

During disturbance, voltage distortion increases to 8.99% from


4.23%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 3.28% during disturbance period from 7.89%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period it is increased to 8.37%.

Similar analysis is carried out for bus 8 (Generator Bus). The


voltage THD values are:

(i) 7.79% (ii) 3.72% and (iii) 8.03%.

The corresponding current THD values are:

(i) 5.95% (ii) 6.03% and (iii) 4.95%.

With regard to load bus,12 the voltage THD values are:

(i) 4.68% (ii) 10.37% and (iii) 3.91%.

The current THD values are:

(i) 3.14% (ii) 5.89% and (iii) 3.92%.


111

FLC based Hex-UPQC


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.16 BUS 7 Voltage and Current waveforms with THDs from
FLC based HEX –UPQC Control
112

FLC based HEX-UPQC


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.17 BUS 8 Voltage and Current waveforms with THDs from
FLC based HEX –UPQC Control
113

FLC based HEX-UPQC


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.18 Bus 12 Voltage and Current waveforms with THDs from
FLC based HEX –UPQC Control
114

4.4.6 Results of FLC Based Hex- IPQC System

The results are available in the simulation output shown in


Figure 4.19 – 4.21. The voltage THDs for bus 7 are:

(i) 9.26 % (ii) 8.66% and (iii) 9.32%.

Similarly corresponding current THDs are:

(i) 8.37% (ii) 6.19% and (iii) 9.36%.

During disturbance, voltage distortion decreases to 8.66% from


9.26%, corresponding to pre disturbance period. The current THD values
reveal that it reduces to 6.19% during disturbance period from 8.37%
corresponding to pre disturbance period. But after clearance of disturbance,
i.e. during post disturbance period it is increased to 9.36%.

Similar analysis is carried out for Bus 8 (Generator Bus). The


corresponding voltage THD values are:

(i) 9.31% (ii) 7.87% and (iii) 14.97%.

The current THD values are:

(i) 8.51% (ii) 6.43% and (iii) 9.41%.

With regard to load bus,12 the voltage THD values are:

(i) 4.73% (ii) 7.29% and (iii) 4.76%.

The current THD values are:

(i) 3.93% (ii) 5.97% and (iii) 3.16%.


115

FLC based Hex-IPQC


Bus 7 Voltage THD Bus 7 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.19 BUS 7 Voltage and Current waveforms with THDs from FLC
based HEX –IPQC Control
116

FLC based HEX-IPQC


Bus 8 Voltage THD Bus 8 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.20 BUS 8 Voltage and Current waveforms with THDs from
FLC based HEX –IPQC Control
117

FLC based HEX-IPQC


Bus 12 Voltage THD Bus 12 Current THD
Before Disturbance Before Disturbance

During Disturbance During Disturbance

After Disturbance After Disturbance

Figure 4.21 Bus 12 Voltage and Current waveforms with THDs from
FLC based HEX –IPQC Control
118

4.4.7 Comparison of Results

Bus 12 Voltage THD (VSC Control) Bus 12 Current THD (VSC Control)
25 25

20 20

15 15

10 10

5 5

0 0
BD DD AD BD DD AD BD DD AD BD DD AD

Witout FLC With FLC Witout FLC With FLC

STATCOM UPQC IPQC STATCOM UPQC IPQC

Bus 7 Voltage THD (HEX Control) Bus 7 Current THD (HEX Control)
16 18
14 16
12 14
12
10
10
8
8
6
6
4 4
2 2
0 0
BD DD AD BD DD AD BD DD AD BD DD AD

Witout FLC With FLC Witout FLC With FLC

STATCOM UPQC IPQC STATCOM UPQC IPQC

Bus 8 Voltage THD (HEX Control) Bus 8 Current THD (HEX Control)
25 18
16
20 14
12
15
10
8
10
6
5 4
2
0 0
BD DD AD BD DD AD BD DD AD BD DD AD

Witout FLC With FLC Witout FLC With FLC

STATCOM UPQC IPQC STATCOM UPQC IPQC

BD – Before Disturbance, DD – During Disturbance, AD- After Disturbance

Figure 4. 22 Device wise comparison – Without and with FLC based VSC
& HEX Control
119

For easy understanding of the results, they are given in the form of
bar charts as shown in Figure 4.22. It also offers device level comparison of
THD values. The numerical value of the results are tabulated in Appendix.

4.5 SUMMARY

In this chapter, simulation of various FACTS controllers for 13 Bus


WECS is considered. Each FACTS controller is simulated with FLC
algorithm controlling VSC and Hexagram converter models and tested for
different conditions such as before, during and after disturbance.

It is observed that Hexagram with FLC controller is able to recover


and maintain the voltage after disturbance. As there is scope for further
performance improvement with ANFIS, connecting ANFIS with VSC and
Hexagram controllers is taken up in the next chapter.

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