Professional Documents
Culture Documents
APW8715A: Features General Description
APW8715A: Features General Description
APW8715A: Features General Description
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
RPOK
VIN
POK
VIN
H/L
LOUT VOUT
PFM
LX
CSS
SS
COUT
APW8715A
A
APW8715A QB : APW8715 XXXXX - Date Code
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
19 PGND
20 BOOT
21LDO
22 VIN
23 SS
18 LX
POK 1 17 LX
EN 2 16 LX
PFM 3 15 PGND
VIN LX
AGND 4 14 PGND
FB 5 13 PGND
TON 6 12 PGND
LDOIN 7
VIN 8
VIN 9
LX 10
LX 11
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA
o
Junction-to-Ambient Resistance in free air (Note 2) 50 C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
APW87 15A
Sym bol Pa ramete r Te st Condition
Min. Typ. Max. Unit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
APW87 15A
Sym bol Param eter Te st Condition
Min. Typ. Max. Unit
PO WER-OK INDICATOR
PO K i n from Lo wer (POK Go es
87 90 93 %
High)
V POK PO K Thre shold
PO K o ut from No rmal (PO K G oes
120 1 25 130 %
Low)
I POK PO K L eakage Cur rent VPOK=5V - 0.1 - µA
CURRE NT SE NS E
I OC P OCP Th reshold Va lley Cu rrent of IL 7 - - A
Zero Crossing Compara to r
VGND-L X Voltage, PFM=0V -5 0 5 mV
Offset
PRO TE CTION
VUV UVP Th reshold 65 70 75 %
UVP Debou nce Interval 16 µs
UVP Ena ble Delay EN high to UV P worka ble Tss ms
V OVR OV P Rising Thresho ld1 OVP Occur 120 1 25 130 %
OV P P ropag ation Delay VFB Rising , Over Voltage=10mV - 3 - µs
OTP Risin g Th reshold (Note o
TOTR - 1 45 - C
4)
o
OTP Hysteresis ( No te 4 ) - 45 - C
LDO OUTPUT
VLDO LDO Outpu t Voltage LDOIN=12 V, No lo ad - 5.3 - V
Pin Description
PIN
FUNCTION
NO. NAME
P ower-Go od Outpu t Pin of PWM. PO K is an op en-d rain output used to i ndicate the status of th e PW M
1 POK
o utp ut voltag e. Conn ect th e P OK in to +5V throu gh a pull -high resistor.
PW M an d L DO E nab le. PWM and LDO a re both enab led when EN=Hig h. Whe n EN=Lo w, PW M an d LDO
2 EN
a re both sh utd own.
P FM Se lectio n Inp ut. W hen the PFM is above hig h logic level, the Device is in force PW M mod e. When the
3 PFM
P FM is b elow low lo gic level, the device is in au to matic PFM/PW M Mode .
4 AGND S igna l Groun d for The IC.
O utput Voltag e Fee dback Pin. This pin is con nected to the resisti ve divide r tha t set the desire d output
5 FB
voltage . The POK , UVP, a nd OVP circuits de tect this si gnal to r eport output vo lta ge status.
6 TO N This Pin is Allowed to Adj ust Th e Swi tchin g Fre quen cy. Con nect a resistor RTON from TON pin to VIN pin.
7 LDOIN L DO Inp ut Pi n. Sup ply i nput for L DO ne eded .
B atte ry Voltage Input Pin. VIN powers line ar regu lators a nd is also used for th e con stant on-time PWM
8, 9, 22 VIN o n-time one-sho t circuits. Con nect V IN to the battery in put a nd bypass with a 1µF ca pacito r for noise
in te rfe rence.
Jun ction Po int o f Th e Hi gh-Si de MOSFET Source, Output Filter Inductor and The Lo w-S ide MOSFE T Dr ain
10, 11,
LX for PWM. Conne ct this pin to th e So urce of the h igh-side MOSFE T. L X serves a s the l owe r supp ly rail for the
1 6~1 8
UGATE high -side gate driver. LX is th e cur rent-sense inp ut for th e P WM.
12 ~15 ,
PGND P ower Grou nd of The LG ATE Lo w-S ide MOS FE T Drive rs.
19
S uppl y Input for The UGATE Gate Dri ver an d an interna l le ve l-shift circu it. Conne ct to an externa l capa ci tor
20 BOOT
to create a boosted volta ge suita ble to d rive a lo gic-level N-chann el MO SFET.
5 .3V Linea r Reg ulator Ou tpu t. L DO ca n p rovide a tota l o f 20mA , 5.3V exte rnal loa ds. It is al so supp ly
21 LDO voltage in put pin fo r Con tro l Circuitry. Bypass to GND with a mi nimum o f 1.0uF ceramic cap acito r for
stabili ty.
23 SS S oft Start Output. Conn ect a ca pacitor to GND to set the soft sta rt interval.
100
0.8
10
0.798
1
0.796
1.08 1.075
1.070
1.07 1.065
1.060
1.06
1.055 PFM Operation
PWM Operation
1.05 1.050
0 2 4 6 8 10 0 5 10 15 20 25 30
Output Current(A) Input Voltage(V)
Switching Frequency vs. Input Efficiency vs. Load Current
Voltage
100
340 VIN =5.5V
90
330
Efficiency (%)
Switching Frequency (kHz)
80
320
70
310
VIN =12V
60
300 VIN =19V
50
290
VOUT =1.05V
Fsw=500kHz
40
280
0 5 10 15 20 25 30 0.01 0.1 1 10
90
Efficiency (%)
80
VOUT =3.3V
70
VOUT =1.5V
60
V OUT =1.05V
50
VIN =19V
40 Fsw=500kHz
0.01 0.1 1 10
Load Current (A)
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
V EN V EN
1 1
VLX VLX
2 2
V OUT V OUT
3 3
V POK V POK
4 4
CSS=10nF CSS=10nF
CSS=10nF
V EN
VEN
1 1
VLX
2 VLX
2
V OUT VOUT
V POK VPOK
3 3
4 4
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
VOUT V OUT
1 1
VLX
2
VLX
2 IL
IL
3 3
VOUT VOUT
1 1
VLX
VLX
2 2
IL
IL
3 3
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
VOUT VOUT
1 1
VLX VLX
2 2
IL IL
3 3
Block Diagram
GND
125% VREF Mean Value
Circuit
Delay
VIN
Fault LDO
Latch
Logic
UV BOOT
PFM
LDO
LDO
LX
VREF
LG
POR Soft-Start Gate
EN Driver
LDO LDO PGND
LDOIN SS
APW8715A
EN VIN 19V
LDOIN CIN
10uF /25V X 4
(MLCC)
Mode
Selection PFM 100K
+5.3V TON
LDO LOUT VOUT
1.0uH 1.058V, 6A
LX
CLDO
1uF CBOOT
0.1uF
RPOK
100k RTOP
20k COUT1 COUT2
BOOT 150uF 22uFx4
POK
FB
RGND
62k
SS
AGND PGND
Note5: It's recommended that EN enable signal can be present after VIN, LDOIN and LDO are ready.
APW8715A
EN VIN 19V
CIN
10uF /25V X 4
Mode (MLCC)
Selection PFM 100K
LDOIN
5V TON
LDO LOUT VOUT
1.0uH 1.058V, 6A
LX
CLDO
1uF CBOOT
0.1uF
RPOK
100k RTOP
COUT1 COUT2
20k
BOOT 150uF 22uFx4
POK
FB
RGND
62k
SS
AGND PGND
Note5: It's recommended that EN enable signal can be present after VIN, LDOIN and LDO are ready.
APW8715A
EN VIN 5V
LDOIN CIN
10uF /12V X 4
(MLCC)
PFM 100K
Mode
Selection
TON
LDO LOUT VOUT
1.0uH 1.058V, 6A
LX
CLDO
1uF CBOOT
0.1uF
RPOK
100k RTOP
COUT1 COUT2
20k
BOOT 150uF 22uFx4
POK
FB
RGND
62k
SS
AGND PGND
Note5: It's recommended that EN enable signal can be present after VIN, LDOIN and LDO are ready.
Function Description
Constant-On-Time PWM Controller with Input Feed-
Where FSW is the nominal switching frequency of the
Forward
converter in PWM mode.
The constant on-time control architecture is a pseudo- The load current at handoff from PFM to PWM mode is
fixed frequency with input voltage feed-forward. This ar- given by:
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor, 1 VIN - VOUT
ILOAD (PFM to PWM) = × × TON-PFM
so the output ripple voltage provides the PWM ramp signal. 2 L
V -V 1 V
In PFM operation, the high-side switch on-time controlled = IN OUT × × OUT
2L FSW VIN
by the on-time generator is determined solely by a one-
shot whose pulse width is inversely proportional to input Forced-PWM Mode
voltage and directly proportional to output voltage. In PWM
The Forced-PW M mode disables the zero-crossing
operation, the high-side switch on-time is determined by
comparator, which truncates the low-side switch on-time
a switching frequency control circuit in the on-time gen-
at the inductor current zero crossing. This causes the
erator block.
low-side gate-drive waveform to become the complement
The switching frequency control circuit senses the switch-
of the high-side gate-drive waveform. This in turn causes
ing frequency of the high-side switch and keeps regulat-
the inductor current to reverse at light loads while UG
ing it at a constant frequency in PWM mode. The design
maintains a duty factor of VOUT/VIN. The benefit of Forced-
improves the frequency variation and is more outstand-
PWM mode is to keep the switching frequency fairly
ing than a conventional constant on-time controller, which
constant. The Forced-PWM mode is most useful for re-
has large switching frequency variation over input voltage,
ducing audio frequency noise, improving load-transient
output current and temperature. Both in PFM and PWM,
response, and providing sink-current capability for dy-
the on-time generator, which senses input voltage on
namic output voltage adjustment.
VIN pin, provides very fast on-time response to input line
When V PFM is above the PFM high threshold (2.5V,
transients.
minimum), the converter is in forced-PWM mode. When
Another one-shot sets a minimum off-time (typical:
VPFM is below the PFM low threshold (0.5V, maximum),
250ns). The on-time one-shot is triggered if the error com-
the chip is in automatic PFM/PWM Mode.
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
Power-On-Reset
shot has timed out.
A Power-On-Reset (POR) function is designed to prevent
Over-Current Protection of the PWM Converter wrong logic controls when the LDO voltage is low. The
In PFM mode, an automatic switchover to pulse-frequency POR function continually monitors the bias supply volt-
modulation (PFM) takes place at light loads. This age on the LDO pin if at least one of the enable pins is set
switchover is affected by a comparator that truncates the high. When the rising LDO voltage reaches the rising
low-side switch on-time at the inductor current zero POR voltage threshold (4.35V, typical), the POR signal
crossing. This mechanism causes the threshold between goes high and the chip initiates soft-start operations.
PFM and PWM operation to coincide with the boundary Should this voltage drop lower than 4.25V (typical), the
between continuous and discontinuous inductor-current POR disables the chip.
operation (also known as the critical conduction point).
EN Pin Control
The on-time of PFM is given by:
W hen V EN is above the EN high threshold (1.6V,
1 VOUT
minimum), the converter is enabled. When VEN is below
TON -PFM = ×
FSW VIN the EN low threshold (0.5V, maximum), the chip is in the
shutdown and only low leakage current is taken from
VCC.
0 Time
26.3× 10-12 × RTON(Ω)
TON =
VIN(V)
Figure 1. Current Limit algorithm
Where:
The PWM controller uses the low-side MOSFETs on-re- RTON is the resistor connected from TON pin to VIN pin.
sistance R DS(ON) to monitor the current for protection Furthermore, The approximate PWM switching frequency
against shorted outputs. The MOSFET’s RDS(ON) is varied is written as:
by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s VOUT
D VIN
datasheet. TON = ,FSW =
FSW TON
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at LX. Where:
Place the hottest power MOSEFTs as close to the IC as FSW is the PWM switching frequency.
possible for best thermal coupling. When combined with
the under-voltage protection circuit, this current-limit
method is effective in almost every circumstance.
Application Information
Output Inductor Selection A good starting point is to choose the ripple current to be
The output voltage is adjustable from 0.8V to 12V with a approximately 30% of the maximum output current. Once
resistor-divider connected with FB, GND, and converterˇ¦s the inductance value has been chosen, selecting an in-
output. Using 1% or better resistors for the resistor-di- ductor that is capable of carrying the required peak cur-
vider is recommended. The output voltage is determined rent without going into saturation.In some types of
by: inductors, especially core that is made of ferrite, the ripple
current will increase abruptly when it saturates. This re-
R TOP sults in a larger output ripple voltage. Besides, the induc-
VOUT = 0.8 × (1 + )
R GND tor needs to have low DCR to reduce the loss of efficiency.
Where 0.8 is the reference voltage, RTOP is the resistor Output Capacitor Selection
connected from converter¡¦s output to FB, and RGND is the Output voltage ripple and the transient voltage deviation
resistor connected from FB to GND. Suggested RGND is in are factors that have to be taken into consideration when
the range from 1k to 20kΩ. To prevent stray pickup, locate selecting an output capacitor. Higher capacitor value and
resistors RTOP and RGND close to APW8715A. lower ESR reduce the output ripple and the load transient
drop. Therefore, selecting high performance low ESR
capacitors is recommended for switching regulator
Output Inductor Selection
applications. In addition to high frequency noise related
The duty cycle (D) of a buck converter is the function of the
to MOSFET turn-on and turnoff, the output voltage ripple
input voltage and output voltage. Once an output voltage
includes the capacitance voltage drop ∆VCOUT and ESR
is fixed, it can be written as:
voltage drop ∆V ESR caused by the AC peak-to-peak
inductor’s current. These two voltages can be represented
VOUT
D= by:
VIN
IRIPPLE
∆COUT =
The inductor value (L) determines the inductor ripple 8 × COUT × FSW
current, IRIPPLE, and affects the load transient response.
Higher inductor value reduces the inductorˇ¦s ripple cur-
∆VESR = IRIPPLE × RESR
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by: These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
VIN - VOUT VOUT capacitors have to be paralleled to achieve the desired
IRIPPLE = ×
FSW × L VIN ESR value. If the output of the converter has to support
another load with high pulsating current, more capacitors
Where FSW is the switching frequency of the regulator. are needed in order to reduce the equivalent ESR and
Although the inductor value and frequency are increased suppress the voltage ripple to a tolerable level. A small
and the ripple current and voltage are reduced, a tradeoff decoupling capacitor (1µF) in parallel for bypassing the
exists between the inductor’s ripple current and the regu- noise is also recommended, and the voltage rating of the
lator load transient response time. output capacitors are also must be considered.
A smaller inductor will give the regulator a faster load To support a load transient that is faster than the switch-
transient response at the expense of higher ripple current. ing frequency, more capacitors are needed for reducing
Increasing the switching frequency (FSW ) also reduces the voltage excursion during load step change. Another
the ripple current and voltage, but it will increase the aspect of the capacitor selection is that the total AC cur-
switching loss of the MOSFETs and the power dissipa- rent going through the capacitors has to be less than the
tion of the converter. The maximum ripple current occurs rated RMS current specified on the capacitors in order to
at the maximum input voltage. prevent the capacitor from over-heating.
TQFN4x4-23
4mm Unit:mm
ThermalVia
diameter
0.3mm X 12
0.3
0.4 4mm
2.95
2.7
0.5
0.25 0.5
0.2
* Just Recommend
Package Information
TQFN4x4-23
D
A
b
Pin 1
A1
A3
NX
E1
L K E2
D1
D2
S TQFN4x4-23
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.032
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.20 0.30 0.008 0.012
D 3.90 4.10 0.154 0.161
D1 2.58 2.78 0.102 0.109
D2 2.95 3.15 0.116 0.124
E 3.90 4.10 0.154 0.161
E1 1.24 1.44 0.049 0.057
E2 0.85 1.05 0.033 0.041
e 0.50 BSC 0.020 BSC
L 0.35 0.45 0.014 0.018
K 0.20 0.008
aaa 0.08 0.003
OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 A
OD1 B
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.50±0.10
-0.00 -0.20
TQFN4x4 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.00±0.10 8.00±0.10 2.00±0.05 1.5 MIN. 4.30±0.20 4.30±0.20 1.00±0.20
-0.00 -0.40
(mm)
Classification Profile
Customer Service
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838