Last Updated on 2nd July 2020

Ayushi Arya
LinkedIn : ayushiarya
Email : ayushiarya | 7997083650

EDUCATION WORK EXPERIENCE

BITS PILANI UNIVERSITY SAMSUNG RESEARCH | SOFTWARE DEVELOPMENT INTERN
HYDERABAD CAMPUS Jan 2020 - June 2020 | Bangalore
B.E. EEE | 2016-2020 • Working in the IoT division/ Tizen Web Platform team of Samsung R&D
CGPA : 7.77 • Involved with TizenOS development, wrote APIs for the Tizen Web Engine for
features like accessibility, android intent, scrollbars, context and popup menu
DAV PUBLIC SCHOOL and several other small features
Grad. May 2016| Jamshedpur, India
• Worked with proprietary Blackduck Protex software to identify license conflicts
CBSE | 91.8%
related to Web Engine release
• Contributing to computational load and resource offloading implementation
task of Javascript API in distributed web engine
COURSEWORK
CSIR - CIMFR | RESEARCH INTERN
UNDERGRADUATE May 2018 – July 2018 | Dhanbad
Data Structures and Algorithms • Developed and successfully tested the Wireless Borehole Extensometer com-
Computer Architecture plying with the safety standards laid out by MSHA (Mine Safety and Health As-
Object Oriented Programming sociation) ,under the guidance of Principal Scientists of Mine Mechanization and
Operating Systems Technology Department,CSIR-CIMFR
Analog and Digital VLSI design • The extremely cost effective ( 2.5 times cheaper than the mechanical devices cur-
Embedded System Design rently in use) device had the potential to serve as an alarm predictor in case of
mine roof collapse, which typically had cost lives of >10000 miners till date in
Dhanbad alone
SKILLS
PROGRAMMING ACADEMIC PROJECTS | BITS
Intermediate:
C • C++ • Verilog LIBRARY MANAGEMENT SYSTEM
Familiar: Feb 2019 – April 2019
Java • NodeJS • Javascript • Developed a prototype of the library management system with three levels of
git • linux • shell scripting login access with different features for each level , governed by OOP paradigms
Bootstrap 4 • React Native • Java (Windows Builder APIs) and SQL were used to implement frontend and
MongoDB • React backend respectively
OTHERS PROCESSOR DESIGN USING VERILOG
• Excellent problem solving skills Jan 2019 – Apr 2019
• Hard working, motivated
• Implemented single-stage and pipelined MIPS like processor using Verilog HDL
• Agile software development practices
• 4 stage design for pipelined processor involved Instruction Fetch, Instruction
• Good communication skills
Decode, ALU and Writeback stage blocks along with the pipeline registers
• Team worker
• Designed the datapath for the three classes of instructions present in MIPS

MODELLING ABS FOR VARYING ROAD CONDITIONS

Aug 2018 – Nov 2018
• Explored in details the control strategy of the anti-lock braking system in the ve-
hicles to optimize slip ratio to facilitate in preventing skidding
• Detailed analysis was done to obtain Transfer Function and MATLAB Simulink
Model was developed
• Model was simulated to obtain transfer characteristics for varied road condi-
tions