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  • FA17-EEE-008 Week2 Lecture3

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    Hammad Satti
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    1. In CMOS devices, interconnects use most of the area while transistors are hidden under wires. There are different wiring layers like Metal 1, Metal 2, and Polysilicon that contribute to delay and noise. 2. Wires have specifications like thickness, width, spacing, length, and pitch that determine their resistance. Resistance does not change if length and width are doubled together. 3. Contact and via resistance can be reduced by using multiple contacts. Capacitance between wires depends on their orientation, with minimum capacitance when wires are orthogonal.

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    1. In CMOS devices, interconnects use most of the area while transistors are hidden under wires. There are different wiring layers like Metal 1, Metal 2, and Polysilicon that contribute to delay and noise. 2. Wires have specifications like thickness, width, spacing, length, and pitch that determine their resistance. Resistance does not change if length and width are doubled together. 3. Contact and via resistance can be reduced by using multiple contacts. Capacitance between wires depends on their orientation, with minimum capacitance when wires are orthogonal.

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    15 views2 pages

    FA17-EEE-008 Week2 Lecture3

    Uploaded by

    Hammad Satti
    1. In CMOS devices, interconnects use most of the area while transistors are hidden under wires. There are different wiring layers like Metal 1, Metal 2, and Polysilicon that contribute to delay and noise. 2. Wires have specifications like thickness, width, spacing, length, and pitch that determine their resistance. Resistance does not change if length and width are doubled together. 3. Contact and via resistance can be reduced by using multiple contacts. Capacitance between wires depends on their orientation, with minimum capacitance when wires are orthogonal.

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    of 2

    SUMMARY OF LECTURE 3 (WEEK

    2)
    In CMOS devices we can say that interconnects use most of the area itself and the coverage of transistor
    is less which is hidden under wires. There are different layers such as Metal 1, Metal 2, Polysilicon, etc.
    in wiring that contributes in delay and noise when and where needed not only this wiring (some metals)
    orthogonally can reduce the effect of capacitance. Wires have following specifications:

    1. Finite thickness
    2. Dependent on process
    3. Width of wire is W
    4. Spacing between size is s
    5. Length of wire is W
    6. The pitch of two wire is P = W + s
    7. Resistance of wire = (p * l)/(t * W)

    If the length and width is double then there will be no change in resistance as long as they both are not
    changed with different value, hence resistance is irrespective of size of the wire.

    Contact and via has resistance around 2 to 20 ohms which can be reduced by using multiple contacts
    that can also reduce overall resistance. Capacitive effects of metals is different for different orientations
    which is concluded from the two statements given below:

    1. If wire in two layers are placed parallel then the capacitive effect will be maximum
    2. If wire in two layers are placed orthogonally then the capacitive effect will be minimum

    Capacitance increases with increase in overlapping area which can be decreased when wires on layers
    are placed orthogonally that’s why capacitance is minimum here. It is also present between side by side
    metals and metals on top and bottom. When doing wiring the diffusion is not recommended as it has
    high capacitive and resistive effect as compared to gate while polysilicon are not used for longer
    connects but for transitive gate because it has lower capacitance and has high resistance.

    Three models can be used to mode the segment of a wire as mentioned below:

    1. L model
    2. Pi model (|---|)
    3. T model

    Total segments of wire is denoted by Ns whereas Ns = L/w, Total resistance can be calculated from
    R=Rs * Ns or R= Rs * (L/w) and total capacitance can be calculated from C=C micron * L

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