Verilog Program for 4 bit binary, BCD counters

i) BCD counters

BLOCKDIAGRAM AND TRUTHTABLE:

VERILOG PROGRAM:
module binary(clk,rst,count);
input clk,rst;
output[3:0] count;
reg[3:0] count;
wire clkd;
reg [21:0] divider;
initial
begin
count=4'b0000;
end
always@(posedge clk)
begin
divider=divider+1;
end
assign clkd=divider[21];
always@(posedge clkd)
begin
if(rst)
count=4'b0000;
else
begin
count=count+1;
if(count==4’b1010)
count=4’b0000;
end
end
endmodule

ii) Binary counter

BLOCKDIAGRAM AND TRUTHTABLE:

VERILOG PROGRAM:
module binary(clk,rst,count);
input clk,rst;
output[3:0] count;
reg[3:0] count;
wire clkd;
reg [21:0] divider;
initial
begin
count=4'b0000;
end
always@(posedge clk)
begin
divider=divider+1;
end
assign clkd=divider[21];
always@(posedge clkd)
begin
if(rst)
count=4'b0000;
else
begin
count=count+1;
end
end
endmodule

Verilog code to control speed, direction of Stepper motor

module stepper(clk,rst,dir,dout);
input clk,rst,dir;
output [3:0] dout;
reg [26:0] clkd;
reg [3:0] shift=4'b1001;
always @(posedge clk)
begin
clkd=clkd+1'b1;
end
always @ (posedge clkd[20])
begin
if(rst)
shift<=4'b1001;
else if(dir)
 shift<={shift[0],shift[3:1]};
else
shift<={shift[2:0],shift[3]};
end
assign dout[3:0]=shift[3:0];
endmodule

Write verilog code to display data on Seven segment display

module segment7(bcd, seg); //Declare inputs, outputs and internal variables.

input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal
number.
default : seg = 7'b1111111;
endcase
end
endmodule

Write Verilog code to generate different waveforms

AIM: To Write Verilog code to generate square waveform

VERILOG PROGRAM:
module square(clk,rst,dout);
input clk,rst;
output [7:0] dout;
reg [24:0]clkd;
reg [7:0] tmp,counter;
always @(posedge clk)
begin
clkd=clkd+1'b1;
end
always @ (posedge clkd[10])
begin
if(rst)
counter<=0;
else
counter<=counter+1'b1;
if(counter<=127)
tmp<=8'b00000000;
else
tmp<=8'b11111111;
end
assign dout = tmp;
endmodule

AIM: To Write Verilog code to generate triangular waveform

module tria(clk,rst,dout);
input clk,rst;
output [7:0]dout;
reg [24:0]clkd;
reg [7:0]temp,counter;
assign dout[7:0]=temp[7:0];
always@(posedge clk)
begin
clkd=clkd+1'b1;
end
always@(posedge (clkd[10]))
begin
if(rst)
begin
counter<=0;
temp<=0;
end
else
counter<=counter+1'b1;
if(counter<=127 && rst==0)
temp<=temp+1'b1;
else
if(counter>=127&&rst==0)
temp<=temp-1'b1;
end
assign dout=temp;
endmodule

Design a Verilog code to perform addition, complement, bit wise AND, and
bit wise NOR operations on ALU

VERILOG PROGRAM:

module alu(input [1:0] a, input [1:0] b, input [1:0] s, output reg[1:0] c, output reg
c0);
always @ (s)
begin
case (s)
2’b00:{c0.c}=a+b;
2’b01:{c0.c}= ~a;
2’b10:{c0.c}= a&b;
2’b11:{c0.c}= ~(a|b);
endcase
end
endmodule

TESTBENCH

module alutb;
reg [1:0] a,b,s;
wire [1:0] c;
wire c0;
alu ug(a,b,s,c,c0);

initial
begin
a=1’b01,b=1’b11,s=2’b00;
#10 s=2’b01;
#10 s=2’b10;
#10 s=2’b11;
#10 $finish;
end
endmodule