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DSD Notes Unit 4 PDF
DSD Notes Unit 4 PDF
DSD Notes Unit 4 PDF
HALF ADDER
module half_add(I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2; /* Since O1 and O2 are outputs and they are written inside “always,”
they should be declared as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1 & I2; // statement 2./*The above two statements are signal-
assignment statements with 10 simulation screen units delay*/ /*Other behavioral
(sequential) statements can be added here*/
end
endmodule
IF Statement
IF is a sequential statement that appears inside always or initial in Verilog. It has
several formats, some of which are as follows:
Verilog
if (clk == 1’b1) // 1’b1 means 1-bit binary number of value 1.
temp = s1;
else
temp = s2;
if clk is high (1), the value of s1 is assigned to the variable temp. Otherwise, s2 is
assigned to the variable temp.
EXECUTION OF IF AS ELSE-IF
if (Expression1)
begin
statement1;
statement 2; .....
end
else if (expression2)
begin
statementi;
statementii; .....
end
else
begin
statement a;
statement b; ....
end
IMPLEMENTING ELSE-IF
if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;
2 bit comparator
Example
case sel
2’b00: temp = I1;
2’b01: temp = I2;
2’b10: temp = I3;
default: temp = I4;
endcase
If sel = 00, then temp = I1, if sel = 01, then temp = I2, if sel = 10, then temp = I3,
if sel = 11 (others or default), then temp = I4. All four test values have the same
priority; it means that if sel = 10, for example, then the third (VHDL) statement
(temp:= I3) is executed directly without checking the first and second expressions
(00 and 01).
FULL ADDER
module fulladd(cin,a,b,sum,cout);
input cin,a,b;
output sum,cout;
reg sum,cout;
always@(cin,a,b)
begin
case ({cin,a,b})
3'b000:{cout,sum}=2'b00;
3'b001:{cout,sum}=2'b01;
3'b010:{cout,sum}=2'b01;
3'b011:{cout,sum}=2'b10;
3'b100:{cout,sum}=2'b01;
3'b101:{cout,sum}=2'b10;
3'b110:{cout,sum}=2'b10;
3'b111:{cout,sum}=2'b11;
endcase
end
endmodule
8 to 1 multiplexer
module mux8(sel, I, y);
input [2:0] sel;
input [7:0] I;
output y;
reg y;
always @(sel ,I)
begin
case(sel)
3'b000:y=I[0];
3'b001:y=I[1];
3'b010:y=I[2];
3'b011:y=I[3];
3'b100:y=I[4];
3'b101:y=I[5];
3'b110:y=I[6];
3'b111:y=I[7];
default : y=1'b0;
endcase
end
endmodule
1 to 4 de multiplexer
module demux (sel, I, y);
input [1:0] sel;
input I;
output[3:0] y;
reg [3:0] y;
always@(I,sel)
begin
y=4'b0000;
case (sel)
2'b00:y[0]=I;
2'b01:y[1]=I;
2'b10:y[2]=I;
2'b11:y[3]=I;
default:y=4'b0000;
endcase
end
endmodule
For-Loop
for <lower index value> <upper index value> <step>
statements1; statement2; statement3; ….
end loop
Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1)
begin
result = result + 2**i;
end
end
statement1; statement2; ....
While-Loop
The general format of the While-Loop is:
while (condition)
Statement1; Statement2; …………
end
while (i < x)
begin
i = i + 1;
z = i*z;
end
Verilog repeat
In Verilog, the sequential statement repeat causes the execution of statements
between its begin and end to be repeated a fixed number of times; no condition is
allowed in repeat.
Verilog Repeat
repeat (32)
begin
#100 i = i + 1;
end
Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common use for
forever is to generate clocks in code-oriented test benches. The following code
describes a clock with a period of 20 screen time units:
initial
begin
clk = 1’b0;
forever #20 clk = ~clk;
end