1604
10, OCTOBER 1997
A 0.5-V MTCMOS/SIMOX Logic Gate
Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, and Toshiaki Tsuchiya
Abstract— This paper proposes a multithreshold CMOS
(MTCMOS) circuit that uses SIMOX process technology. This
MTCMOS/SIMOX circuit combines fully depleted low-threshold
CMOS logic gates and partially depleted high-threshold power-
switch transistors. The low-threshold CMOS gates have a
large noise margin for fluctuations in operating temperature in
addition to high-speed operation at the low supply voltage of
0.5 V. The high-threshold power-switch transistor in which the
body is connected to the gate through the reverse-diode makes it
possible to obtain large channel conductance in the active mode
without any increase of the leakage current in the sleep mode.
The effectiveness of the MTCMOS/SIMOX circuit is confirmed
by an evaluation of a gate-chain test element group (TEG) and
an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed
and fabricated with 0.25-m MTCMOS/SIMOX technology.
Index Terms— CMOS digital integrated circuits, CMOSFET
logic devices, low-voltage circuits, power control, silicon-on-
insulator technology.
I. INTRODUCTION
R EDUCING supply voltage without any sacrifice of speed
is the most effective way to lower power consumption in
battery-operated portable equipment. Toward this end, various
low-voltage circuits with low-threshold MOSFET’s have been
studied [1], [2]. We proposed multithreshold CMOS (MTC-
MOS) circuit technology [3] with low-threshold CMOS logic
gates and high-threshold power-switch transistors and showed
that it provides high-speed operation in the active mode and
low-power operation in the sleep mode. Using MTCMOS
technology, a 1-V digital signal processor (DSP) [4] for mobile
phone applications has recently been developed. Improvements
in MTCMOS device technology promise to lead to higher
operating frequencies.
However, higher frequencies will greatly increase power
consumption even if the supply voltage is 1 V. To reduce
power consumption, it is necessary to lower the supply voltage
below 1 V without sacrificing speed. Operation at a supply
voltage of around 0.5 V is also expected to open the way for
direct power supply by sunlight for portable communications
terminals because the 0.5 V is equal to the voltage generated by
one solar-battery cell. An ultra-low-voltage circuit consisting
of depletion-mode MOSFET’s that operates at a supply voltage
of 200 mV has been reported [5], but the circuit needs back-
gate bias, which is much larger than the supply voltage, to
increase the threshold voltage and to reduce the leakage current
in the sleep mode. The large applied voltage between the
Manuscript received August 30, 1996; revised April 7, 1997.
T. Douseki, S. Shigematsu, M. Harada, H. Inokawa, and T. Tsuchiya are
with the NTT System Electronics Laboratories, Atsugi-shi, Kanagawa, 243-
01, Japan.
J. Yamada is with the NTT Technology Department, Shinjuku-ku, Tokyo,
163-19, Japan.
Publisher Item Identifier S 0018-9200(97)06306-3.
0018–9200/97$10.00  1997 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.
gate and the substrate terminals is contradictory to scaling
theory [6], and it generates leakage current through the thin
gate oxide in the scaled-down MOSFET’s. In addition, the
leakage current of depletion-mode MOSFET’s is over one
order of magnitude larger than that of enhancement-mode low-
threshold MOSFET’s [1]–[3]. This causes the increase of the
power consumption in the active mode for large scale integra-
tors (LSI’s) [1]–[3], in which the power consumption due to
the leakage current contributes to total power consumption.
This paper describes ultra-low-voltage circuit technology
with enhancement-mode MOSFET’s and no large back-
gate bias. Section II describes a novel MTCMOS circuit
scheme [7] that uses SIMOX process technology [8]. This
MTCMOS/SIMOX circuit combines fully depleted low-
threshold CMOS logic gates and partially depleted variable
high-threshold MOSFET’s. In Section III, the effectiveness
of the circuit is confirmed by evaluating a gate-chain test
element group (TEG) and a 16-bit arithmetic logic unit
(ALU), which were designed and fabricated with 0.25-
m MTCMOS/SIMOX technology. A summary is given in
Section IV.
II. CIRCUIT SCHEME
The MTCMOS/SIMOX circuit scheme is shown in Fig. 1.
Combining fully depleted low-threshold CMOS logic gates
and a partially depleted high-threshold power-switch transistor
makes it possible to achieve both high-speed operation in the
active mode and low-power operation in the sleep mode at
an ultra-low supply voltage of 0.5 V. In what follows, the
characteristics of each part of the MTCMOS/SIMOX circuit
are described. For the low-threshold CMOS logic gates, the
fully depleted MOSFET’s can improve speed at ultra-low
supply voltage. This is because the circuits composed of
the fully depleted MOSFET’s are not affected by junction
capacitance, which increases significantly at a supply voltage
below 1 V in conventional bulk MOSFET’s whose bodies are
tied to the supply line. In addition, the current drivability of the
fully depleted MOSFET’s is better than that of conventional
bulk MOSFET’s. The subthreshold swing of the fully depleted
MOSFET is small and the threshold voltage can be reduced
without any increase in subthreshold current. For the power-
switch transistor, a partially depleted MOSFET whose body
is connected to the gate can reduce the threshold voltage
and increase the channel conductance in the active mode
without increasing the leakage current in the sleep mode. The
technique of connecting the body directly to the gate and
varying the threshold voltage at the operating mode is used
in ordinary DTMOS [9]. However, it cannot be applied to a
circuit with a supply voltage over 0.8 V. The static current
characteristics of the DTMOS are shown in Fig. 2(a). When
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 10, OCTOBER 1997 1605

Fig. 1. MTCMOS/SIMOX circuit scheme. Fig. 3. Characteristics of drain current in high-threshold MOSFET’s.

Fig. 4. Sleep-control circuit scheme.

one. In the active mode ( V), the drain current of the

variable-threshold MOSFET increases because the threshold
voltage is reduced due to the forward body biasing. At the
gate voltage of 0.5 V, the drain current, or in other words,
the channel conductance, of the variable-threshold MOSFET
(a) (b) is more than two times larger than that of the conventional
Fig. 2. Static current characteristics of high-threshold MOSFET’s: (a) DT- MOSFET.
MOS and (b) variable-threshold MOSFET. The sleep-control circuit using the variable-threshold MOS-
FET’s is shown in Fig. 4. The sleep-control circuit has to
drive the large high-threshold power-switch transistor while
the supply voltage is applied, the pn-diode between the source
keeping the leakage current small in the sleep mode. To
and body has forward bias. If the supply voltage is over
accelerate the switching of the internal sleep-control signal SL,
0.8 V, which is equal to the built-in potential of the diode,
the sleep-control circuit is made of multistage CMOS inverters
a large leakage current flows from the body to the gate. To
that combine low-threshold MOSFET’s and variable-threshold
apply the technique over a wide supply-voltage range, we
MOSFET’s. The variable-threshold MOSFET’s are alternately
use a variable-threshold MOSFET in which the reverse-biased
connected to the supply voltage lines VDD and GND so that
diode composed of a small low-threshold MOSFET is inserted
a large leakage current cannot flow through the circuit in the
between the body and the gate. Static current characteristics
sleep mode. The leakage current of one sleep-control circuit
of the variable-threshold MOSFET are shown in Fig. 2(b). For
consisting of a standard cell was measured. A microphotograph
supply voltages over 0.8 V, the reverse-biased diode clamps
of the measured sleep-control circuit is shown in Fig. 5(a). The
the forward bias of the pn-diode between the body and the
channel width of the power-switch transistor is 20 times larger
source, and gate leakage current is suppressed. The leakage
than that of the first-stage CMOS inverter. The characteristics
current is less than 0.1 A when the reverse-biased diode is
of the leakage current are shown in Fig. 5(b). The leakage
one-tenth the size of the high-threshold MOSFET with the
current of this circuit is about 10 pA in the sleep mode and
channel width of 10 m.
10 nA in the active mode. This means that the leakage current
The characteristics of the drain current of the high-threshold
of sub-100 K gate LSI’s with 100 sleep-control circuits would
MOSFET’s, the variable-threshold MOSFET/SIMOX, and
be about 1 nA in the sleep mode. In addition, the leakage
a conventional MOSFET/SIMOX with fixed body bias are
current in the active mode is 1 A, which is much smaller
shown in Fig. 3. The drain-source voltage was set at 50 mV
than that of the low-threshold CMOS logic gates.
so that the channel conductance, an important factor in the
power-switch transistor, could be evaluated. In the sleep mode
( V), the drain current of the variable-threshold III. EXPERIMENTS AND DISCUSSION
MOSFET is equal to that of the conventional MOSFET We designed and fabricated a gate-chain TEG and a 16-b
because its body bias is equal to that of the conventional ALU with 0.25- m MTCMOS/SIMOX technology to demon-
1606
(a)
(b)
Fig. 5. Measured leakage current of the sleep-control circuit: (a) micropho-
tograph of the measured sleep-control circuit and (b) characteristics of the
leakage current.
strate the effectiveness of the MTCMOS/SIMOX circuit. We
used a SIMOX wafer in which the thicknesses of the gate
oxide, the active silicon layer, and the buried oxide are 5,
50, and 100 nm, respectively. Variations of the thicknesses
of the active silicon layer and the buried oxide are less than
2 nm, and the standard deviation of threshold voltage in fully
depleted low-threshold MOSFET’s is within 10 mV [10].
Low and high threshold voltages were obtained by changing
the channel doping level. The dual-poly gate process was
used to ensure operation in the fully depleted mode at low-
threshold MOSFET’s and suppress short-channel effects. The
channel length of the low-threshold MOSFET’s was set to
the minimum value of 0.24 m for high-speed operation.
The channel length of the high-threshold MOSFET’s was set
to 0.32 m so that the variation of the threshold voltage
would be small and the effect of the variable threshold
voltage would be large at the supply voltage of 0.5 V.
The threshold voltage and the drain saturation current of
the low- and high-threshold MOSFET’s are summarized in
Table I.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 10, OCTOBER 1997
TABLE I
0.25-m MTCMOS/SIMOX DEVICE CHARACTERISTICS (VDD = 0:5 V)
A. Gate-Chain TEG
To evaluate the delay time and power consumption of the
logic gate, we designed and fabricated a gate-chain TEG
containing many logic gates for such things as the inverters,
NAND gates, and NOR gates. The TEG makes it possible to
evaluate the delay time and the power consumption in relation
to the number of the fanouts and the wire length. The TEG
comprises standard cells. The channel width of a standard
cell for the low-threshold CMOS logic gates is 3 m for the
nMOSFET and 6 m for the pMOSFET. The channel width of
a standard cell for the high-threshold power-switch transistors
is 20 times larger than that for the low-threshold CMOS logic
gates. The delay times in the 2-NAND logic gate are 80 ps at
the supply voltage of 1 V and 197 ps at 0.5 V in the unloaded
condition.
The delay-time of a fundamental logic gate, a two-input
NAND gate with three fanouts and wiring length of 1 mm, was
also evaluated. The dependence of the delay time in the funda-
mental logic gate with our MTCMOS/SIMOX circuit scheme
on the supply voltage is shown in Fig. 6. The delay-time
characteristics of conventional half- and quarter-micrometer
bulk MTCMOS circuits [4] are also shown for comparison.
The figure shows that only the MTCMOS/SIMOX circuit can
operate at a supply voltage of 0.4 V without any increase in
the delay time. At the supply voltage of 1 V, the delay time is
273 ps, which is less than half that of the quarter-micrometer
bulk MTCMOS circuit. At the supply voltage of 0.5 V, the
delay time is 710 ps, which is less than 40% of that of the half-
micrometer bulk MTCMOS circuit at 1 V. To analyze the main
factors in the delay-time reduction, we calculated the delay-
time components of each MTCMOS circuit from the measured
delay-time data for the fanouts and the wiring length. The
results are shown in Fig. 7. The largest reduction factor is the
wiring delay-time related to the large current drivability of the
SIMOX device. The second is the intrinsic delay-time related
to the junction capacitance. These results becomes more clear
for low supply voltage below 1 V.
The influence of the power-switch transistor on the delay
time is shown in Fig. 8. Since our power-switch transistor with
the variable-threshold MOSFET/SIMOX has large channel
conductance and small threshold-voltage variation [10], the
delay time and variation are less than those of a conventional
MOSFET/SIMOX with fixed-body bias. At the supply voltage
of 0.4 V, the delay time with our power-switch transistor
scheme is 1125 ps. This is 10% shorter and its variation 30%
smaller than that with the conventional power-switch transistor
scheme.
The total performance of the MTCMOS circuits were cal-
culated from the measured delay-time and power consumption
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 10, OCTOBER 1997
Fig. 6. Delay-time characteristics of fundamental logic gates in the MTC-
MOS circuit scheme.
(a) (b)
Fig. 7. Delay-time components of fundamental logic gates: (a)
0:5 V and (b) VDD = 1 V.
of the fundamental logic gates. The total power-consumption
per logic gate was obtained by
where the first term, , is the static power consumption and
the second term is the dynamic power consumption. Specif-
ically, is the dynamic power consumption per operating
frequency. is the activation rate and is the circuit stages
of the critical path in an LSI. The total performance of the
0.25- m MTCMOS circuits is shown in Fig. 9. The static
and the dynamic power consumption of our circuit in the
active mode are 0.04 W/gate and 0.05 W/MHz/gate at
the supply voltage of 0.5 V [6]. We assumed an activation
rate of 10% and 30 circuit stages in
the critical path. The power consumption of our proposed
circuit is about two orders of magnitude lower than that of
a conventional 3.3-V half-micrometer CMOS circuit. For the
same design rule comparison, it is one sixth lower than that
of 1-V bulk/MTCMOS circuits, while almost the same delay
time is maintained.
To verify the effectiveness of the MTCMOS/SIMOX circuit
in an LSI, an 8-K gates 16-b ALU, which has an activation rate
of based on a fundamental logic gate, was designed
and fabricated. A microphotograph of the ALU is shown in
Fig. 10. The chip is 4 4 mm and the core is 1.7 1.7 mm .
The fully depleted low-threshold CMOS logic gates are located
mainly in the core and the variable-threshold power-switch
1607
(a)
(b)
Fig. 8. Comparison of power-switch transistor schemes: (a) variable-
V DD = threshold MOSFET/ SIMOX and (b) conventional MOSFET/SIMOX with
fixed-body bias.
(1)
Fig. 9. Total performance of fundamental logic gates.
transistors with sleep control circuits are on both sides. These
areas are small and are less than 10% of the total core area. In
the variable-threshold power-switch transistors, the last-stage
transistor connected between the supply line and the virtual
supply line occupies most of the area. So, the area penalty
due to the reverse-biased diode connected between gate and
body terminals is very small. The Schmoo plots for evaluating
the maximum operating frequency are shown in Fig. 11. The
maximum operating frequency is at least 40 MHz at the supply
voltage of 0.5 V. The power consumption is 0.35 mW. The
power consumption in the sleep mode can be suppressed to
less than 5 nW. The measured waveforms of the sleep-control
signal are shown in Fig. 12. The waveform of the output of the
sleep-control circuit is shown in Fig. 12(a). Symmetric output
waveforms with the same rise and fall time were obtained. The
1608
Fig. 10. Microphotograph of the test chip.
Fig. 11. Schmoo plots of the operating clock rate.
delay time of the sleep-control circuit is 20 ns at the supply
voltage of 0.5 V. The response of the virtual supply-voltage
line is shown in Fig. 12(b). The turn-on time, which is the
transition time from the sleep to the active mode, is 0.4 s and
the turnoff time, which is the opposite, is 8 s. The features
of the 16-b ALU are summarized in Table II.
IV. CONCLUSION
A novel multithreshold CMOS circuit that employs SIMOX
technology has been developed. Combining fully depleted
low-threshold CMOS logic gates and a partially depleted
high-threshold power-switch transistor makes it possible to
achieve both high-speed operation in the active mode and
low-power operation in the sleep mode at an ultra-low supply
voltage below 0.5 V. To demonstrate the effectiveness of the
MTCMOS/SIMOX circuit, we designed and fabricated a gate-
chain TEG and a 16-b ALU with 0.25- m MTCMOS/SIMOX
technology. It was shown that the 2-NAND logic gate has
a delay time of 197 ps in the unloaded condition and the
fundamental logic gate has a delay time of 710 ps at the
supply voltage of 0.5 V. The power consumption of the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 10, OCTOBER 1997
(a)
(b)
Fig. 12. Waveforms of the sleep-control signal: (a) waveforms of the internal
sleep-control signal and (b) response of the virtual supply-voltage line.
TABLE II
TEST CHIP FEATURES
MTCMOS/SIMOX circuit is about two orders of magnitude
lower than that of the conventional 3.3-V half-micrometer
bulk CMOS circuit. A 40-MHz, 0.35-mW, 16-b ALU with
a power consumption of less than 5 nW in the sleep mode
was successfully obtained at the supply voltage of 0.5 V.
ACKNOWLEDGMENT
The authors would like to thank S. Horiguchi, T. Sakai, K.
Izumi, H. Yoshimura, and H. Fukuda for their encouragement.
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