Professional Documents
Culture Documents
Ug1075 Zynq Ultrascale PKG Pinout PDF
Ug1075 Zynq Ultrascale PKG Pinout PDF
Packaging Overview
Virtex® UltraScale+™ devices provide the highest performance and integration capabilities
in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as
well as the highest on-chip memory density. As the industry's most capable FPGA family,
the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and
data center and fully integrated radar/early-warning systems.
Virtex UltraScale devices provide the greatest performance and integration at 20 nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at
the 20 nm process node, this family is ideal for applications including 400G networking,
large scale ASIC prototyping, and emulation.
Zynq® UltraScale+ devices provide 64-bit processor scalability while combining real-time
control with soft and hard engines for graphics, video, waveform, and packet processing.
Integrating an Arm®-based system for advanced analytics and on-chip programmable
logic for task acceleration creates unlimited possibilities for applications including 5G
Wireless, next generation ADAS, and Industrial Internet-of-Things.
This user guide is part of the Zynq UltraScale+ MPSoC documentation suite.
IMPORTANT: All standard packages are lead-free (signified by an additional V in the package name).
All devices supported in a particular package are footprint compatible. Each device is split into I/O
banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture SelectIO
Resources User Guide (UG571) [Ref 6].
The flip-chip assembly materials for the Zynq UltraScale+ devices are manufactured using
ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than
0.002 alpha-particles per square centimeter per hour.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
• All package and die components, including flip-chip solder bumps, are lead-free.
• Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package.
• VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to
VCCAUX at the board level.
• Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
VCCINT_IO must be connected to VCCBRAM (depending on the device speed grade
and voltage settings) at the board level.
• Groups of gigabit serial transceiver (GT) power pins are separated by column for each
column of GT Quads.
• Standard HP I/O banks each have a total of 52 SelectIO™ pins, optionally configurable
as (up to) 24 differential pairs.
• Standard HD I/O banks each have a total of 24 SelectIO pins, optionally configurable as
(up to) 12 differential pairs.
• Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.
• Four differential clock pin pairs per bank consist of a single type of global clock (GC or
HDGC) input.
• Four memory byte groups per HP I/O bank are each separated into an upper and a
lower memory byte group.
• Multiple PL configuration pins are removed.
• A POR_OVERRIDE pin is used to override the default power-on-reset delay. See
Table 1-4.
Device/Package Combinations
Table 1-1 shows the size and BGA pitch of the Zynq UltraScale+ device packages. All
packages are available with eutectic BGA balls. For these packages, the Pb-free signifier in
the package name is a Q.
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package
Device Package PS-GTR Channels GTH Channels GTY Channels
XCZU2CG 4 0 0
XCZU2EG 4 0 0
XCZU3CG 4 0 0
SBVA484
XCZU3EG 4 0 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0
XQZU3EG SFRA484 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
XCZU3CG 4 0 0
SFVA625
XCZU3EG 4 0 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
XCZU3CG 4 0 0
XCZU3EG 4 0 0
XCZU4CG 4 4 0
XCZU4EG 4 4 0
XCZU4EV 4 4 0
SFVC784
XCZU5CG 4 4 0
XCZU5EG 4 4 0
XCZU5EV 4 4 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0
XAZU4EV 4 4 0
XAZU5EV 4 4 0
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont’d)
Device Package PS-GTR Channels GTH Channels GTY Channels
XQZU21DR 4 0 0
SFRC784
XQZU5EV 4 4 0
XCZU4CG 4 16 0
XCZU4EG 4 16 0
XCZU4EV 4 16 0
XCZU5CG 4 16 0
XCZU5EG 4 16 0
FBVB900
XCZU5EV 4 16 0
XCZU7CG 4 16 0
XCZU7EG 4 16 0
XCZU7EV 4 16 0
XAZU7EV 4 16 0
XQZU5EV 4 16 0
FFRB900
XQZU7EV 4 16 0
XCZU6CG 4 16 0
XCZU6EG 4 16 0
XCZU9CG FFVC900 4 16 0
XCZU9EG 4 16 0
XCZU15EG 4 16 0
XQZU9EG 4 16 0
FFRC900
XQZU15EG 4 16 0
XCZU6CG 4 24 0
XCZU6EG 4 24 0
XCZU9CG FFVB1156 4 24 0
XCZU9EG 4 24 0
XCZU15EG 4 24 0
XQZU9EG 4 24 0
FFRB1156
XQZU15EG 4 24 0
XCZU7CG 4 20 0
XCZU7EG 4 20 0
FFVC1156
XCZU7EV 4 20 0
XCZU11EG 4 20 0
XQZU7EV 4 20 0
FFRC1156
XQZU11EG 4 20 0
XCZU21DR FFVD1156 4 0 16
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont’d)
Device Package PS-GTR Channels GTH Channels GTY Channels
XQZU21DR FFRD1156 4 0 16
XCZU25DR 4 0 8
XCZU27DR FFVE1156 4 0 8
XCZU28DR 4 0 8
XQZU28DR FFRE1156 4 0 8
XCZU25DR 4 0 8
XCZU27DR FSVE1156 4 0 8
XCZU28DR 4 0 8
XCZU11EG 4 16 0
XCZU17EG FFVB1517 4 16 0
XCZU19EG 4 16 0
XQZU19EG FFRB1517 4 16 0
XCZU7CG 4 24 0
XCZU7EG 4 24 0
XCZU7EV FFVF1517 4 24 0
XCZU11EG 4 32 0
XAZU11EG 4 32 0
XCZU25DR 4 0 8
XCZU27DR FFVG1517 4 0 16
XCZU28DR 4 0 16
XQZU28DR FFRG1517 4 0 16
XCZU25DR 4 0 8
XCZU27DR FSVG1517 4 0 16
XCZU28DR 4 0 16
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont’d)
Device Package PS-GTR Channels GTH Channels GTY Channels
XCZU11EG 4 32 16
XCZU17EG FFVC1760 4 32 16
XCZU19EG 4 32 16
XQZU11EG 4 32 16
FFRC1760
XQZU19EG 4 32 16
XCZU17EG 4 44 28
FFVD1760
XCZU19EG 4 44 28
XCZU29DR 4 0 16
FFVF1760
XCZU39DR 4 0 16
XQZU29DR FFRF1760 4 0 16
XCZU29DR 4 0 16
FSVF1760
XCZU39DR 4 0 16
XCZU17EG 4 44 0
FFVE1924
XCZU19EG 4 44 0
Notes:
1. The maximum user I/O numbers do not include the GT serial transceiver pins or the PUDC_B and POR_OVERRIDE
pins used for configuration.
Pin Definitions
Table 1-4 lists the pin definitions.
Multi-
I2C_SCLK Bidirectional
function
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used
for I2C access until after configuration.
Multi-
I2C_SDA Bidirectional
function
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used
for I2C access until after configuration.
Multi-
SMBALERT Bidirectional
function IMPORTANT: By default, the PMBus is active prior
to configuration. Only use as a multi-functional
I/O pin in designs that can tolerated this pin being
driven prior to configuration.
Notes:
1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6] for more information on the
VRP pins.
2. V CCO pins in unbonded banks must be connected to the V CCO for that bank (for package migration). Do NOT connect
unbonded V CCO pins to different supplies. Without a package migration requirement, V CCO pins in unbonded banks can be
tied to a common supply (V CCO or GND).
3. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 13] for the default connections required to support
on-chip monitoring.
4. L (left), R (right), N (north), and S (south) signify the GT transceiver quad power supply groups.
IMPORTANT: Footprint compatibility does not necessarily imply that all pins will function in the same
manner for different devices in a package. For limitations and guidelines on designing for footprint
compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packages
section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 14].
Table 1-5 shows the footprint compatible devices available for each package. See the
Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] for specific package letter code options.
All packages are available with eutectic BGA balls. For these packages, the device type is XQ
and the Pb-free signifier in the package name is a Q.
Many Zynq UltraScale+ devices that are footprint compatible in a package have different
I/O bank and transceiver quad numbers connected to the same package pins. Due to these
differences, when migrating between devices in a specific package, the type of bank (HD vs.
HP) or quad (PS-GTR, GTH, or GTY), whether a bank is connected or NC at the package pins,
and where the bank or quad is located on the die must be taken into consideration.
Table 1-6 and Table 1-7 show how the banks and transceiver quads are numbered between
devices in each package.
For all grouped-together footprint-compatible packages, the bank and quad numbers in
the same column (indicated by the letters A through Z) for each device are connected to the
same package pins. For example, in the FFVB1517 packages, bank 88 for the XCZU11 is
connected to the same pins as bank 90 for the XCZU17 and XCZU19.
A limited number of HP I/O banks have fewer than 52 SelectIO pins. For a visual
representation of all of this information, see the Die Level Bank Numbering Overview
section.
XCZU2
64 65 66 26 25, 24, 44
XAZU2
SFVA625
XCZU3
64 65 66 26 25, 24, 44
XAZU3
XCZU2
64 65 66 25 26 24 44
XAZU2
XCZU3
64 65 66 25 26 24 44
XAZU3
SFVC784
XCZU4
64 65 66 45 46 44 43 63
XAZU4
XCZU5
64 65 66 45 46 44 43 63
XAZU5
XQZU3 64 65 66 25 26 24 44
SFRC784
XQZU5 64 65 66 45 46 44 43 63
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont’d)
Package to Device I/O Mapping(1)
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
XCZU6 64 65 66 48 47 50, 49, 44, 67
FFVC900 XCZU9 64 65 66 48 47 50, 49, 44, 67
XCZU15 64 65 66 48 47 50, 49, 44, 67
XQZU9 64 65 66 48 47 50, 49, 44, 67
FFRC900
XQZU15 64 65 66 48 47 50, 49, 44, 67
XCZU6 44 64 65 66 67 47 48 49 50
FFVB1156 XCZU9 44 64 65 66 67 47 48 49 50
XCZU15 44 64 65 66 67 47 48 49 50
XQZU9 44 64 65 66 67 47 48 49 50
FFRB1156
XQZU15 44 64 65 66 67 47 48 49 50
FFVE1156 71, 70, 69, 68, 67, 64, 91, 90, 87,
XCZU27 65 66 88 89
84
FSVE1156
71, 70, 69, 68, 67, 64, 91, 90, 87,
XCZU28 65 66 88 89
84
71, 70, 69, 68, 67, 64, 91, 90, 87,
FFRE1156 XQZU28 65 66 88 89
84
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont’d)
Package to Device I/O Mapping(1)
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
XCZU11 65 64 66 88 89 90 71 70 69 68 67 91
FFVB1517 XCZU17 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
XCZU19 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
FFRB1517 XQZU19 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
XCZU7 65 66 64 63 87 88 67 68 28 27 48, 47
FFVF1517 XCZU11 65 66 67 64 88 89 70 71 69 68 91, 90
XAZU11 65 66 67 64 88 89 70 71 69 68 91, 90
XCZU25 84 64 65 66 87 67 68 69 89, 88
FFVG1517
XCZU27 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FSVG1517
XCZU28 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FFRG1517 XQZU28 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont’d)
Package to Device I/O Mapping(1)
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
XCZU11 65 64 66 67 88 89 90 91 71 70 69 68
FFVC1760 XCZU17 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XCZU19 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XQZU11 65 64 66 67 88 89 90 91 71 70 69 68
FFRC1760
XQZU19 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XCZU17 65 64 66 67 90 91 93 94 74 73 72 71 70 69 68
FFVE1924
XCZU19 65 64 66 67 90 91 93 94 74 73 72 71 70 69 68
Notes:
1. An alphabetical designator, A through Z, is assigned to every bank in a package. I/Os from banks with the same designator are bonded out to the same pins in
that package. For example, in the FFVF1517 package, the E designator is assigned to bank 67 for the XCZU11 and bank 64 for the XCZU7. These banks are bonded
to the same pins, regardless of where they appear on the XCZU11 and XCZU7 device.
2. Bank 66 is partially bonded out in the SBVA484 package (see Figure 1-3).
For each grouped set of footprint compatible packages listed in Table 1-7, there is a row detailing the power supply group for
each Quad. These groups are labeled according to the regions for the transceiver power supply pins, as listed in the ASCII
Pinout Files linked from Chapter 3, Package Files. For a visual representation of all of this information, see the Die Level Bank
Numbering Overview section.
XCZU2
XAZU2
SFVA625
XCZU3
XAZU3
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont’d)
Package to Die Transceiver Mapping(1)
Package Device Unbonded Quads
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
Power Supply Group R
XCZU4 223 224 225 226
XCZU5 223 224 225 226
FBVB900
XCZU7 224 225 226 227 228, 223
XAZU7 224 225 226 227 228, 223
XQZU5 223 224 225 226
FFRB900
XQZU7 224 225 226 227 228, 223
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont’d)
Package to Die Transceiver Mapping(1)
Package Device Unbonded Quads
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
Power Supply Group L
XCZU25 128 129 127
FFVE1156
XCZU27 128 129 131, 130, 127
FSVE1156
XCZU28 128 129 131, 130, 127
FFRE1156 XCZU28 128 129 131, 130, 127
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont’d)
Package to Die Transceiver Mapping(1)
Package Device Unbonded Quads
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
Power Supply Group RS RN L
XCZU11 224 225 226 227 228 229 230 231 128 129 130 131 127
FFVC1760 XCZU17 224 225 226 227 228 229 230 231 128 129 130 131 127
XCZU19 224 225 226 227 228 229 230 231 128 129 130 131 134, 133, 132, 127, 234, 233, 232
XQZU11 224 225 226 227 228 229 230 231 128 129 130 131 127
FFRC1760
XQZU19 224 225 226 227 228 229 230 231 128 129 130 131 134, 133, 132, 127, 234, 233, 232
Notes:
1. An alphabetical designator, A through Z, is assigned to every Quad in a package. Transceivers from Quads with the same designator are bonded out to the same pins in
that package. For example, in the FFVF1517 package, the E designator is assigned to Quad 228 for the XCZU11 and Quad 227 for the XCZU7. These Quads are bonded to
the same pins, regardless of where they appear on the XCZU11 and XCZU7 device.
GTH/GTY Columns
• One GT Quad = Four transceivers = Four GTHE4 or GTYE4 primitives.
• Not all GT Quads are bonded out in every package.
• Also shown are quads labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
• The XY coordinates shown in each quad correspond to the transceiver channel number
found in the pin names for that quad, as shown in Figure 1-2.
• An alphabetic designator is shown in each quad. Each letter corresponds to the
columns in Table 1-6 and Table 1-7.
• The power supply group is shown in brackets [ ] for each quad.
I/O Banks
• Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential
(24 differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
• A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are
labeled as partial.
• Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12
differential pairs) or single-ended I/Os.
• Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
• Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
• Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
• An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table 1-6 and Table 1-7.
Clocking
• Each bank has four pairs of global clock (GC or HDGC) inputs for four differential or
four single-ended clock inputs. Single-ended clock inputs should be connected to the
P-side of the differential pair.
• Clock signals are distributed through global buffers driving routing and distribution
networks to reach any clock region, I/O, or GT.
• Global clock inputs can connect to an MMCM and two PLLs within the horizontally
adjacent CMT.
Device Diagrams
Figure 1-1 shows an example diagram with a brief explanation for each component.
X-Ref Target - Figure 1-1
GTY Quad 131 GTH Quad 231 X0Y31 →MGTH[TX or RX][P or N]3_231
PCIE4 HP I/O Bank 71 HD I/O Bank 94 X0Y30 →MGTH[TX or RX][P or N]2_231
X0Y16-X0Y19 X0Y28-X0Y31
X0Y4 R Q X0Y29 →MGTH[TX or RX][P or N]1_231
M [L] H [RN] X0Y28 →MGTH[TX or RX][P or N]0_231
GTY Quad 130 GTH Quad 230 X0Y27 →MGTH[TX or RX][P or N]3_230
CMAC HP I/O Bank 70 HD I/O Bank 93 X0Y26 →MGTH[TX or RX][P or N]2_230
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 S P X0Y25 →MGTH[TX or RX][P or N]1_230
L [L] G [RN] X0Y24 →MGTH[TX or RX][P or N]0_230
GTY Quad 129 GTH Quad 229 X0Y23 →MGTH[TX or RX][P or N]3_229
ILKN HP I/O Bank 69 HD I/O Bank 91 X0Y22 →MGTH[TX or RX][P or N]2_229
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 T O X0Y21 →MGTH[TX or RX][P or N]1_229
K [L] (RCAL) F [RN] X0Y20 →MGTH[TX or RX][P or N]0_229
GTY Quad 128 GTH Quad 228
PCIE4 HP I/O Bank 68 HD I/O Bank 90
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 U N
J [L] E [RN]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 PCIE4
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 F X1Y1 Transceiver Power
D [RS]
Supply Group
GTH Quad 226
HP I/O Bank 66 SYSMON
PS GTR 505 PS MIO 502 X0Y8-X0Y11
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration X0Y4-X0Y7
C
B [RS]
PCIE4 GTH Quad 224 X0Y3 →MGTH[TX or RX][P or N]3_224
HP I/O Bank 64 X0Y2 →MGTH[TX or RX][P or N]2_224
PS CONFIG 503 PS MIO 500 X1Y0 X0Y0-X0Y3
D (tandem)
X0Y1 →MGTH[TX or RX][P or N]1_224
A [RS] X0Y0 →MGTH[TX or RX][P or N]0_224
Figure 1-2 through Figure 1-41 show a die view of each device followed by a view with
respect to each available package. The available resources by device and package are
detailed in the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] or Zynq UltraScale+
RFSoC Overview (DS889) [Ref 2].
SYSMON
PS GTR 505 PS MIO 502 HD I/O Bank 26 HP I/O Bank 66
Configuration
PS CONFIG 503 PS MIO 500 HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
X15118-111316
Bank Diagram by Package for XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3
X-Ref Target - Figure 1-3
PS CONFIG 503 PS MIO 500 HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
X15119-071417
Figure 1-3: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SBVA484 Package
IMPORTANT: For the devices in the SBVA484 package shown in Figure 1-3, the HP I/Os in bank 66 are
powered by VCCO_65.
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 24 HD I/O Bank 44
B
X15120-111316
Figure 1-4: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SFVA625 Package
X15121-111316
Figure 1-5: XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Banks in SFVC784 Package
X15122-111316
Bank Diagram by Package for XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5
X-Ref Target - Figure 1-7
X15124-111316
Figure 1-7: XCZU4, XAZU4, XCZU5, and XAZU5 Banks in SFVC784 Package and
XQZU5 Banks in SFRC784 Package
X15125-111316
Figure 1-10: XCZU7 and XAZU7 Banks in FBVB900 Package and XQZU7 Banks in FFRB900
Package
Figure 1-11: XCZU7 Banks in FFVC1156 Package and XQZU7 Banks in FFRC1156 Package
X-Ref Target - Figure 1-12
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66
Configuration
X15129-071417
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration
C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 44
B
X15130-071417
Figure 1-14: XCZU6 and XCZU9 Banks in FFVC900 Package and XQZU9 in FFRC900 Package
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration
C
X15131-100118
Figure 1-15: XCZU6 and XCZU9 Banks in FFVB1156 Package and XQZU9 in FFRB1156 Package
PCIE4
GTH Quad 224
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X1Y0
(tandem) X0Y0-X0Y3
X15132-121517
Figure 1-17: XCZU11 Banks in FFVC1156 Package and XQZU11 Banks in FFRC1156 Package
GTY Quad 130 CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15 X0Y1 U P X0Y24-X0Y27
GTY Quad 128 PCIE4 HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
X0Y4-X0Y7 X0Y2 W N X0Y16-X0Y19
Figure 1-20: XCZU11 Banks in FFVC1760 Package and XQZU11 Banks in FFRC1760 Package
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66
Configuration
X15137-111218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration
C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 44
B
X15138-111218
Figure 1-22: XCZU15 Banks in FFVC900 Package and XQZU15 Banks in FFRC900 Package
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration
C
X15139-111218
Figure 1-23: XCZU15 Banks in FFVB1156 Package and XQZU15 Banks in FFRB1156 Package
PCIE4
GTH Quad 224
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X1Y0
(tandem) X0Y0-X0Y3
X15140-071417
GTY Quad 133 ILKN HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
X0Y24-X0Y27 X0Y2 R P X0Y36-X0Y39
GTY Quad 132 CMAC HP I/O Bank 72 ILKN GTH Quad 232
X0Y20-X0Y23 X0Y2 S X1Y1 X0Y32-X0Y35
GTY Quad 131 PCIE4 HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
X0Y16-X0Y19 X0Y3 T O X0Y28-X0Y31
GTY Quad 130 CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15 X0Y1 U N X0Y24-X0Y27
GTY Quad 128 PCIE4 HP I/O Bank 68 PCIE4 GTH Quad 228
X0Y4-X0Y7 X0Y2 W X1Y2 X0Y16-X0Y19
SYSMON
PS GTR 505 PS MIO 502 SD-FEC HP I/O Bank 66
Configuration
X19543-101518
HP I/O Bank 65
PS DDR 504 PS MIO 501 SD-FEC Configuration
C
X19545-101518
Figure 1-30: XCZU21DR Banks in FFVD1156 Package and XQZU21DR Banks in FFRD1156 Package
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19546-032218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19547-032218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
X19548-032218
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19549-032218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19550-032218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
X19551-032218
SYSMON
PS GTR 505 PS MIO 502 SD-FEC HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 SD-FEC HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 SD-FEC HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19552-101518
HP I/O Bank 65
PS DDR 504 PS MIO 501 SD-FEC Configuration ADC Bank 225
C
PS CONFIG 503 PS MIO 500 SD-FEC HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19553-101518
HP I/O Bank 65
PS DDR 504 PS MIO 501 SD-FEC Configuration ADC Bank 225
C
X19554-101518
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19555-032218
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
X19556-032218
Figure 1-41: XCZU29DR and XCZU39DR Banks in FFVF1760 and FSVF1760 Packages and
XQZU29DR Banks in FFRF1760 Package
IMPORTANT: SBVA484 and SFVA625 packages only support 32-bit data buses for the PS DDR
controller. The Zynq UltraScale+ device DDR subsystem can only be configured for 32-bit or 32-bit plus
ECC DDR3/DDR4/LPDDR4 designs when using these packages.
DDR3/3L Guidelines
DDR3/3L Pin Rules
The DDR3/3L pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in a 64-bit interface without
ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins
can be left unconnected.
• Connect the PS_DDR_ZQ pin to GND using a 240Ω resistor. There should be separate
240Ω resistors at the MPSoC or RFSoC and at the DRAM.
Pin Name DDR3/3L 64-bit DDR3/3L 64-bit DDR3/3L 32-bit DDR3/3L 32-bit
1Rank 2Rank 1Rank 2Rank
PS_DDR_DM4 to Connect DM4 to Connect DM4 to Can be left Can be left
PS_DDR_DM7 PS_DDR_DM4, DM5 PS_DDR_DM4, DM5 unconnected. unconnected.
to PS_DDR_DM5, to PS_DDR_DM5,
and so on. and so on.
PS_DDR_DM8 DM8, can be left DM8, can be left DM4, can be left DM4, can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to
PS_DDR_DQ31 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1
to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1,
and so on. and so on. and so on. and so on.
PS_DDR_DQ32 to Connect DQ32 to Connect DQ32 to Can be left Can be left
PS_DDR_DQ63 PS_DDR_DQ32, PS_DDR_DQ32, unconnected. unconnected.
DQ33 to DQ33 to
PS_DDR_DQ33, and PS_DDR_DQ33, and
so on. so on.
PS_DDR_DQ64 DQ64 (ECC_bit[0]), DQ64 (ECC_bit[0]), DQ32 (ECC_bit[0]), DQ32 (ECC_bit[0]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ65 DQ65 (ECC_bit[1]), DQ65 (ECC_bit[1]), DQ33 (ECC_bit[1]), DQ33 (ECC_bit[1]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ66 DQ66 (ECC_bit[2]), DQ66 (ECC_bit[2]), DQ34 (ECC_bit[2]), DQ34 (ECC_bit[2]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ67 DQ67 (ECC_bit[3]), DQ67 (ECC_bit[3]), DQ35 (ECC_bit[3]), DQ35 (ECC_bit[3]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ68 DQ68 (ECC_bit[4]), DQ68 (ECC_bit[4]), DQ36 (ECC_bit[4]), DQ36 (ECC_bit[4]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ69 DQ69 (ECC_bit[5]), DQ69 (ECC_bit[5]), DQ37 (ECC_bit[5]), DQ37 (ECC_bit[5]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ70 DQ70 (ECC_bit[6]), DQ70 (ECC_bit[6]), DQ38 (ECC_bit[6]), DQ38 (ECC_bit[6]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
Pin Name DDR3/3L 64-bit DDR3/3L 64-bit DDR3/3L 32-bit DDR3/3L 32-bit
1Rank 2Rank 1Rank 2Rank
PS_DDR_DQ71 DQ71 (ECC_bit[7]), DQ71 (ECC_bit[7]), DQ39 (ECC_bit[7]), DQ39 (ECC_bit[7]),
can be left can be left can be left can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQS_N0 to Connect DQS#0 to Connect DQS#0 to Connect DQS#0 to Connect DQS#0 to
PS_DDR_DQS_N3 PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0,
DQS#1 to DQS#1 to DQS#1 to DQS#1 to
PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1,
and so on. and so on. and so on. and so on.
PS_DDR_DQS_N4 to Connect DQS#4 to Connect DQS#4 to Can be left Can be left
PS_DDR_DQS_N7 PS_DDR_DQS_N4, PS_DDR_DQS_N4, unconnected. unconnected.
DQS#5 to DQS#5 to
PS_DDR_DQS_N5, PS_DDR_DQS_N5,
and so on. and so on.
PS_DDR_DQS_N8 DQS#8, can be left DQS#8, can be left DQS#4, can be left DQS#4, can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQS_P0 to Connect DQS0 to Connect DQS0 to Connect DQS0 to Connect DQS0 to
PS_DDR_DQS_P3 PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0,
DQS1 to DQS1 to DQS1 to DQS1 to
PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1,
and so on. and so on. and so on. and so on.
PS_DDR_DQS_P4 to Connect DQS4 to Connect DQS4 to Can be left Can be left
PS_DDR_DQS_P7 PS_DDR_DQS_P4, PS_DDR_DQS_P4, unconnected. unconnected.
DQS5 to DQS5 to
PS_DDR_DQS_P5, PS_DDR_DQS_P5,
and so on. and so on.
PS_DDR_DQS_P8 DQS8, can be left DQS8, can be left DQS4, can be left DQS4, can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_ODT0 ODT ODT[0] ODT ODT[0]
PS_DDR_ODT1 Can be left ODT[1] Can be left ODT[1]
unconnected. unconnected.
PS_DDR_PARITY Par_In for RDIMMs. Par_In for RDIMMs. Par_In for RDIMMs. Par_In for RDIMMs.
Can be left Can be left Can be left Can be left
unconnected for unconnected for unconnected for unconnected for
components and components and components and components and
UDIMMs. UDIMMs. UDIMMs. UDIMMs.
PS_DDR_RAM_RST_N RESET# RESET# RESET# RESET#
PS_DDR_ZQ Connect a 240Ω Connect a 240Ω Connect a 240Ω Connect a 240Ω
resistor to GND. (2) resistor to GND.(2) resistor to GND.(2) resistor to GND.(2)
Notes:
1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
2. There should be separate 240Ω resistors at the FPGA and at the DRAM.
DDR4 Guidelines
DDR4 Pin Rules
The DDR4 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in a 64-bit interface without
ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins
can be left unconnected.
• For component interfaces, the PS_DDR_ALERT_N pin must be connected with fly-by
routing to a 50Ω pull-up resistor to VCC at the last DRAM component. If unused, the
PS_DDR_ALERT_N for the FPGA and the DRAMs must be connected to a 4.7KΩ pull-up
resistor to VDDQ/VCCO_DDR. The PS_DDR_ALERT_N can be left floating at the DRAM.
• Connect the PS_DDR_ZQ pin to GND using a 240Ω resistor. There should be separate
240Ω resistors at the FPGA and at the DRAM.
• Component interfaces with the same component for all components in the interface.
The x16 components have a different number of bank groups than the x8 components.
For example, create a 72-bit wide component interface by using nine x8 components or
five x16 components, where half of one component is not used. Creating four x16
components and one x8 component is not permissible.
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
VCCO_PSDDR(1) Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V.
PS_DDR_A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to
PS_DDR_A16 PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to
PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so
on. on. on. on. on. on.
WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared
with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14,
CAS_N can be CAS_N can be CAS_N can be CAS_N can be CAS_N can be CAS_N can be
shared with shared with shared with shared with shared with shared with
PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and
RAS_N can be RAS_N can be RAS_N can be RAS_N can be RAS_N can be RAS_N can be
shared with shared with shared with shared with shared with shared with
PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16.
PS_DDR_A17 Can be left Can be left Can be left Can be left Can be left Can be left
unconnected unconnected unconnected unconnected unconnected unconnected
PS_DDR_ACT_N ACT_n ACT_n ACT_n ACT_n ACT_n ACT_n
PS_DDR_ALERT_N ALERT_n ALERT_n ALERT_n ALERT_n ALERT_n ALERT_n
PS_DDR_BA0 BA[0] BA[0] BA[0] BA[0] BA[0] BA[0]
PS_DDR_BA1 BA[1] BA[1] BA[1] BA[1] BA[1] BA[1]
PS_DDR_BG0 BG[0] BG[0] BG[0] BG[0] BG[0] BG[0]
PS_DDR_BG1 (2) BG[1] BG[1] BG[1] BG[1] BG[1] BG[1]
PS_DDR_CK_N0 CK_c[0] CK_c[0] CK_c[0] CK_c[0] CK_c[0] CK_c[0]
PS_DDR_CK_N1 Can be left CK_c[1] Can be left CK_c[1] Can be left CK_c[1]
unconnected. unconnected. unconnected.
PS_DDR_CK0 CK_t[0] CK_t[0] CK_t[0] CK_t[0] CK_t[0] CK_t[0]
PS_DDR_CK1 Can be left CK_t[1] Can be left CK_t[1] Can be left CK_t[1]
unconnected. unconnected. unconnected.
PS_DDR_CKE0 CKE CKE[0] CKE CKE[0] CKE CKE[0]
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
PS_DDR_CKE1 Can be left CKE[1] Can be left CKE[1] Can be left CKE[1]
unconnected. unconnected. unconnected.
PS_DDR_CS_N0 CS_n CS_n[0] CS_n CS_n[0] CS_n CS_n[0]
PS_DDR_CS_N1 Can be left CS_n[1] Can be left CS_n[1] Can be left CS_n[1]
unconnected. unconnected. unconnected.
PS_DDR_DM0 to Connect Connect Connect Connect Connect Connect
PS_DDR_DM1 DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0]
to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0,
DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1]
to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1,
and so on. and so on. and so on. and so on. and so on. and so on.
PS_DDR_DM2 to Connect Connect Connect Connect Can be left Can be left
PS_DDR_DM3 DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] unconnected. unconnected.
to PS_DDR_DM2, to PS_DDR_DM2, to PS_DDR_DM2, to PS_DDR_DM2,
DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3]
to PS_DDR_DM3, to PS_DDR_DM3, to PS_DDR_DM3, to PS_DDR_DM3,
and so on. and so on. and so on. and so on.
PS_DDR_DM4 to Connect Connect Can be left Can be left Can be left Can be left
PS_DDR_DM7 DM_n[4]/DBI_n[4] DM_n[4]/DBI_n[4] unconnected. unconnected. unconnected. unconnected.
to PS_DDR_DM4, to PS_DDR_DM4,
DM_n[5]/DBI_n[5] DM_n[5]/DBI_n[5]
to PS_DDR_DM5, to PS_DDR_DM5,
and so on. and so on.
PS_DDR_DM8 DM_n[8]/DBI_n[8], DM_n[8]/DBI_n[8], DM_n[4]/DBI_n[4], DM_n[4]/DBI_n[4], DM_n[2]/DBI_n[2], DM_n[2]/DBI_n[2],
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to
PS_DDR_DQ15 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1
to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1,
and so on. and so on. and so on. and so on. and so on. and so on.
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
PS_DDR_DQ16 to Connect DQ16 to Connect DQ16 to Connect DQ16 to Connect DQ16 to Can be left Can be left
PS_DDR_DQ31 PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, unconnected. Do unconnected. Do
DQ17 to DQ17 to DQ17 to DQ17 to not swap with not swap with
PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ0 to PS_DDR_DQ0 to
so on. so on. so on. so on. PS_DDR_DQ15. PS_DDR_DQ15.
PS_DDR_DQ32 to Connect DQ32 to Connect DQ32 to Can be left Can be left Can be left Can be left
PS_DDR_DQ63 PS_DDR_DQ32, PS_DDR_DQ32, unconnected. Do unconnected. Do unconnected. Do unconnected. Do
DQ33 to DQ33 to not swap with not swap with not swap with not swap with
PS_DDR_DQ33, and PS_DDR_DQ33, and PS_DDR_DQ0 to PS_DDR_DQ0 to PS_DDR_DQ0 to PS_DDR_DQ0 to
so on. so on. PS_DDR_DQ31. PS_DDR_DQ31. PS_DDR_DQ31. PS_DDR_DQ31.
PS_DDR_DQ64 DQ64 (ECC_bit[0]), DQ64 (ECC_bit[0]), DQ32 (ECC_bit[0]), DQ32 (ECC_bit[0]), DQ16 (ECC_bit[0]), DQ16 (ECC_bit[0]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ65 DQ65 (ECC_bit[1]), DQ65 (ECC_bit[1]), DQ33 (ECC_bit[1]), DQ33 (ECC_bit[1]), DQ17 (ECC_bit[1]), DQ17 (ECC_bit[1]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ66 DQ66 (ECC_bit[2]), DQ66 (ECC_bit[2]), DQ34 (ECC_bit[2]), DQ34 (ECC_bit[2]), DQ18 (ECC_bit[2]), DQ18 (ECC_bit[2]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ67 DQ67 (ECC_bit[3]), DQ67 (ECC_bit[3]), DQ35 (ECC_bit[3]), DQ35 (ECC_bit[3]), DQ19 (ECC_bit[3]), DQ19 (ECC_bit[3]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ68 DQ68 (ECC_bit[4]), DQ68 (ECC_bit[4]), DQ36 (ECC_bit[4]), DQ36 (ECC_bit[4]), DQ20 (ECC_bit[4]), DQ20 (ECC_bit[4]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
PS_DDR_DQ69 DQ69 (ECC_bit[5]), DQ69 (ECC_bit[5]), DQ37 (ECC_bit[5]), DQ37 (ECC_bit[5]), DQ21 (ECC_bit[5]), DQ21 (ECC_bit[5]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ70 DQ70 (ECC_bit[6]), DQ70 (ECC_bit[6]), DQ38 (ECC_bit[6]), DQ38 (ECC_bit[6]), DQ22 (ECC_bit[6]), DQ22 (ECC_bit[6]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ71 DQ71 (ECC_bit[7]), DQ71 (ECC_bit[7]), DQ39 (ECC_bit[7]), DQ39 (ECC_bit[7]), DQ23 (ECC_bit[7]), DQ23 (ECC_bit[7]),
can be left can be left can be left can be left can be left can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQS_N0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to
PS_DDR_DQS_N1 PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0,
DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to
PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1,
and so on. and so on. and so on. and so on. and so on. and so on.
PS_DDR_DQS_N2 to Connect DQS_c2 to Connect DQS_c2 to Connect DQS_c2 to Connect DQS_c2 to Can be left Can be left
PS_DDR_DQS_N3 PS_DDR_DQS_N2, PS_DDR_DQS_N2, PS_DDR_DQS_N2, PS_DDR_DQS_N2, unconnected. unconnected.
DQS_c3 to DQS_c3 to DQS_c3 to DQS_c3 to
PS_DDR_DQS_N3, PS_DDR_DQS_N3, PS_DDR_DQS_N3, PS_DDR_DQS_N3,
and so on. and so on. and so on. and so on.
PS_DDR_DQS_N4 to Connect DQS_c4 to Connect DQS_c4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_N7 PS_DDR_DQS_N4, PS_DDR_DQS_N4, unconnected. unconnected. unconnected. unconnected.
DQS_c5 to DQS_c5 to
PS_DDR_DQS_N5, PS_DDR_DQS_N5,
and so on. and so on.
PS_DDR_DQS_N8 DQS_c8, can be left DQS_c8, can be left DQS_c4, can be left DQS_c4, can be left DQS_c2, can be left DQS_c2, can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
PS_DDR_DQS_P0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to
PS_DDR_DQS_P1 PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0,
DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to
PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1,
and so on. and so on. and so on. and so on. and so on. and so on.
PS_DDR_DQS_P2 to Connect DQS_t2 to Connect DQS_t2 to Connect DQS_t2 to Connect DQS_t2 to Can be left Can be left
PS_DDR_DQS_P3 PS_DDR_DQS_P2, PS_DDR_DQS_P2, PS_DDR_DQS_P2, PS_DDR_DQS_P2, unconnected. unconnected.
DQS_t3 to DQS_t3 to DQS_t3 to DQS_t3 to
PS_DDR_DQS_P3, PS_DDR_DQS_P3, PS_DDR_DQS_P3, PS_DDR_DQS_P3,
and so on. and so on. and so on. and so on.
PS_DDR_DQS_P4 to Connect DQS_t4 to Connect DQS_t4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_P7 PS_DDR_DQS_P4, PS_DDR_DQS_P4, unconnected. unconnected. unconnected. unconnected.
DQS_t5 to DQS_t5 to
PS_DDR_DQS_P5, PS_DDR_DQS_P5,
and so on. and so on.
PS_DDR_DQS_P8 DQS_t8, can be left DQS_t8, can be left DQS_t4, can be left DQS_t4, can be left DQS_t2, can be left DQS_t2, can be left
unconnected unconnected unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_ODT0 ODT ODT[0] ODT ODT[0] ODT ODT[0]
PS_DDR_ODT1 Can be left ODT[1] Can be left ODT[1] Can be left ODT[1]
unconnected. unconnected. unconnected.
PS_DDR_PARITY PAR PAR PAR PAR PAR PAR
PS_DDR_RAM_RST_N RESET_n RESET_n RESET_n RESET_n RESET_n RESET_n
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
PS_DDR_ZQ Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND
through a 240Ω through a 240Ω through a 240Ω through a 240Ω through a 240Ω through a 240Ω
resistor. Connect resistor. Connect resistor. Connect resistor. Connect resistor. Connect resistor. Connect
DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to
VSSQ through a VSSQ through a VSSQ through a VSSQ through a VSSQ through a VSSQ through a
240Ω resistor. 240Ω resistor. 240Ω resistor. 240Ω resistor. 240Ω resistor. 240Ω resistor.
Notes:
1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
2. The PS_DDR_BG1 pin can be left unconnected when targeting x16 component interfaces without a BG1 pin, but it should always be connected for DIMM applications.
LPDDR4 Guidelines
LPDDR4 Pin Rules
The LPDDR4 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in an 64-bit interface
without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and
PS_DDR_DM8 pins can be left unconnected.
• Connect the PS_DDR_ZQ pin to GND using a 240Ω resistor. There should be separate
240Ω resistors at the FPGA and at the DRAM.
• To achieve maximum performance, address copy mode is suggested.
Pin Name LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit
1Rank 1Rank ECC 2Rank 2Rank ECC
VCCO_PSDDR(1) Set to 1.1V Set to 1.1V Set to 1.1V Set to 1.1V
PS_DDR_A0 CA0_A CA0_A CA0_A CA0_A
PS_DDR_A1 CA1_A CA1_A CA1_A CA1_A
PS_DDR_A2 CA2_A CA2_A CA2_A CA2_A
PS_DDR_A3 CA3_A CA3_A CA3_A CA3_A
PS_DDR_A4 CA4_A CA4_A CA4_A CA4_A
PS_DDR_A5 CA5_A CA5_A CA5_A CA5_A
PS_DDR_A6 to Can be left Can be left Can be left Can be left
PS_DDR_A9 unconnected. unconnected. unconnected. unconnected.
Pin Name LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit
1Rank 1Rank ECC 2Rank 2Rank ECC
PS_DDR_A10 CA0_B CA0_B CA0_B CA0_B
PS_DDR_A11 CA1_B CA1_B CA1_B CA1_B
PS_DDR_A12 CA2_B CA2_B CA2_B CA2_B
PS_DDR_A13 CA3_B CA3_B CA3_B CA3_B
PS_DDR_A14 CA4_B CA4_B CA4_B CA4_B
PS_DDR_A15 CA5_B CA5_B CA5_B CA5_B
PS_DDR_A16 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_A17 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_ACT_N Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_ALERT_N Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_BA0 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_BA1 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_BG0 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_BG1 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_CK_N0 CK_c_A CK_c_A CK_c_A CK_c_A
PS_DDR_CK_N1 CK_c_B CK_c_B CK_c_B CK_c_B
PS_DDR_CK0 CK_t_A CK_t_A CK_t_A CK_t_A
PS_DDR_CK1 CK_t_B CK_t_B CK_t_B CK_t_B
PS_DDR_CKE0 CKE_A and CKE_B CKE_A CKE0_A and CKE0_B CKE0_A
PS_DDR_CKE1 Can be left Can be left CKE1_A and CKE1_B CKE1_A
unconnected. unconnected.
PS_DDR_CS_N0 CS_A and CS_B CS_A CS0_A and CS0_B CS0_A
PS_DDR_CS_N1 Can be left Can be left CS1_A and CS1_B CS1_A
unconnected. unconnected.
PS_DDR_DM0 DMI0_A DMI0_A DMI0_A DMI0_A
PS_DDR_DM1 DMI1_A DMI1_A DMI1_A DMI1_A
PS_DDR_DM2 DMI0_B DMI0_B DMI0_B DMI0_B
PS_DDR_DM3 DMI1_B DMI1_B DMI1_B DMI1_B
PS_DDR_DM4 to Can be left Can be left Can be left Can be left
PS_DDR_DM7 unconnected. unconnected. unconnected. unconnected.
Pin Name LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit
1Rank 1Rank ECC 2Rank 2Rank ECC
PS_DDR_DM8 Can be left DMI_ECC Can be left DMI_ECC
unconnected. unconnected.
PS_DDR_DQ0 to Connect DQ0_A to Connect DQ0_A to Connect DQ0_A to Connect DQ0_A to
PS_DDR_DQ15 PS_DDR_DQ0, PS_DDR_DQ0, PS_DDR_DQ0, PS_DDR_DQ0,
DQ1_A to DQ1_A to DQ1_A to DQ1_A to
PS_DDR_DQ1, and PS_DDR_DQ1, and PS_DDR_DQ1, and PS_DDR_DQ1, and
so on. so on. so on. so on.
PS_DDR_DQ16 to Connect DQ0_B to Connect DQ0_B to Connect DQ0_B to Connect DQ0_B to
PS_DDR_DQ31 PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16,
DQ1_B to DQ1_B to DQ1_B to DQ1_B to
PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and
so on. so on. so on. so on.
PS_DDR_DQ32 to Can be left Can be left Can be left Can be left
PS_DDR_DQ63 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DQ64 Can be left DQ_ECC0 Can be left DQ_ECC0
unconnected. (ECC_bit[0]) unconnected. (ECC_bit[0])
PS_DDR_DQ65 Can be left DQ_ECC1 Can be left DQ_ECC1
unconnected. (ECC_bit[1]) unconnected. (ECC_bit[1])
PS_DDR_DQ66 Can be left DQ_ECC2 Can be left DQ_ECC2
unconnected. (ECC_bit[2]) unconnected. (ECC_bit[2])
PS_DDR_DQ67 Can be left DQ_ECC3 Can be left DQ_ECC3
unconnected. (ECC_bit[3]) unconnected. (ECC_bit[3])
PS_DDR_DQ68 Can be left DQ_ECC4 Can be left DQ_ECC4
unconnected. (ECC_bit[4]) unconnected. (ECC_bit[4])
PS_DDR_DQ69 Can be left DQ_ECC5 Can be left DQ_ECC5
unconnected. (ECC_bit[5]) unconnected. (ECC_bit[5])
PS_DDR_DQ70 Can be left DQ_ECC6 Can be left DQ_ECC6
unconnected. (ECC_bit[6]) unconnected. (ECC_bit[6])
PS_DDR_DQ71 Can be left DQ_ECC7 Can be left DQ_ECC7
unconnected. (ECC_bit[7]) unconnected. (ECC_bit[7])
PS_DDR_DQS_N0 DQS0_c_A DQS0_c_A DQS0_c_A DQS0_c_A
PS_DDR_DQS_N1 DQS1_c_A DQS1_c_A DQS1_c_A DQS1_c_A
PS_DDR_DQS_N2 DQS0_c_B DQS0_c_B DQS0_c_B DQS0_c_B
PS_DDR_DQS_N3 DQS1_c_B DQS1_c_B DQS1_c_B DQS1_c_B
PS_DDR_DQS_N4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_N7 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DQS_N8 Can be left DQS_c_ECC Can be left DQS_c_ECC
unconnected. unconnected.
PS_DDR_DQS_P0 DQS0_t_A DQS0_t_A DQS0_t_A DQS0_t_A
PS_DDR_DQS_P1 DQS1_t_A DQS1_t_A DQS1_t_A DQS1_t_A
PS_DDR_DQS_P2 DQS0_t_B DQS0_t_B DQS0_t_B DQS0_t_B
Pin Name LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit
1Rank 1Rank ECC 2Rank 2Rank ECC
PS_DDR_DQS_P3 DQS1_t_B DQS1_t_B DQS1_t_B DQS1_t_B
PS_DDR_DQS_P4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_P7 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DQS_P8 Can be left DQS_t_ECC Can be left DQS_t_ECC
unconnected. unconnected.
PS_DDR_ODT0 Unconnected at Unconnected at Unconnected at Unconnected at
FPGA. FPGA. FPGA. FPGA.
PS_DDR_ODT1 Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_PARITY Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_RAM_RST_N RESET_n RESET_n RESET_n RESET_n
PS_DDR_ZQ Connect to GND Connect to GND Connect to GND Connect to GND
through a 240Ω through a 240Ω through a 240Ω through a 240Ω
resistor. Connect resistor. Connect resistor. Connect resistor. Connect
DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to
VDDQ through a VDDQ through a VDDQ through a VDDQ through a
240Ω resistor. 240Ω resistor. 240Ω resistor. 240Ω resistor.
Notes:
1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
LPDDR3 Guidelines
LPDDR3 Pin Rules
The LPDDR3 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in an 64-bit interface
without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and
PS_DDR_DM8 pins can be left unconnected.
• Connect the PS_DDR_ZQ pin to GND using a 240Ω resistor. There should be separate
240Ω resistors at the FPGA and at the DRAM.
• To achieve maximum performance, address copy mode is suggested.
Notes:
1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
2. There should be separate 240Ω resistors at the FPGA and at the DRAM.
Package Files
° Memory Byte Group—Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the
UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
[Ref 15].
° Bank—Bank number.
° I/O Type—CONFIG, HD, HP, GTH, GTY, PS-GTR, PSMIO, PSDDR, or PSCONFIG
depends on the I/O type. For more information on the I/O type, see the UltraScale
Architecture SelectIO Resources User Guide (UG571) [Ref 6].
° Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.
• Total number of pins in the package.
Evaluation Only
These package specifications are based on initial device specifications, package routability
analysis and mechanical package construction. Package specifications with this designation
are not stable and package pinouts are likely to change and these specifications should
only be used for initial system level design feasibility.
Engineering Sample
These package specifications are based on a released package design and validated with ES
engineering sample (ES) devices. Package specifications with this designation are
considered stable, however some pinout and mechanical specifications might change prior
to the production release of the particular device. Package pinouts with this designation are
to be used for PCB and Vivado® designs using ES devices.
Production
These package specifications are released coincident with production release of a particular
device. Customers receive formal notification of any subsequent changes.
www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html
Note: All package files are ASCII files in TXT and CSV file format. Only the available files listed in
Table 3-1 are linked and consolidated in this ZIP file:
www.xilinx.com/support/packagefiles/zuppackages/zupall.zip
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 3-1: Package/Device Pinout Files for CG, EG, and EV devices
Packages Footprint Compatible Devices
XCZU2CG XCZU3CG
XCZU2EG XCZU3EG
SBVA484
XAZU2EG XAZU3EG
Production Production
SFRA484 XQZU3EG
Production
XCZU2CG XCZU3CG
XCZU2EG XCZU3EG
SFVA625
XAZU2EG XAZU3EG
Production Production
XCZU4CG XCZU5CG
XCZU2CG XCZU3CG
XCZU4EG XCZU5EG
XCZU2EG XCZU3EG
SFVC784 XCZU4EV XCZU5EV
XAZU2EG XAZU3EG
XAZU4EV XAZU5EV
Production Production
Production Production
SFRC784 XQZU3EG XQZU5EV
Production Production
XCZU4CG XCZU5CG XCZU7CG
XCZU4EG XCZU5EG XCZU7EG XAZU7EV
FBVB900
XCZU4EV XCZU5EV XCZU7EV Production
Production Production Production
FFRB900 XQZU5EV XQZU7EV
Production Production
Table 3-1: Package/Device Pinout Files for CG, EG, and EV devices (Cont’d)
Packages Footprint Compatible Devices
XCZU6CG XCZU9CG
XCZU15EG
FFVC900 XCZU6EG XCZU9EG
Production
Production Production
FFRC900 XQZU9EG XQZU15EG
Production Production
XCZU6CG XCZU9CG
XCZU15EG
FFVB1156 XCZU6EG XCZU9EG
Production
Production Production
FFRB1156 XQZU9EG XQZU15EG
Production Production
XCZU7CG
XCZU7EG XCZU11EG
FFVC1156
XCZU7EV Production
Production
FFRC1156 XQZU7EV XQZU11EG
Production Production
XCZU11EG XCZU17EG XCZU19EG
FFVB1517
Production Production Production
FFRB1517 XCZU19EG
Production
XCZU7CG
XCZU7EG XCZU11EG XAZU11EG
FFVF1517
XCZU7EV Production Production
Production
XCZU11EG XCZU17EG XCZU19EG
FFVC1760
Production Production Production
FFRC1760 XQZU11EG XQZU19EG
Production Production
XCZU17EG XCZU19EG
FFVD1760
Production Production
XCZU17EG XCZU19EG
FFVE1924
Production Production
Device Diagrams
Summary
The diagrams in this chapter show top-view perspective of the package pinout of each
Zynq® UltraScale+™ device/package combination. Table 4-1 is a cross reference to the
device/package diagrams. The I/O-bank diagram shows the location of each user I/O,
PSMIO, PSDDR, PSCONFIG, and PS-GTR, GTH, and GTY transceiver and the respective bank
or GT quad. The configuration-power diagram shows the location of every power pin and
dedicated as well as multi-function configuration pin in the package. See Package
Specifications Designations in Chapter 3 for definitions of Evaluation Only, Engineering
Sample, and Production device diagrams.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
XQZU3EG XQZU5EV
SFRC784 Production Production
page 112 page 116
XCZU4CG, XCZU4EG, XCZU7EV
XCZU4EVand XCZU5EV XCZU7CG, XCZU7EG
XCZU5CG, XCZU5EG XAZU7EV
FBVB900 Production Production
Production Production
page 120 page 122
page 118 page 124
XQZU5EV XQZU7EV
FFRB900 Production Production
page 120 page 124
XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG XCZU15EG
FFVC900 Production Production Production
page 126 page 126 page 126
XQZU9EG XQZU15EG
FFRC900 Production Production
page 126 page 126
XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG XCZU15EG
FFVB1156 Production Production Production
page 128 page 128 page 128
XQZU9EG XQZU15EG
FFRB1156 Production Production
page 128 page 128
XCZU7CG, XCZU7EG XCZU7EV XCZU11EG
FFVC1156 Production Production Production
page 130 page 132 page 134
XQZU7EV XQZU11EG
FFRC1156 Production Production
page 132 page 134
XCZU21DR
FFVD1156 Production
page 136
XQZU21DR
FFRD1156 Production
page 136
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A S 12 12 12 10 10 9 45 48 50 58 69 70 3
505
3 A
VC 65
VC 26
3
B 11 11 11 11 12 9 41 44 47 57 65 68 75 77 B
C
3
O
505
VC 501
VC 502
C 24 22 7 8 8 38 39 46 51 55 62 72 2 2 C
C
O
O
505
VC 502
2
D 21 24 22 7 5 5 6 36 40 42 49 60 66 73 74 D
C
2
O
505
V C 26
3
E 21 20 20 3 3 6 33 35 37 43 56 59 64 E
C
3
O
505
VC 501
F 19 23 23 S 2 4 4 29 31 32 34 53 63 71 76 1 1 F
C
O
505
VC 6 5
VC 503
2
G 19 17 18 1 1 2 26 30 27 28 52 54 61 67 G
C
2
O
505
VC 503
1
H 17 S 18 16 DI CK RC MD PI MD H
C
1
O
505
1
J 15 13 13 16 MS DO MD MD PO
505
1 J
V C 65
K 15 14 14 PR SR PG IN EO ES 0 0 K
C
O
505
0
L 11 11 12 12 DN
505
0 L
0
M 9 9 10 10 G 505
0 M
N 7 S 8 8 70 71 N
V C 65
VC 504
P 7 2 6 69 P 67 65 P
C
C
O
O
R 5 2 4 6 68 DM N 66 R
VC 504
T 5 1 1 4 21 23 RS ZQ AL 64 T
C
O
U 3 3 0 3 4 20 DM 22 24 25 29 AC BG BA PA CS CE CE U
VC 500
VC 504
VC 504
V 2 8 7 9 18 N P 19 P N 28 31 BA C CN C CS V
C
C
O
O
W 1 11 13 14 21 17 16 3 27 26 DM 30 A A BG CN OD OD W
VC 504
VC 504
Y 6 16 15 18 25 5 P 1 9 P 12 14 A A A A A Y
C
O
O
VC 500
AA 5 10 17 19 22 7 4 N 8 10 N 13 A A A A A A AA
C
O
VC 504
AB 12 20 23 24 6 DM 2 0 11 DM 15 A A A A A AB
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A V A
B V B
C 35 C
D 34 V D
E E
F 33 E F
G G
H E H
J J
K E K
L 24 21 PL PL AU AU L
M 22 23 PL DP DP AU AU M
N 8 7 LP LP FP BT DD N
P LP LP AD AD DD P
R 38 LP LP FP FP R
T 13 15 FP FP FP FP DD T
U U
V V
W W
Y Y
AA AA
AB AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A 8 8 S 19 19 24 22 22 3 2 30 39 41 57 58 60 65 3
505
3 A
3
B 7 10 10 21 23 24 20 4 3 2 29 43 47 55 59 69
505
3 B
C 7 12 12 21 23 20 6 4 5 31 38 46 48 61 62 70 2
505
2 C
V C 66
V C 26
VC 501
VC 502
2
D 9 9 11 11 14 14 S 6 5 1 32 36 51 56 63 66 D
C
2
O
505
VC 66
VC 501
VC 502
3
E 3 3 2 13 13 S 7 8 8 1 34 44 50 53 71 72 E
C
3
O
505
VC 26
F 5 4 2 15 18 16 7 10 12 33 35 42 54 64 75 73 1 1 F
C
O
505
VC 66
VC 501
VC 502
2
G 1 5 4 15 17 18 16 10 11 12 27 40 49 52 68 74 G
C
2
O
505
1
H 1 6 6 17 9 9 11 26 28 37 45 67 77 76
505
1 H
VC 503
1
J 15 17 17 23 24 24 MD MD MD EO J
C
1
O
505
VC 503
K 15 18 23 21 21 22 RC CK PI PO MD G 0 0 K
C
O
505
VC 65
0
L 18 13 S 19 22 DI DO MS IN ES L
C
0
O
505
0
M 16 16 13 20 19 S PG PR
505
0 M
N 3 14 14 20 SR DN 69 N
VC 65
P 3 5 5 11 10 10 70 P DM 67 P
C
O
R 1 1 11 12 12 8 71 N 65 66 R
T 6 9 9 8 68 64 CE CS T
VC 6 5
U 2 6 4 7 7 S RS ZQ AL A U
C
O
VC 64
VC 500
VC 504
V 2 4 S S 0 2 16 23 AC BG BA BG PA OD A V
C
O
O
VC 500
VC 500
W 23 20 20 22 12 10 10 3 1 10 15 22 19 DM 16 A A BA CS CE W
C
O
VC 504
Y 23 19 22 11 12 8 4 6 7 13 24 23 22 P 17 A A C OD A Y
C
O
VC 64
VC 504
AA 19 24 24 11 8 7 7 5 20 7 DM 21 N 20 18 A CN C CN A AA
C
C
O
O
VC 64
VC 504
AB 21 21 13 14 1 9 9 9 12 18 6 0 9 DM 14 26 29 A A A AB
C
C
O
O
VC 504
AC S 13 14 1 6 6 8 14 5 P 2 8 15 27 P N A A A AC
C
O
VC 504
AD 17 15 16 16 5 5 2 2 4 17 21 4 N 10 P 13 25 DM 31 A A AD
C
O
VC 504
AE 17 15 18 18 3 3 4 11 19 25 3 1 11 N 12 24 28 30 A AE
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A V A
B V B
C C
D V D
E E
F E F
G G
H E H
J 35 34 J
K 33 K
L L
M PL PL PL M
N 24 21 DP DP AU BT N
P 22 23 LP LP AU AU P
R 8 7 LP LP LP AU DD R
T FP LP AD AD DD T
U 38 FP FP FP FP DD U
V 15 13 FP FP V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
VC 66
V C 25
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
VC 26
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
VC 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
VC 66
V C 25
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 26
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
VC 65
VC 501
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
V C 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
VC 503
VC 504
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
O
O
R 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
O
U 3 2 RS ZQ AL OD OD U
VC 504
V 3 2 BG BA PA CS CE CE V
C
O
W 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
Y 1 11 10 12 10 10 A AC C CN A A Y
C
O
VC 24
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
VC 64
VC 44
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
V C 64
VC 24
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
V C 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
VC 44
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N n n n n N
P n n n P
R n n 38 24 21 R
T n n n 22 23 PL PL PL T
U n n n 15 8 7 DP DP AU AU n U
V n n n n n LP LP LP AU n n V
W n n n 13 LP LP LP AU AD n W
Y n n n n n FP FP BT DD AD n Y
AA FP FP FP FP DD DD AA
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
V C 66
V C 45
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
V C 46
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
VC 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
V C 66
VC 45
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 46
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
V C 65
VC 501
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
VC 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N V G 3
224
3 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
V C 503
VC 504
3
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
3
O
224
R 2
224
2 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
2
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
2
O
224
U 1
224
1 3 2 RS ZQ AL OD OD U
VC 504
1 1
V 3 2 BG BA PA CS CE CE V
C
1 1
O
224 224
W 0
224
0 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
0 0
Y 1 11 10 12 10 10 A AC C CN A A Y
C
0 0
O
224 224
V C 44
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
VC 64
VC 43
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
VC 64
VC 44
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
VC 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
VC 43
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
# # EO
Figure 4-7: SFVC784 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N N
P V P
R 38 24 21 R
T V 22 23 PL PL PL T
V
U 15 8 7 DP DP AU AU R U
V E LP LP LP AU R R V
V
W 13 LP LP LP AU AD R W
Y E FP FP BT DD AD R Y
AA FP FP FP FP DD DD AA
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
VC 66
V C 45
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
V C 46
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
V C 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
V C 66
V C 45
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 46
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
V C 65
VC 5 0 1
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
VC 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N V G 3
224
3 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
VC 503
VC 504
3
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
3
O
224
R 2
224
2 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
2
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
2
O
224
U 1
224
1 3 2 RS ZQ AL OD OD U
VC 504
1 1
V 3 2 BG BA PA CS CE CE V
C
1 1
O
224 224
W 0
224
0 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
0 0
Y 1 11 10 12 10 10 A AC C CN A A Y
C
0 0
O
224 224
V C 44
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
V C 64
V C 43
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
VC 64
VC 44
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
VC 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
V C 43
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
# # EO
Figure 4-9: SFVC784 Package—XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N N
P V P
R 38 24 21 R
T V 22 23 PL PL PL T
V
U 15 8 7 DP DP AU AU U
V E LP LP LP AU V
V
W 13 LP LP LP AU AD W
Y E FP FP BT DD AD Y
AA FP FP FP FP DD DD AA
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
226
3
226
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
226 226 226
1
C 1
226
1
226
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
V C 46
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
226 226 226
VC 45
VC 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
225 225
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
225 225 225
VC 46
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
225 225 505 505
VC 45
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
225 225 225 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
224 224 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
224 224 505 505
0 1 0
L 2
224
2
0
224
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
224
1
224
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
224 223
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
223 224
0
R 3
223
3 0
223
MD MD ES EO 41 DM N 63 P N 56 R
2
T 2
223
2
223
2 42 44 46 61 60 57 T
1
U 1
223
45 32 34 48 50 P 52 U
0
V 0
223
1
223
1 33 35 49 51 DM N 53 V
W 0
223
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
V C 66
VC 5 0 4
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
AB 23 22 17 14 14 12 5 5 3 1 4 5 16 ZQ AL RS PA CE 64 OD AB
C
O
V C 64
VC 504
AC 23 21 21 17 8 11 11 7 3 1 3 15 17 17 S P 28 29 31 BA BG BG OD CE AC
C
O
O
V C 66
VC 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
V C 65
VC 504
AE 20 19 S 16 15 13 10 10 2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
C
O
O
VC 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
V C 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
# # EO
Figure 4-11: FBVB900 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
T 24 21 PL PL PL AU T
U V 22 23 DP DP BT AU U
V 8 7 LP LP LP AU AU V
W 15 LP LP LP AD AD W
Y 13 FP FP FP FP FP DD Y
AA FP FP DD DD AA
AB R R R R AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
226
3
226
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
226 226 226
1
C 1
226
1
226
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
V C 46
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
226 226 226
VC 45
VC 5 0 1
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
225 225
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
225 225 225
VC 46
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
225 225 505 505
V C 45
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
225 225 225 505 505
V C 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
224 224 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
224 224 505 505
0 1 0
L 2
224
2
0
224
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
224
1
224
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
224 223
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
223 224
0
R 3
223
3 0
223
MD MD ES EO 41 DM N 63 P N 56 R
2
T 2
223
2
223
2 42 44 46 61 60 57 T
1
U 1
223
45 32 34 48 50 P 52 U
0
V 0
223
1
223
1 33 35 49 51 DM N 53 V
W 0
223
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
V C 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
AB 23 22 17 14 14 12 5 5 3 1 4 5 16 ZQ AL RS PA CE 64 OD AB
C
O
V C 64
VC 504
AC 23 21 21 17 8 11 11 7 3 1 3 15 17 17 S P 28 29 31 BA BG BG OD CE AC
C
O
O
VC 66
VC 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
VC 6 5
VC 5 0 4
AE 20 19 S 16 15 13 10 10 C
2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
O
O
V C 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
VC 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
T 24 21 PL PL PL AU T
U V 22 23 DP DP BT AU U
V 8 7 LP LP LP AU AU V
W 15 LP LP LP AD AD W
Y 13 FP FP FP FP FP DD Y
AA FP FP DD DD AA
AB AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
227
3
227
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
227 227 227
1
C 1
227
1
227
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
VC 47
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
227 227 227
VC 48
VC 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
226 226
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
226 226 226
VC 47
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
226 226 505 505
VC 48
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
226 226 226 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
225 225 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
225 225 505 505
0 1 0
L 2
225
2
0
225
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
225
1
225
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
225 224
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
224 225
0
R 3
224
3 0
224
MD MD ES EO 41 DM N 63 P N 56 R
2
T 2
224
2
224
2 42 44 46 61 60 57 T
1
U 1
224
45 32 34 48 50 P 52 U
0
V 0
224
1
224
1 33 35 49 51 DM N 53 V
W 0
224
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
VC 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
AB 23 22 17 14 14 12 5 5 3 1 4 5 16 ZQ AL RS PA CE 64 OD AB
C
O
VC 64
VC 504
AC 23 21 21 17 8 11 11 7 3 1 3 15 17 17 S P 28 29 31 BA BG BG OD CE AC
C
O
O
VC 66
V C 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
V C 65
VC 504
AE 20 19 S 16 15 13 10 10 2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
C
O
O
VC 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
VC 65
V C 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
T 24 21 PL PL PL AU T
U V 22 23 DP DP BT AU U
V 8 7 LP LP LP AU AU V
W 15 LP LP LP AD AD W
Y 13 FP FP FP FP FP DD Y
AA FP FP DD DD AA
AB R R R R AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
FBVB900 Package–XCZU7EV
X-Ref Target - Figure 4-17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
227
3
227
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
227 227 227
1
C 1
227
1
227
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
VC 47
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
227 227 227
VC 48
V C 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
226 226
VC 5 0 0
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
226 226 226
VC 47
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
226 226 505 505
VC 4 8
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
226 226 226 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
225 225 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
225 225 505 505
0 1 0
L 2
225
2 0
225
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
225
1
225
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
225 224
VC 5 0 3
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
224 225
0
R 3
224
3 0
224
MD MD ES EO 41 DM N 63 P N 56 R
2
T 2
224
2
224
2 42 44 46 61 60 57 T
1
U 1
224
45 32 34 48 50 P 52 U
0
V 0
224
1
224
1 33 35 49 51 DM N 53 V
W 0
224
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
VC 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
AB 23 22 17 14 14 12 5 5 3 1 4 5 16 ZQ AL RS PA CE 64 OD AB
C
O
VC 6 4
VC 504
AC 23 21 21 17 8 11 11 7 3 1 3 15 17 17 S P 28 29 31 BA BG BG OD CE AC
C
O
O
VC 66
V C 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
VC 65
VC 504
AE 20 19 S 16 15 13 10 10 C
2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
O
O
V C 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
V C 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 5 0 4
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
T 24 21 PL PL PL AU T
U V 22 23 DP DP BT AU U
V 8 7 LP LP LP AU AU V
W 15 LP LP LP AD AD W
Y 13 FP FP FP FP FP DD Y
AA FP FP DD DD AA
AB AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A G 3 2 2 3 2 1 A
V
3 3 3 19 17 7 26 44 45 52 66 3 3
230 230 128
2 3
B 3 1 3 2 1 G B
V
2 2 2 20 10 28 37 46 67 3
230 230 128
1
C 1
230
1
230
1 4 1 4 4 18 15 0 27 49 54 68 2
128
2 C
VC 500
VC 502
0 1 2
D 0 0 6 4 5 5 5 21 16 30 34 47 53 D
C
0 1 2
O
230 230 128 128
VC 501
1
E 3 3 6 5 6 6 7 14 2 29 36 56 69 1 1 E
C
1
O
229 230 128
3 0 1
F 3
229
2
229
2 8 7 7 8 7 23 13 3 38 48 55 70
128
0
128
1 F
VC 500
2 0
G 8 10 8 9 9 25 4 11 40 50 71 0 0 G
C
2 0
O
229 230 128
V C 48
VC 47
V C 501
1 3 0
H 1 1 11 10 12 12 22 1 6 39 57 60 75 H
C
1 3 0
O
229 229 505 128
VC 47
VC 502
1
J 0 0 12 12 11 11 10 24 5 31 51 58 64 3 3 J
C
1
O
229 229 505
VC 48
VC 500
0 2 3
K 3 3 24 9 9 11 10 12 8 32 41 63 72 K
C
0 2 3
O
229 228 505 505
VC 501
3 0
L 24 23 23 9 43 59 76 77 2 2 L
C
3 0
O
228 229 505
VC 502
2 1 2
M 2 2 22 21 33 42 61 74 M
C
2 1 2
O
228 228 505 505
1
N 1
228
1
1
228
22 S 21 35 62 65 73 1
505
1 N
1 0 1
P 1
228
0
228
0 20 20 SR RC EO ES
505
0
505
1 P
VC 503
0 0
R 19 MS CK PI PO G 0 0 R
C
0 0
O
228 228 505
VC 503
0
T 6 19 18 DN DO DI PG IN T
C
0
O
505
U 6 5 5 9 9 10 10 13 17 18 15 MD MD MD MD PR 47 46 44 45 U
V C 66
V 4 4 8 11 11 13 17 15 DM P N 62 63 61 V
C
O
VC 66
W 3 3 8 7 12 12 C
O
16 16 42 43 41 40 P 60 W
V C 66
Y 2 2 1 1 7 S 14 14 S 32 33 59 58 N DM Y
C
O
VC 65
AA 24 23 23 15 15 10 10 5 5 34 35 57 56 48 AA
C
O
AB 24 19 18 13 13 12 7 6 6 1 P N DM 51 49 50 AB
VC 65
AC 22 21 19 18 14 11 12 7 4 1 PA RS AC ZQ 39 36 52 P N DM AC
C
O
VC 65
AD 22 21 17 16 14 11 9 8 4 3 20 22 21 23 AL A A A 37 38 BG 53 54 55 AD
C
O
VC 504
VC 504
AE S 20 20 17 16 S S 9 8 3 2 DM P 24 25 27 26 A A A A 64 67 DM 71 AE
C
O
O
V C 64
AF 24 24 23 16 16 7 7 8 1 2 N 19 P N DM A A A BA BG 65 69 AF
C
O
VC 64
VC 504
VC 504
AG 22 23 S 13 13 12 S 8 1 2 16 17 18 28 30 31 A C CN CS BA 66 P 70 AG
C
C
O
O
VC 64
AH 22 20 20 18 14 11 12 9 3 2 7 3 1 29 11 14 A A OD CE N 68 AH
C
O
VC 504
VC 504
AJ S 21 18 17 14 11 9 6 5 3 6 P N 2 10 P N 15 CS CE C CN OD A AJ
C
O
O
VC 504
AK 21 19 19 17 15 15 10 10 6 5 4 4 5 4 DM 0 9 8 DM 12 13 A A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
# # EO
Figure 4-19: FFVC900 Package—XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A E A
B V V V B
V
C V C
D V E V D
V
E V E
F V E V F
G E E G
V
H V H
J V E J
V
K V V K
L E E L
M V E V M
N V E N
P V E V P
R E R
T T
U 24 21 U
V 22 23 PL PL PL AU AU V
W 8 7 LP DP DP AU AU W
Y LP LP LP AD Y
AA 34 33 LP LP FP AD BT AA
AB 35 13 15 FP FP FP FP DD AB
AC 38 FP FP DD DD AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A G 9 9 4 3 12 12 12 11 11 G A
V
3 3 3 57 64 65 66 3 3
230 230 130
2 1 3
B 2
230
2
230
2
1
230
10 8 7 4 3 10 10 12 10 55 59 67 68 69 2
130
2
130
3 B
1 0 2
C 1
230
0
230
10 8 7 2 9 11 11 10 9 56 61 70 71
130
2 C
VC 502
0 1
D 1 1 4 4 11 6 5 2 9 7 8 9 7 63 75 1 1 D
C
0 1
O
230 230 130 130
VC 49
V C 47
1 1 0
E 0 0 3 11 12 6 5 8 8 7 8 7 53 60 72 E
C
1 1 0
O
230 229 130 130
VC 49
VC 502
3 3
F 3 3 3 6 6 12 1 1 6 6 6 5 52 54 77 0 0 F
C
3 3
O
229 229 130 129
VC 50
VC 48
VC 502
0 0
G 2 2 2 5 8 9 9 11 5 5 6 5 58 62 74 3 3 G
C
0 0
O
229 229 130 129
V C 47
2 2
H 1 1 2 5 7 8 10 11 2 1 1 3 32 33 73 76 2 2 H
C
2 2
O
229 229 129 129
V C 50
VC 48
1 1 1
J 1 1 7 10 12 12 2 4 4 3 31 41 46 1 1 J
C
1 1 1
O
229 228 129 129
0 1
K 0
229
0
229
0 S 18 23 S 24 19 4 3 2 1 29 36 43 49 0
129
0
129
1 K
VC 501
3 0 0 0
L 15 17 18 23 24 19 4 3 2 1 30 34 38 47 L
C
3 0 0 0
O
228 228 129 129
VC 5 0 1
2 3
M 3 3 15 17 22 20 20 27 40 42 48 3 3 M
C
2 3
O
228 228 128 128
1 2
N 2
228
2 16 16 13 21 22 28 37 39 44 51
128
1
128
2 N
VC 67
1 1
P 1 1 14 14 13 21 26 35 45 50 2 2 P
C
1 1
O
228 228 128 128
0
R 0
228
0 12 11 11 4 2 ES MD MD MS CK
128
0 1
128
1 R
VC 67
V C 503
0 0
T 10 10 12 3 6 4 2 EO MD MD DO 0 0 T
C
0 0
O
228 128 128
VC 67
VC 503
2 3
U 18 18 8 9 9 3 6 PG SR RC DI U
C
C
2 3
O
O
505 505
3
V 23 23 17 17 8 7 7 S 5 5 PI PO PR IN 3
505
3
505
3 V
VC 66
1
W 24 24 15 15 9 9 1 1 DN 2 2 W
C
1
O
505 505
V C 66 2
Y 22 22 13 13 14 11 11 6 6 C
O
5 1
505
1
505
2 Y
VC 66
0 1
AA 21 21 S 14 12 12 S 3 3 5 AA
C
0 1
O
505 505
0
AB S 20 16 10 10 8 4 2 2 G 0
505
0
505
0 AB
AC 19 19 20 16 7 7 8 4 1 1 AC
VC 65
AD 23 23 18 S 9 9 6 2 7 20 23 22 45 44 46 47 60 61 63 62 AD
C
O
VC 500
AE 24 24 17 18 13 12 10 6 1 3 9 12 12 C
O
8 18 25 24 40 P N DM P N DM AE
VC 6 5
VC 44
AF 21 21 17 13 11 12 10 1 4 3 9 11 0 11 21 PA RS AL ZQ A 41 42 43 58 59 AF
C
C
O
O
VC 65
VC 500
VC 504
AG S 20 14 14 11 8 5 5 4 10 10 11 3 23 22 20 24 27 26 AC BA 35 34 33 32 56 57 AG
C
C
O
O
AH 22 19 20 15 7 7 8 S 2 2 7 7 4 10 21 P 25 P N DM BA BG P N DM 51 48 50 AH
VC 64
V C 44
VC 504
VC 504
AJ 22 19 15 16 16 S 9 6 1 8 8 1 12 N 18 29 30 A OD CE 39 36 DM P 49 AJ
C
C
O
O
V C 64
VC 500
AK 23 24 24 18 18 11 11 9 6 1 6 5 5 13 19 DM 17 28 31 A A A BG 37 38 N 53 52 AK
C
C
O
O
VC 64
VC 504
VC 504
AL 23 22 22 13 13 12 12 3 2 6 4 6 14 19 7 16 12 13 15 A C CN A CS 55 54 71 AL
C
C
O
O
AM 21 S 17 14 14 8 8 3 2 4 2 5 16 6 5 4 DM 14 A A A A A OD 68 69 70 AM
VC 504
VC 504
AN 21 19 20 17 16 10 7 5 3 2 1 15 DM P N P N 11 A C CN CS CE 64 P N DM AN
C
C
O
O
AP S 19 20 15 15 16 10 7 5 4 4 3 1 9 17 3 1 2 0 9 8 10 A A A A A 65 66 67 AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
# # EO
Figure 4-21: FFVB1156 Package—XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A E A
B V E V B
C E V C
D V E V D
E E V E
V
F V E V F
G E E G
V
H V E V H
J V V J
V
K V E V K
L V E L
V
M V V M
N V V N
P V E V P
R E R
T T
U 24 21 U
V 22 23 E V V
W 8 7 PL PL PL E W
Y AU AU DP DP E V Y
AA LP BT AU AU E AA
AB LP LP AD AD V AB
AC LP LP LP FP AD AD AC
AD 33 13 15 FP FP DD FP FP AD
AE 35 34 FP FP DD DD AE
AF 38 n n AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 88
VC 67
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
V C 88
VC 67
VC 28
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
VC 68
VC 28
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
VC 68
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
227
VC 67
VC 28
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
227
VC 87
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
227
VC 68
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
227
1
L 1
227
1
227
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
227
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
VC 87
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
227 226 505 505
3 1
P 3
226
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
226
2
226
2 1
227
RC ES 1
505
1
505
2 R
0 0 1
T 1
226
1 0
227
PG EO
505
0
505
1 T
1 1 0
U 1
226
0
226
0 1
226
0
505
0 G 505
0 U
0 0
V 0
226
0
226
47 V
3 1
W 3
225
3
225
3
1
225
44 46 45 59 P N 61 62 W
0
Y 2
225
2 0
225
P N DM 57 DM 60 63 Y
2 1
AA 2
225
1
225
1 1
224
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
225
0
224
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
225
0
225
0
1
223
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
224 223
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
224 224
V C 66
VC 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
224
VC 66
V C 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
224 224
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
224
VC 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
C
0
O
224 223
VC 66
VC 6 5
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
223
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
223 223
AM 1
223
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
223
0
223
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
223
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V V 8 7 LP PL DP AU V
W E LP LP PL AU AU W
V
Y V LP LP BT PL AU Y
AA E 13 15 34 35 LP FP AD AD AA
AB V E FP FP FP FP DD AB
AC E 33 FP FP DD DD AC
AD V R R R R AD
AE AE
AF V AF
AG AG
AH V AH
AJ AJ
AK V AK
AL AL
AM V 38 AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
FFVC1156 Package–XCZU7EV
X-Ref Target - Figure 4-25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 88
VC 67
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
VC 8 8
VC 67
VC 28
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
V C 68
V C 28
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
V C 68
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
227
VC 6 7
V C 28
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
227
VC 87
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
227
VC 68
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
227
1
L 1
227
1
227
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
227
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
V C 87
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
227 226 505 505
3 1
P 3
226
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
226
2
226
2 1
227
RC ES 1
505
1
505
2 R
0 0 1
T 1
226
1 0
227
PG EO
505
0
505
1 T
1 1 0
U 1
226
0
226
0
1
226
0
505
0 G 505
0 U
0 0
V 0
226
0
226
47 V
3 1
W 3
225
3
225
3
1
225
44 46 45 59 P N 61 62 W
0
Y 2
225
2 0
225
P N DM 57 DM 60 63 Y
2 1
AA 2
225
1
225
1 1
224
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
225
0
224
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
225
0
225
0
1
223
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
224 223
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
224 224
VC 66
VC 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
224
VC 66
VC 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
224 224
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
224
VC 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
C
0
O
224 223
VC 66
V C 65
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
223
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
223 223
AM 1
223
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
223
0
223
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
223
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V V 8 7 LP PL DP AU V
W E LP LP PL AU AU W
V
Y V LP LP BT PL AU Y
AA E 13 15 34 35 LP FP AD AD AA
AB V E FP FP FP FP DD AB
AC E 33 FP FP DD DD AC
AD V AD
AE AE
AF V AF
AG AG
AH V AH
AJ AJ
AK V AK
AL AL
AM V 38 AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Figure 4-26: FFVC1156 Package—XCZU7EV Power, Dedicated, and Multi-function Pin Diagram
FFVC1156 Package–XCZU11EG
X-Ref Target - Figure 4-27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 89
VC 68
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
V C 89
VC 68
V C 67
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
VC 69
VC 67
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
VC 6 9
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
228
VC 68
VC 67
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
228
VC 8 8
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
228
VC 6 9
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
228
1
L 1
228
1
228
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
228
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
VC 88
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
228 227 505 505
3 1
P 3
227
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
227
2
227
2 1
228
RC ES 1
505
1
505
2 R
0 0 1
T 1
227
1 0
228
PG EO
505
0
505
1 T
1 1 0
U 1
227
0
227
0 1
227
0
505
0 G 505
0 U
0 0
V 0
227
0
227
47 V
3 1
W 3
226
3
226
3 1
226
44 46 45 59 P N 61 62 W
0
Y 2
226
2 0
226
P N DM 57 DM 60 63 Y
2 1
AA 2
226
1
226
1 1
225
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
226
0
225
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
226
0
226
0
1
224
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
225 224
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
225 225
V C 66
V C 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
225
VC 66
VC 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
225 225
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
225
V C 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
0
O
225 224
VC 66
VC 65
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
224
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
224 224
AM 1
224
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
224
0
224
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
224
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V V 8 7 LP PL DP AU V
W E LP LP PL AU AU W
V
Y V LP LP BT PL AU Y
AA E 13 15 LP FP AD AD AA
AB V E FP FP FP FP DD AB
AC E 33 FP FP DD DD AC
AD V 34 n n n n AD
AE 35 AE
AF V AF
AG AG
AH V 38 AH
AJ AJ
AK V AK
AL AL
AM V AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Figure 4-28: FFVC1156 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
FFVD1156 Package–XCZU21DR
X-Ref Target - Figure 4-29
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 12 20 21 21 23 24 24 24 23 29 26 43 52 54 55 59 63 3
131
3
131
3 A
2 1
B 11 11 12 20 22 22 23 24 22 21 23 20 42 45 48 53 61 62 2
131
2
131
2
131
1 B
VC 501
0
C 10 10 19 19 17 17 18 19 22 21 20 27 44 46 56 57 60 64 1 1 C
C
0
O
131 131
VC 68
VC 502
3 2
D 7 9 9 S 16 16 18 19 S 18 18 41 49 51 74 58 67 0 0 D
C
3 2
O
131 130 130
V C 89
V C 68
1
E 6 6 7 15 13 14 14 17 17 16 16 32 34 47 50 76 66 69 3 3 E
C
1
O
130 130
VC 67
VC 501
0
F 5 8 8 15 13 12 S 15 15 14 14 S 33 39 40 75 65 2 2 1 1 F
C
0
O
130 130 130
VC 67
VC 502
1
G 5 3 3 4 11 11 12 9 13 13 12 12 31 37 36 38 73 68 0 0 G
C
1
O
131 130
V C 89
VC 68
0 3
H 2 2 4 7 10 10 9 11 11 8 6 28 30 35 70 72 71 77 PI H
C
0 3
O
131 129
VC 67
J 1 1 S 7 8 8 6 6 7 10 8 6 2 3 3 G J
V
PO 3 3
C
O
129
1 2
K 2 4 4 10 2 4 4 5 9 7 10 5 4 4 2 MD
130
1
129
2 K
V C 88
L 2 6 8 10 2 3 5 9 S 5 1 1 EO MD ES 2 2 L
C
O
129
VC 88
VC 503
0 1
M 1 5 6 8 1 1 3 MD MD M
C
0 1
O
130 129
N 1 5 7 9 11 11 CK DI MS 1
129
1 N
VC 503
1 0
P 3 3 7 9 12 12 RC PG P
C
1 0
O
129 129
R 2 3 3 6 7 10 10 PR DO 0
129
0 R
0 3
T 2 4 5 6 7 11 11 IN SR DN
129
0
128
3 T
U 1 1 4 5 VC 87 8 8 12 12 3 3 U
C
O
128
V C 87
1 2
V 24 24 S S 9 9 V
C
1 2
O
128 128
W 23 23 18 18 15 17 17 2
128
2 W
0 1
Y 21 22 22 14 14 15 16 128
0
128
1 Y
AA 21 19 12 13 13 16 1
128
1 AA
VC 66
0
AB 20 20 19 12 11 11 10 10 AB
C
0
O
128
VC 66
AC 2 2 5 S 9 9 8 0 0 AC
C
O
128
3
AD 3 4 5 6 7 7 8 11 9 7 4 0
505
3 AD
VC 66
VC 500
AE 1 3 4 6 24 24 8 5 3 2 35 40 45 44 3 3 AE
C
C
O
505
V C 65
3 2
AF 1 10 22 23 23 20 15 13 10 6 1 BA 36 32 41 P 46 AF
C
3 2
O
505 505
VC 500
AG 8 8 10 22 21 21 20 19 17 16 14 12 A A PA AL ZQ 37 P N N DM 2 2 AG
C
O
505
2 1
AH 9 9 17 17 S 18 19 18 19 20 DM 23 22 A A BG RS DM 33 43 42 47
505
2
505
1 AH
VC 65
VC 504
VC 504
AJ 12 12 14 14 18 16 16 21 23 21 N P A A AC BA 39 38 34 53 48 1 1 AJ
C
C
O
O
505
VC 65
1 0
AK 7 11 11 13 13 15 15 22 24 25 20 19 18 A C BG A 64 65 54 P 50 AK
C
1 0
O
505 505
VC 504
VC 504
AL 7 S 5 S DM 7 9 8 25 24 17 16 CN A CS A 66 P 55 N 49 G 0 0 AL
C
C
O
O
505
0
AM 4 6 6 5 6 P 4 3 P 15 27 P 31 C A A OD CE 68 N DM 51
505
0 AM
VC 504
VC 504
AN 4 3 2 2 5 N 10 12 N DM N DM 30 CN A A CS OD DM 71 52 57 58 P DM AN
C
C
O
O
AP 3 1 1 1 2 0 11 13 14 26 29 28 A A A A CE 67 70 69 56 59 60 N 61 63 62 AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A V A
B V B
C V C
D V D
E V E
F E F
G E G
H E H
VCC
J FEC E J
VCC
K FEC E K
VCC
V
L FEC L
VCC
M n FEC V M
VCC
V
N n FEC N
VCC
P n FEC V P
VCC
R FEC E R
VCC
T FEC V T
VCC
U 24 21 FEC AU AU E U
VCC
V n 22 23 FEC AU AD AD V V
VCC
W 8 7 FEC
AU PL E W
VCC
Y FEC BT PL LP V Y
VCC
AA FEC DP PL LP AA
VCC
AB FEC
DD DP LP LP LP V AB
VCC
AC FEC
FP FP FP FP LP AC
VCC
AD 13 FEC
DD DD FP FP FP AD
VCC
AE 35 34 15 FEC AE
VCC
AF 33 FEC V AF
AG E AG
AH V AH
AJ E AJ
AK V AK
AL AL
AM 38 AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Figure 4-30: FFVD1156 Package—XCZU21DR Power, Dedicated, and Multi-function Pin Diagram
VC 500
C 1 229 1 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
VC 88
VC 502
E 0 229 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
V C 89
VC 5 0 1
VC 502
G 3 228 3 8 8 6 4 G G
V
4 11 16 13 31 33 52 56 3 3
C
O
O
128
V C 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 2 228 2 C229C 11 12 3 3 2 0 1 28 EO 2
128
2 J
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
128
1
128
2 K
L 1 228 1 C228C MD MD 1
128
1 L
0 1
M MD RC DI
128
0
128
1 M
VC 503
N 0 228 0 S 228 S PR MS 0 0 N
C
O
128
3 0
P PG CK
505
3
128
0 P
R IN SR ES 3
505
3 R
VC 503
2 3
T 3 227 3 DN DO G T
C
2 3
O
505 505
U 2
505
2 U
1 2
V 1 227 1 C227C 505
1
505
2 V
W 1
505
1 W
0 1
Y 3 226 3 C226C 505
0
505
1 Y
AA 0
505
0 AA
0
AB 1 226 1 C225C 46 44
505
0 AB
AC 19 22 22 23 47 45 P N AC
AD 3 225 3 C224C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
V C 65
VC 504
AF 1 225 1 V 227 V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
O
VC 504
AG V 226 V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
V C 66
AH 3 224 3 V 225 V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
VC 65
AJ V 224 V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
V C 65
VC 504
AK 1 224 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
AM 3 3 10 10 13 12 14 14 1 2 4 5 6 DM 1 10 15 A A CN A CS OD 65 69 AM
VC 504
AN 6 6 4 4 9 9 S 12 8 8 1 2 5 6 5 P 11 P 14 A A C A CS P N 70 AN
C
O
VC 504
AP 5 5 2 2 1 1 11 11 7 7 3 3 6 4 N 2 0 N A A A CN OD CE 64 68 AP
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC DAC DAC E A
B DAC DAC DAC DAC DAC B
C DAC DAC DAC DAC DAC E C
DAC DAC DAC
D DAC DAC DAC VTT DAC AUX AUX V D
DAC DAC DAC
E DAC VTT DAC AUX AUX E E
DAC
F DAC DAC DAC VTT DAC DAC V F
DAC DAC DAC
G DAC VTT DAC VCC VCC n G
DAC
H DAC DAC DAC DAC DAC DAC
VCC n n n V H
DAC VCC
V
J DAC DAC VCC DAC FEC n J
DAC VCC VCC
K DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V K
DAC DAC VCC
V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
M DAC DAC DAC DAC DAC DAC
VCC
DAC
AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
P DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC P
VCC
R ADC ADC ADC DAC DAC DAC DAC DAC FEC E R
VCC VCC
T ADC ADC ADC DAC DAC DAC AMS 24 21 FEC T
VCC
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 FEC AU AU AU E U
VCC VCC
V ADC ADC ADC ADC AMS 8 7 FEC BT AU V V
ADC VCC
W ADC ADC ADC ADC ADC ADC
VCC
ADC
FEC
AD AD PL E W
ADC VCC VCC
Y ADC ADC VCC ADC AMS FEC FP DP DP PL PL V Y
ADC VCC
AA ADC ADC ADC ADC ADC ADC VCC ADC FEC FP LP LP LP AA
ADC VCC VCC
AB ADC ADC
VCC
ADC
AMS FEC
FP FP LP LP LP V AB
ADC ADC VCC
AC ADC ADC ADC ADC ADC ADC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC
VCC
ADC
AMS 13 34 FEC
FP DD DD AD
ADC VCC
AE ADC ADC ADC ADC ADC ADC VCC ADC 35 FEC AE
VCC
AF ADC ADC ADC FEC AF
ADC
AG ADC ADC ADC ADC AUX AG
ADC
AH ADC ADC AUX AH
ADC
AJ ADC ADC ADC ADC AUX AJ
ADC
AK ADC ADC ADC ADC AUX AK
AL ADC ADC ADC 38 AL
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 2 229 3 229 3 3 12 11 11 14 24 40 43 46 50 60 71 73
129
3 A
2
B 2 3 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3
129
3
129
2 B
VC 5 0 0
C 1 229 1 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
V C 88
VC 502
E 0 229 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
VC 89
VC 501
VC 502
G 3 228 3 8 8 6 4 G G
V
4 11 16 13 31 33 52 56 3 3
C
O
O
128
V C 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 2 228 2 C C 11 12 3 3 2 0 1 28 EO 2
128
2 J
229
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
128
1
128
2 K
L 1 228 1 C C MD MD 1
128
1 L
228
0 1
M MD RC DI
128
0
128
1 M
VC 503
N 0 228 0 S 228 S PR MS 0 0 N
C
O
128
3 0
P PG CK
505
3
128
0 P
R IN SR ES 3
505
3 R
VC 503
2 3
T 3 227 3 DN DO G T
C
2 3
O
505 505
U 2
505
2 U
1 2
V 1 227 1 C C 505
1
505
2 V
227
W 1
505
1 W
0 1
Y 3 226 3 C C 505
0
505
1 Y
226
AA 0
505
0 AA
0
AB 1 226 1 C C 46 44
505
0 AB
225
AC 19 22 22 23 47 45 P N AC
AD 3 225 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
224
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
V C 65
VC 504
AF 1 225 1 V 227 V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
V C 504
AG V 226 V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
VC 66
AH 3 224 3 V 225 V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
VC 65
AJ V 224 V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
V C 65
VC 504
AK 1 224 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
AM 3 3 10 10 13 12 14 14 1 2 4 5 6 DM 1 10 15 A A CN A CS OD 65 69 AM
VC 504
AN 6 6 4 4 9 9 S 12 8 8 1 2 5 6 5 P 11 P 14 A A C A CS P N 70 AN
C
O
VC 504
AP 5 5 2 2 1 1 11 11 7 7 3 3 6 4 N 2 0 N A A A CN OD CE 64 68 AP
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DO
Figure 4-33: FFVE1156 and FSVE1156 Packages—XCZU27DR and XCZU28DR I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC DAC DAC E A
B DAC DAC DAC DAC DAC B
C DAC DAC DAC DAC DAC E C
DAC DAC DAC
D DAC DAC DAC VTT DAC AUX AUX V D
DAC DAC DAC
E DAC VTT DAC AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC n G
DAC
H DAC DAC DAC DAC DAC DAC
VCC n n n V H
DAC VCC
V
J DAC DAC VCC DAC FEC n J
DAC VCC VCC
K DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V K
DAC DAC VCC
V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
M DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
P DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC P
VCC
R ADC ADC ADC DAC DAC DAC DAC DAC FEC E R
VCC VCC
T ADC ADC ADC DAC DAC DAC AMS 24 21 FEC T
VCC
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 FEC AU AU AU E U
VCC VCC
V ADC ADC ADC ADC AMS 8 7 FEC BT AU V V
ADC VCC
W ADC ADC ADC ADC ADC ADC VCC ADC FEC AD AD PL E W
ADC VCC VCC
Y ADC ADC VCC ADC AMS FEC FP DP DP PL PL V Y
ADC VCC
AA ADC ADC ADC ADC ADC ADC VCC ADC FEC FP LP LP LP AA
ADC VCC VCC
AB ADC ADC VCC ADC AMS FEC FP FP LP LP LP V AB
ADC ADC VCC
AC ADC ADC ADC ADC ADC ADC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC VCC ADC AMS 13 34 FEC FP DD DD AD
ADC VCC
AE ADC ADC ADC ADC ADC ADC VCC ADC 35 FEC AE
VCC
AF ADC ADC ADC FEC AF
ADC
AG ADC ADC ADC ADC AUX AG
ADC
AH ADC ADC AUX AH
ADC
AJ ADC ADC ADC ADC AUX AJ
ADC
AK ADC ADC ADC ADC AUX AK
AL ADC ADC ADC 38 AL
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Figure 4-34: FFVE1156 and FSVE1156 Packages—XCZU27DR and XCZU28DR Power, Dedicated,
and Multi-function Pin Diagram
FFVB1517 Package–XCZU11EG
X-Ref Target - Figure 4-35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B 24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
C 20 20 21 19 S 19 21 21 17 17 23 21 22 21 S 20 C
VC 71
D S 18 18 15 18 18 19 S 14 14 15 21 23 23 21 20 D
C
O
VC 70
VC 69
VC 68
E S 17 17 15 16 15 15 13 13 15 19 18 18 17 19 19 E
C
O
O
F 13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
V C 71
G 10 11 9 14 14 7 17 17 14 13 10 11 11 8 S 13 13 16 15 G
C
O
VC 9 0
VC 70
VC 69
VC 68
H 10 11 9 12 12 7 S 12 12 11 10 9 8 10 10 12 6 6 15 H
C
O
O
J 9 12 S 11 11 8 10 10 11 7 7 9 11 11 12 4 J
VC 71
K 8 8 9 12 10 8 8 8 7 9 9 6 6 5 8 S 9 2 2 4 K
C
O
V C 90
VC 70
VC 69
VC 68
L 7 7 4 2 10 5 5 7 6 5 4 1 5 8 9 5 3 3 L
C
O
O
M 6 6 3 4 2 3 3 6 4 4 6 5 4 1 7 7 5 1 1 M
3 1
N 3
227
3
227
3
1
227
5 5 3 1 1 1 6 2 2 2 2 2 3 3 9 9 7 3 3 N
VC 89
VC 67
2
P 2 2 11 12 12 1 4 4 2 3 3 19 S 15 15 11 11 7 5 1 P
C
2
O
227 227
VC 67
1 0
R 1 1 11 10 10 1 1 23 S 19 17 13 13 12 12 5 6 1 R
C
1 0
O
227 227 227
0
T 0
227
0
227
0 9 9 23 21 21 17 18 18 14 S 8 6 4 T
VC 67
3 1
U 3 3 8 6 5 24 24 16 16 14 10 10 8 4 2 U
C
3 1
O
226 226 226
VC 502
2
V G 8 6 5 20 20 22 22 2 V
V
2 2 72 69 73 70 53 60 62
C
2
O
226 226
VC 89
VC 503
1 0
W 1 1 7 1 MD SR MD 64 65 68 74 58 54 61 63 66 W
C
1 0
O
226 226 226
VC 502
0
Y 0 0 7 3 1 RC PG EO 59 67 55 56 52 57 71 75 77 76 Y
C
0
O
226 226
3 1
AA 3
225
3
225
3 1
225
4 3 MD MD DO ES AA
VC 503
2 1 2 3
AB 2 2 4 2 2 PI PO PR AB
C
2 1 2 3
O
225 225 505 505 505
1 0 3
AC 1
225
1
225
1 0
225
12 10 10 MS DN IN DI 3
505
3
505
3 AC
VC 8 8
0 0 2
AD 0 0 12 9 CK 2 2 AD
C
0 0 2
O
VC 501
1 0
AG 1 1 7 7 5 5 26 33 39 43 48 AG
C
1 0
O
224 224 224
V C 88
0
AH 0 0 4 6 6 1 32 35 40 44 47 46 44 45 62 P 59 58 AH
C
0
O
224 224
VC 504
AJ 21 21 4 3 1 5 5 2 31 34 37 45 49 P N DM 63 61 N 56 AJ
C
O
VC 501
AK 1 3 8 8 10 15 15 17 17 19 23 3 2 2 1 4 2 29 36 41 46 50 42 43 41 40 60 DM 57 AK
C
O
VC 65
VC 65
VC 504
AL 1 3 5 10 11 13 13 19 22 23 3 3 1 4 0 3 10 12 51 19 27 26 A AL AC ZQ 32 33 48 50 AL
C
C
O
O
VC 65
V C 66
AM 5 S 11 12 S 16 S 22 24 6 6 8 8 2 1 14 20 DM 18 P 31 A BG BG 34 35 P 49 51 AM
C
C
O
VC 504
VC 504
AN 4 4 6 6 12 14 14 16 20 20 24 9 7 7 10 10 4 13 17 22 17 25 N 30 A BA RS DM N DM P N AN
C
O
O
VC 500
AP 2 2 7 7 9 9 18 18 21 9 11 12 12 S 5 16 15 21 P 16 24 28 A A PA 37 38 36 52 54 AP
C
O
VC 66
VC 504
VC 504
AR 2 4 8 8 10 17 17 21 23 23 S 11 14 14 16 6 19 23 23 N 14 DM 29 BA A A OD 39 69 53 55 AR
C
C
O
O
V C 64
VC 64
AT 1 2 4 12 12 10 13 15 S 19 19 15 13 13 16 18 7 20 25 2 0 13 12 15 A A C CE 68 70 71 AT
C
C
O
VC 64
VC 500
VC 504
AU 1 3 6 11 11 13 S 15 24 20 19 15 20 17 17 18 9 22 3 1 P DM P N A CN A CS DM P N AU
C
C
O
O
VC 66
AV 3 5 6 9 14 14 18 24 22 20 19 20 S 22 22 11 18 24 DM N 9 8 11 A A C CN 64 65 66 67 AV
C
O
AW 5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21 6 5 4 7 10 A A A A A CS CE OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n n n n n n n n n n n n n A
B n n n n n n n n n n n n n n n B
C n n n n n n n n n n n n n n n n n C
D n n n n n n n n n n n n n n n n n D
E n n n n n n n n n n n n n n n n E
F n n n n n n n n n n n n n n n F
G n n n n n n n n n n n n n G
H n n n n n n n n n n n n n n H
J n n n n n n n n n n n n n n n J
K n n n n n n n n n n n K
L n n n n n n n n n n n n n L
M n n n M
N E n n n N
P V E n n P
R E R
T V E T
U V U
V V V
W V W
V
Y V 24 21 Y
AA V 22 23 AA
V
AB V 8 7 E AB
AC V V AC
AD V E PL PL BT E AD
AE E PL DP DP V AE
AF V E LP LP LP AU AU AF
AG E LP AD AD AU AU AG
AH V 15 13 LP LP FP FP AH
AJ FP FP FP DD AJ
AK 33 FP FP DD DD AK
AL 34 AL
AM 38 35 AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 23 23 S 17 17 S 8 10 10 4 2 2 10 10 24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B 21 19 19 15 15 11 9 9 8 4 6 6 S 8 8 24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
VC 74
C 21 20 20 S 13 13 11 12 7 7 1 1 11 11 7 7 20 20 21 19 S 19 21 21 17 17 23 21 22 21 S 20 C
C
O
V C 74
VC 72
VC 71
D 24 24 18 16 14 14 12 3 3 1 3 3 12 12 9 S 18 18 15 18 18 19 S 14 14 15 21 23 23 21 20 D
C
O
O
VC 74
VC 70
VC 69
VC 68
E 22 22 18 16 5 5 4 1 5 5 14 14 9 S 17 17 15 16 15 15 13 13 15 19 18 18 17 19 19 E
C
O
O
F 23 23 21 19 19 6 6 4 2 2 16 16 13 13 13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
VC 73
V C 71
G S 21 20 20 11 9 9 5 5 10 11 18 18 S 9 14 14 7 17 17 14 13 10 11 11 8 S 13 13 16 15 G
C
O
O
VC 7 3
VC 93
VC 70
VC 6 9
V C 68
H 24 24 22 22 11 7 7 3 10 11 15 17 17 9 12 12 7 S 12 12 11 10 9 8 10 10 12 6 6 15 H
C
O
O
VC 73
VC 72
J 17 17 13 13 12 12 3 6 2 2 9 12 15 19 24 S 11 11 8 10 10 11 7 7 9 11 11 12 4 J
C
O
VC 71
K 15 15 14 14 10 8 1 6 8 8 9 12 19 20 24 10 8 8 8 7 9 9 6 6 5 8 S 9 2 2 4 K
C
O
VC 93
V C 70
VC 69
V C 68
L S 18 18 16 16 S 10 8 1 4 4 7 7 4 2 21 20 10 5 5 7 6 5 4 1 5 8 9 5 3 3 L
C
O
O
VC 72
M 6 6 3 4 2 21 22 3 3 6 4 4 6 5 4 1 7 7 5 1 1 M
C
O
3 1
N 3
227
3
227
3
1
227
5 5 3 1 23 23 22 1 1 6 2 2 2 2 2 3 3 9 9 7 3 3 N
VC 91
VC 67
2
P 2 2 11 12 12 1 S 4 4 2 3 3 19 S 15 15 11 11 7 5 1 P
C
2
O
227 227
VC 67
1 0
R 1 1 11 10 10 1 1 23 S 19 17 13 13 12 12 5 6 1 R
C
1 0
O
227 227 227
0
T 0
227
0
227
0 9 9 23 21 21 17 18 18 14 S 8 6 4 T
VC 67
3 1
U 3 3 8 6 5 24 24 16 16 14 10 10 8 4 2 U
C
3 1
O
226 226 226
VC 502
2
V G 8 6 5 20 20 22 22 2 V
V
2 2 72 69 73 70 53 60 62
C
2
O
226 226
VC 91
VC 503
1 0
W 1 1 7 1 MD SR MD 64 65 68 74 58 54 61 63 66 W
C
1 0
O
226 226 226
VC 502
0
Y 0 0 7 3 1 RC PG EO 59 67 55 56 52 57 71 75 77 76 Y
C
0
O
226 226
3 1
AA 3
225
3
225
3 1
225
4 3 MD MD DO ES AA
VC 503
2 1 2 3
AB 2 2 4 2 2 PI PO PR AB
C
2 1 2 3
O
225 225 505 505 505
1 0 3
AC 1
225
1
225
1
0
225
12 10 10 MS DN IN DI 3
505
3
505
3 AC
VC 90
0 0 2
AD 0 0 12 9 CK 2 2 AD
C
0 0 2
O
VC 501
1 0
AG 1 1 7 7 5 5 26 33 39 43 48 AG
C
1 0
O
224 224 224
VC 90
0
AH 0 0 4 6 6 1 32 35 40 44 47 46 44 45 62 P 59 58 AH
C
0
O
224 224
VC 504
AJ 21 21 4 3 1 5 5 2 31 34 37 45 49 P N DM 63 61 N 56 AJ
C
O
VC 501
AK 1 3 8 8 10 15 15 17 17 19 23 3 2 2 1 4 2 29 36 41 46 50 42 43 41 40 60 DM 57 AK
C
O
VC 65
VC 6 5
VC 504
AL 1 3 5 10 11 13 13 19 22 23 3 3 1 4 0 3 10 12 51 19 27 26 A AL AC ZQ 32 33 48 50 AL
C
C
O
O
VC 65
VC 6 6
AM 5 S 11 12 S 16 S 22 24 6 6 8 8 2 1 14 20 DM 18 P 31 A BG BG 34 35 P 49 51 AM
C
C
O
VC 504
VC 504
AN 4 4 6 6 12 14 14 16 20 20 24 9 7 7 10 10 4 13 17 22 17 25 N 30 A BA RS DM N DM P N AN
C
O
O
V C 500
AP 2 2 7 7 9 9 18 18 21 9 11 12 12 S 5 16 15 21 P 16 24 28 A A PA 37 38 36 52 54 AP
C
O
VC 66
VC 504
VC 504
AR 2 4 8 8 10 17 17 21 23 23 S 11 14 14 16 6 19 23 23 N 14 DM 29 BA A A OD 39 69 53 55 AR
C
C
O
O
VC 64
VC 6 4
AT 1 2 4 12 12 10 13 15 S 19 19 15 13 13 16 18 7 20 25 2 0 13 12 15 A A C CE 68 70 71 AT
C
C
O
VC 64
VC 500
VC 504
AU 1 3 6 11 11 13 S 15 24 20 19 15 20 17 17 18 9 22 3 1 P DM P N A CN A CS DM P N AU
C
C
O
O
VC 66
AV 3 5 6 9 14 14 18 24 22 20 19 20 S 22 22 11 18 24 DM N 9 8 11 A A C CN 64 65 66 67 AV
C
O
AW 5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21 6 5 4 7 10 A A A A A CS CE OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N E N
P V E P
R E R
T V E T
U V U
V V V
W V W
V
Y V 24 21 Y
AA V 22 23 AA
V
AB V 8 7 E AB
AC V V AC
AD V E PL PL BT E AD
AE E PL DP DP V AE
AF V E LP LP LP AU AU AF
AG E LP AD AD AU AU AG
AH V 15 13 LP LP FP FP AH
AJ FP FP FP DD AJ
AK 33 FP FP DD DD AK
AL 34 AL
AM 38 35 AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
B 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
VC 67
VC 68
VC 28
C 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
O
VC 27
D 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
O
V C 87
VC 27
E 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
O
O
V C 88
VC 67
VC 68
VC 28
F 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
O
V C 27
G 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
O
VC 87
H 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
O
VC 88
VC 67
VC 6 8
VC 28
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
228 228
2
K 2
228
2
228
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
228 228
0
M 0
228
0
228
0 1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3
N 3
227
3
227
3 1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2
O
227 227
1
R 1
227
1
227
1 16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
227
0
227
0 1
228
25 15 11 T
3 0 3
U 3
226
3
226
3 0
228
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
226
2
226
2 1
227
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
226 226 227 505 505
0 1 2
Y 0
226
0
226
0 1
226
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
225
3
225
3 0
226
17
505
1
505
0 AA
2 1 0
AB 2
225
2
225
2 1
225 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
225 225
0 0
AD 0
225
0
225
0 0
225
46 42 45 57 56 P 63 AD
3 1
AE 3
224
3
224
3 1
224
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
224 224 224
1 1
AG 1
224
1
224
1 1
223
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
224
0
224
0
0
223
23 22 S S 22 23 22 S 23 MD MD MD ES EO 35 38 52 P N 51 AH
VC 503
3
AJ 3 3 21 23 24 22 20 22 21 21 22 23 21 21 MD PO PI DN A 37 DM 55 DM 50 AJ
C
3
O
223 223
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
223 223
VC 63
VC 64
VC 504
1
AL 1 1 23 21 S 17 15 18 9 9 19 8 16 16 17 S 23 18 ZQ A BG AC 32 39 70 DM AL
C
C
1
O
O
223 223
0
AM 0
223
0
223
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
VC 63
VC 64
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 6 6
AR 3 5 16 16 17 S 20 20 9 10 11 12 S 15 13 14 8 10 12 9 4 2 1 DM P N A C A A A AR
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
VC 63
VC 64
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
VC 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n V n n A
B n n n n V B
C n n V n n C
D n n n n V D
E n n V n n E
F n n n n V F
G n n V n n G
H n n n n E H
J V J
K E K
L V L
M E n n M
N V E n n N
P V n n E P
R V E n n R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
AA V E 8 7 PL PL PL DP DP E V AA
V
AB V LP LP LP LP AD AU E AB
AC V E LP LP FP BT AD AU AC
V
AD V FP FP FP FP AU AU AD
AE V E FP FP DD DD DD AE
V
AF V R R R R AF
AG V E 13 15 R R AG
AH E 33 AH
AJ V 34 AJ
AK E 35 AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV 38 AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
FFVF1517 Package–XCZU7EV
X-Ref Target - Figure 4-41
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
B 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
VC 67
VC 68
VC 28
C 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
O
VC 27
D 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
O
V C 87
VC 27
E 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
O
O
V C 88
VC 67
VC 68
VC 28
F 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
O
V C 27
G 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
O
VC 87
H 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
O
VC 88
VC 67
VC 6 8
VC 28
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
228 228
2
K 2
228
2
228
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
228 228
0
M 0
228
0
228
0 1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3
N 3
227
3
227
3 1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2
O
227 227
1
R 1
227
1
227
1 16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
227
0
227
0 1
228
25 15 11 T
3 0 3
U 3
226
3
226
3 0
228
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
226
2
226
2 1
227
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
226 226 227 505 505
0 1 2
Y 0
226
0
226
0 1
226
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
225
3
225
3 0
226
17
505
1
505
0 AA
2 1 0
AB 2
225
2
225
2 1
225 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
225 225
0 0
AD 0
225
0
225
0 0
225
46 42 45 57 56 P 63 AD
3 1
AE 3
224
3
224
3 1
224
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
224 224 224
1 1
AG 1
224
1
224
1 1
223
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
224
0
224
0
0
223
23 22 S S 22 23 22 S 23 MD MD MD ES EO 35 38 52 P N 51 AH
VC 503
3
AJ 3 3 21 23 24 22 20 22 21 21 22 23 21 21 MD PO PI DN A 37 DM 55 DM 50 AJ
C
3
O
223 223
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
223 223
VC 63
VC 64
VC 504
1
AL 1 1 23 21 S 17 15 18 9 9 19 8 16 16 17 S 23 18 ZQ A BG AC 32 39 70 DM AL
C
C
1
O
O
223 223
0
AM 0
223
0
223
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
VC 63
VC 64
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 6 6
AR 3 5 16 16 17 S 20 20 9 10 11 12 S 15 13 14 8 10 12 9 4 2 1 DM P N A C A A A AR
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
VC 63
VC 64
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
VC 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n V n n A
B n n n n V B
C n n V n n C
D n n n n V D
E n n V n n E
F n n n n V F
G n n V n n G
H n n n n E H
J V J
K E K
L V L
M E n n M
N V E n n N
P V n n E P
R V E n n R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
AA V E 8 7 PL PL PL DP DP E V AA
V
AB V LP LP LP LP AD AU E AB
AC V E LP LP FP BT AD AU AC
V
AD V FP FP FP FP AU AU AD
AE V E FP FP DD DD DD AE
V
AF V AF
AG V E 13 15 AG
AH E 33 AH
AJ V 34 AJ
AK E 35 AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV 38 AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Figure 4-42: FFVF1517 Package—XCZU7EV Power, Dedicated, and Multi-function Pin Diagram
FFVF1517 Package–XCZU11EG
X-Ref Target - Figure 4-43
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
3
A 3
231
3
231
3 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
2
B 2
231
2
231
2 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
V C 70
VC 71
V C 69
1
C 1 1 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
1
O
231 231
VC 68
0
D 0 0 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
0
O
231 231
VC 8 8
VC 68
3
E 3 3 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
3
O
230 230
VC 89
V C 70
VC 71
V C 69
2
F 2 2 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
2
O
230 230
VC 68
1
G 1 1 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
1
O
230 230
VC 88
0
H 0 0 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
0
O
230 230
VC 89
V C 70
V C 71
VC 69
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
229 229
2
K 2
229
2
229
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
229 229
0 1
M 0
229
0
229
0 1
231
1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3 0
N 3
228
3
228
3 0
231
1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2 1
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2 1
O
228 228 230
1 0
R 1
228
1
228
1 0
230
16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
228
0
228
0 1
229
25 15 11 T
3 0 3
U 3
227
3
227
3 0
229
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
227
2
227
2
1
228
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
227 227 228 505 505
0 1 2
Y 0
227
0
227
0 1
227
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
226
3
226
3 0
227
17
505
1
505
0 AA
2 1 0
AB 2
226
2
226
2 1
226 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
226 226
0 0
AD 0
226
0
226
0 0
226
46 42 45 57 56 P 63 AD
3 1
AE 3
225
3
225
3 1
225
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
225 225 225
1 1
AG 1
225
1
225
1 1
224
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
225
0
225
0
0
224
23 22 S S 22 23 22 S 23 MD MD MD ES EO 35 38 52 P N 51 AH
VC 503
3
AJ 3 3 21 23 24 22 20 22 21 21 22 23 21 21 MD PO PI DN A 37 DM 55 DM 50 AJ
C
3
O
224 224
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
224 224
VC 64
VC 67
VC 504
1
AL 1 1 23 21 S 17 15 18 9 9 19 8 16 16 17 S 23 18 ZQ A BG AC 32 39 70 DM AL
C
C
1
O
O
224 224
0
AM 0
224
0
224
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
V C 64
V C 67
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 66
AR 3 5 16 16 17 S 20 20 9 10 11 12 S 15 13 14 8 10 12 9 4 2 1 DM P N A C A A A AR
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
V C 64
VC 67
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
V C 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A V A
B V B
C V C
D V D
E V E
F V F
G V G
H E H
J V J
K E K
L V L
M E M
N V E N
P V E P
R V E R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
AA V E 8 7 PL PL PL DP DP E V AA
V
AB V LP LP LP LP AD AU E AB
AC V E LP LP FP BT AD AU AC
V
AD V FP FP FP FP AU AU AD
AE V E FP FP DD DD DD AE
V
AF V n n n n AF
AG V E 13 15 n n AG
AH E 33 35 AH
AJ V 34 AJ
AK E AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Figure 4-44: FFVF1517 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 A
VC 87
VC 501
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 B
C
O
O
V C 87
C 3 229 3 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 C
C
O
VC 68
V C 67
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 D
C
O
O
VC 69
VC 501
E 2 229 2 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 E
C
O
O
VC 69
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 F
C
O
VC 68
VC 67
G 1 229 1 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 G
C
O
O
VC 68
VC 502
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 H
C
O
O
V C 69
VC 502
J 0 229 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
O
O
129
VC 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 G K
V
62 64 70 73
C
3
O
129
2
L 3 228 3 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2
129
2
129
2 L
1
M 5 3 1 2 6 S 2 3 54 69 74 76
129
1 M
0
N 2 228 2 C229C 3 1 2 6 2 1 1 52 66 75 12 1
129
1
129
0 N
P 1 11 14 0
129
0 P
3
R 1 228 1 C228C 0 9 13 16 3
128
3
128
3 R
T 7 3 17 2
128
2 T
VC 500
2
U 0 228 0 S 228 S 8 15 23 U
C
2
O
128
1
V 4 10 20 21
129
1 1
128
1 V
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 227 3 C227C 2 18 22 24
128
1 0
128
0 Y
0 0
AA 5 PG CK
128
0
128
0 AA
AB 1 227 1 C226C R IN DN SR PR MD MD AB
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 226 3 C225C MS DI DO 3
505
3 AD
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 226 1 C224C S 18 18 24 24 EO PO 62 2
505
2 AF
1 1
AG 23 S 16 23 22 63 61
505
1
505
1 AG
VC 65
AH 3 225 3 V 227 V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
505
VC 64
0 0
AJ V 226 V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
505 505
VC 66
AK 1 225 1 V 225 V 21 19 22 14 14 19 S C
O 20 20 23 21 24 27 26 A 57 56 G 0
505
0 AK
AL V 224 V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
VC 65
VC 64
VC 504
AM 3 224 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
VC 66
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
VC 84
VC 504
VC 504
AP 1 224 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
VC 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
VC 66
VC 504
VC 504
AT 7 8 8 S 6 4 4 5 5 7 9 S 8 10 P 8 N DM CN A A A P DM 64 N 66 AT
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V r r A
B DAC DAC DAC r r V R R B
C DAC V r r R R C
D DAC DAC DAC r r V R R D
E DAC DAC V r r R R E
F DAC DAC DAC DAC r r V R R F
G DAC DAC V r r R R G
DAC
H DAC DAC DAC
VTT r r V R R H
DAC
J DAC VTT V R R J
DAC
K DAC DAC DAC VTT DAC V K
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
M DAC DAC DAC DAC DAC DAC
AUX
DAC
VCC
DAC
FEC r r E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
P DAC DAC DAC DAC DAC DAC AUX DAC VCC SUB FEC r r V P
DAC DAC VCC VCC
V
R DAC DAC AUX DAC VCC DAC AMS FEC V R
DAC DAC VCC
T DAC DAC DAC DAC DAC DAC AUX DAC VCC DAC FEC r r V T
DAC DAC VCC VCC
V
U DAC DAC AUX DAC VCC DAC AMS FEC r r V U
DAC VCC
V DAC DAC DAC DAC DAC DAC DAC DAC
VCC
DAC
FEC E V
DAC VCC VCC
W ADC ADC ADC ADC ADC ADC DAC
VCC
DAC
AMS 24 21 FEC E V W
VCC
Y ADC ADC DAC DAC DAC DAC 22 23 FEC E Y
VCC VCC
AA ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AMS 8 7 FEC V AA
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AC ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS FEC BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC
AUX
ADC
VCC
ADC
FEC
DP DP PL AU E AD
ADC ADC ADC VCC VCC
AE ADC ADC ADC ADC ADC ADC AUX ADC VCC SUB AMS FEC LP PL PL AD V AE
ADC ADC VCC
AF ADC ADC AUX ADC VCC ADC 13 15 FEC FP DP LP AD E AF
ADC ADC VCC VCC
AG ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS 33 FEC FP LP LP DD V AG
ADC ADC VCC
AH ADC ADC AUX ADC VCC ADC 34 FEC FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC AUX ADC VCC ADC AMS 35 FEC FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 3
131
3 A
VC 87
VC 5 0 1
3
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 2 2 B
C
3
O
131 131
VC 87
2
C 3 229 3 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 1 1 C
C
2
O
131 131
V C 68
VC 67
1
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 0 0 D
C
1
O
131 131
VC 69
VC 501
0
E 2 229 2 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 3 3 E
C
0
O
130 131
V C 69
3
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 2 2 F
C
3
O
130 130
V C 68
VC 67
2
G 1 229 1 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 1 1 G
C
2
O
130 130
V C 68
VC 502
1
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 0 0 H
C
1
O
130 130
VC 69
VC 502
0
J 0 229 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
0
O
129 130
V C 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 G K
V
62 64 70 73
C
3
O
129
2
L 3 228 3 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2
129
2
129
2 L
1 1
M 5 3 1 2 6 S 2 3 54 69 74 76
131
1
129
1 M
0
N 2 228 2 C C 3 1 2 6 2 1 1 52 66 75 12 1
129
1
129
0 N
229
0
P 1 11 14
131
0 0
129
0 P
3
R 1 228 1 C C 0 9 13 16 3
128
3
128
3 R
228
1
T 7 3 17
130
1 2
128
2 T
VC 500
0 2
U 0 228 0 S 228 S 8 15 23 U
C
0 2
O
130 128
1
V 4 10 20 21
129
1 1
128
1 V
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 227 3 C C 2 18 22 24
128
1 0
128
0 Y
227
0 0
AA 5 PG CK
128
0
128
0 AA
AB 1 227 1 C C R IN DN SR PR MD MD AB
226
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 226 3 C C MS DI DO 3
505
3 AD
225
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 226 1 C C S 18 18 24 24 EO PO 62 2
505
2 AF
224
1 1
AG 23 S 16 23 22 63 61
505
1
505
1 AG
VC 65
AH 3 225 3 V 227 V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
505
VC 64
0 0
AJ V 226 V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
505 505
VC 66
AK 1 225 1 V 225 V 21 19 22 14 14 19 S 20 20 23 21 24 27 26 A 57 56 G 0 0 AK
C
O
505
AL V 224 V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
VC 65
VC 64
VC 504
AM 3 224 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
VC 6 6
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
V C 84
VC 504
VC 504
AP 1 224 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
V C 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
V C 66
VC 504
VC 504
AT 7 8 8 S 6 4 4 5 5 7 9 S 8 10 P 8 N DM CN A A A P DM 64 N 66 AT
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DO
Figure 4-47: FFVG1517 and FSVG1517 Packages—XCZU27DR and XCZU28DR I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V A
B DAC DAC DAC V B
C DAC V C
D DAC DAC DAC V D
E DAC DAC V E
F DAC DAC DAC DAC V F
G DAC DAC V G
DAC
H DAC DAC DAC
VTT V H
DAC
J DAC VTT V J
DAC
K DAC DAC DAC VTT DAC V K
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
M DAC DAC DAC DAC DAC DAC
AUX
DAC
VCC
DAC
FEC E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
P DAC DAC DAC DAC DAC DAC AUX DAC VCC SUB FEC V P
DAC DAC VCC VCC
V
R DAC DAC AUX DAC VCC DAC AMS FEC V R
DAC DAC VCC
T DAC DAC DAC DAC DAC DAC AUX DAC VCC DAC FEC V T
DAC DAC VCC VCC
V
U DAC DAC AUX DAC VCC DAC AMS FEC V U
DAC VCC
V DAC DAC DAC DAC DAC DAC DAC DAC
VCC
DAC
FEC E V
DAC VCC VCC
W ADC ADC ADC ADC ADC ADC DAC
VCC
DAC
AMS 24 21 FEC E V W
VCC
Y ADC ADC DAC DAC DAC DAC 22 23 FEC E Y
VCC VCC
AA ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AMS 8 7 FEC V AA
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AC ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS FEC BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC AUX ADC VCC ADC FEC DP DP PL AU E AD
ADC ADC ADC VCC VCC
AE ADC ADC ADC ADC ADC ADC AUX ADC VCC SUB AMS FEC LP PL PL AD V AE
ADC ADC VCC
AF ADC ADC AUX ADC VCC ADC 13 15 FEC FP DP LP AD E AF
ADC ADC VCC VCC
AG ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS 33 FEC FP LP LP DD V AG
ADC ADC VCC
AH ADC ADC
AUX
ADC
VCC
ADC 34 FEC
FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC AUX ADC VCC ADC AMS 35 FEC FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Figure 4-48: FFVG1517 and FSVG1517 Packages—XCZU27DR and XCZU28DR Power, Dedicated,
and Multi-function Pin Diagram
FFVC1760 Package–XCZU11EG
X-Ref Target - Figure 4-49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A 10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22 A
V C 90
V C 69
B 9 9 10 11 11 10 11 10 11 11 16 18 20 22 24 20 22 23 24 22 22 21 19 8 10 14 14 17 20 20 S 23 23 24 B
C
O
O
VC 91
V C 89
VC 68
VC 71
VC 70
C 6 8 8 7 7 8 12 10 9 15 S 18 20 23 19 20 22 S 23 23 21 19 8 12 12 15 16 S 19 19 24 C
C
O
O
VC 91
VC 69
3
D 4 6 5 5 9 7 8 12 9 8 15 14 19 21 23 19 17 18 S S S 17 17 7 11 13 15 16 D
C
3
O
131
2
E 4 3 3 2 2 9 7 4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13 3
131
3
131
2 E
V C 68
VC 71
V C 70
1
F 1 1 1 5 6 4 5 6 6 13 12 11 10 15 16 14 14 18 14 15 15 5 4 3 3 2 2 F
C
1
O
131 131
VC 90
VC 69
3 0
G 1 5 6 5 2 3 4 7 12 11 10 12 13 13 10 12 13 13 5 4 1 1 G
C
3 0
O
231 131 131
V C 89
3
H 3 3 2 3 1 2 3 4 7 8 9 11 11 12 10 12 11 11 6 2 0 0 H
C
3
O
231 131 130
V C 68
VC 71
V C 70
2 1 2
J 2 2 2 3 1 12 12 11 8 S 9 7 9 10 9 9 8 7 6 1 2 3 3 J
C
2 1 2
O
231 231 131 130 130
1
K 1
231
1 10 10 7 11 5 5 6 7 8 9 10 4 S 8 7 1 2
130
2
130
1 K
V C 88
1 0 0
L 0 0 9 7 8 8 4 6 2 3 8 S 6 4 2 26 28 27 30 1 1 L
C
1 0 0
O
231 231 131 130 130
VC 88
0 3
M 3 3 9 6 6 5 4 3 3 2 3 6 6 6 2 29 31 32 0 0 M
C
0 3
O
231 230 130 129
VC 501
3 1 2
N 2 2 1 1 2 5 4 1 2 1 4 4 5 5 3 3 1 33 35 37 3 3 N
C
3 1 2
O
230 230 130 129 129
2 1
P 2
230
1
230
1 2 3 4 1 2 1 5 5 1 34 40 39 41 2
129
2
129
1 P
1 1 0 0
R 1
230
0
230
0 1
231
3 38 44 43
130
0 1
129
1
129
0 R
0 0 3
T G T
V
0 3 3 0 36 47 45 42 0 0 3
230 229 231 129 128
VC 501
3 1 1 2
U 2 2 EO 46 49 3 3 U
C
3 1 1 2
O
229 229 230 129 128 128
2 0 1
V 2
229
1
229
1 0
230
IN ES 50 48 2
128
2
128
1 V
VC 503
1 1 0 0
W 0 0 PR 52 51 1 1 W
C
1 1 0 0
O
229 229 229 129 128 128
0 0
Y 0
229
3
228
3 0
229
PG DN 54 53 0
128
0 Y
3 1 1 3 3
AA 3
228
2
228
2 1
228
MD MD 56
128
1
505
3
505
3 AA
2 0 0
AB 2
228
1
228
1 0
228
SR MD 55 57
128
0 3
505
3 AB
VC 502
1 1 2 2
AC 0 0 CK RC MD 58 59 61 AC
C
1 1 2 2
O
228 228 227 505 505
VC 503
0 0
AD 3 3 DI MS DO 60 63 62 64 66 13 15 2 2 AD
C
0 0
O
228 227 227 505
3 1 1 1
AE G AE
V
3 2 2 1 PO PI 65 67 69 68 18 19 1 1
227 227 226 505 505
VC 500
2 0
AF 1 1 70 71 72 75 21 1 1 AF
C
2 0
O
227 227 226 505
VC 502
1 1 0 0
AG 0 0 73 77 74 25 23 G AG
C
1 1 0 0
O
227 227 225 505 505
0 0
AH 0
227
3
226
3 0
225
76 22 24 20 0
505
0 AH
3 1
AJ 3
226
2
226
2 1
224
24 20 22 19 23 23 24 24 17 16 14 12 46 44 P 60 AJ
2 0
AK 2
226
1
226
1 0
224
24 20 22 19 22 22 24 23 24 10 11 8 9 47 N 42 43 62 63 61 AK
1
AL 1
226
0
226
0 21 19 23 S 20 S 21 21 23 7 6 5 4 45 DM 40 41 P N DM AL
VC 500
0
AM 3 3 18 17 23 21 19 23 20 19 20 20 22 21 S 15 17 1 3 2 0 RS PA AL 57 56 58 59 AM
C
0
O
226 225
VC 504
3
AN 2 2 18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16 31 30 28 ZQ BA BA 39 36 32 33 AN
C
3
O
225 225
VC 67
VC 66
2
AP 1 1 14 S 16 22 S 24 S 18 17 16 15 20 20 S 16 17 18 19 29 A BG BG A 38 P 35 34 AP
C
2
O
225 225
VC 64
VC 65
VC 504
VC 5 0 4
1
AR 0 0 14 13 13 15 15 17 16 18 17 S 19 14 14 13 18 DM P P DM A A AC 37 DM N 48 AR
C
C
1
O
O
225 225
0
AT 0
225
3
224
3 12 12 11 11 14 18 17 16 14 13 13 19 12 12 13 18 N 20 N 26 A A OD CE 51 49 50 AT
VC 67
VC 504
VC 504
3
AU 2 2 S 8 10 12 14 18 15 14 12 11 7 7 11 11 10 23 21 22 25 27 A A CS DM P N AU
C
C
3
O
O
224 224
V C 66
V C 64
V C 65
2
AV 10 10 8 7 10 12 13 13 15 12 11 8 7 7 8 9 10 0 12 14 15 24 C CN 55 54 53 52 AV
C
2
O
224
VC 504
VC 504
1
AW 1 1 3 1 9 9 7 11 11 3 3 9 9 S 8 1 S 8 9 2 1 3 13 A A A A 71 69 70 68 AW
C
1
O
224 224
VC 67
AY 0 0 3 1 7 5 5 1 10 10 4 2 2 1 3 5 5 DM P P N DM A CS CE P N DM AY
C
O
224
V C 66
V C 64
VC 65
0
BA 5 4 4 9 8 7 6 4 2 1 6 4 3 3 1 3 4 6 N 7 9 10 A C CN A 67 65 66 BA
C
0
O
224
BB 6 6 5 2 2 9 8 6 S 4 2 6 5 5 1 2 2 4 6 6 5 4 8 11 A A A OD 64 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B B
C C
D D
E E
F V F
G V G
H E V H
J V J
K V E V K
L V V L
M V E V M
N V V N
V
P V V P
R V V R
T V E V T
V
U V V U
V
V V E V V
V
W V E W
Y V E E Y
AA V E 24 21 E E AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E V AD
AE V PL E AE
AF V E FP PL PL DP E AF
V
AG V FP AU AD DP AU AG
AH V E 13 15 LP AU BT AD AU AH
V
AJ V FP FP LP AD AD AJ
AK V E 33 FP DD LP LP AK
AL V 34 FP FP DD DD AL
AM V 35 AM
AN V AN
AP V AP
AR V AR
AT V AT
AU AU
AV V AV
AW 38 AW
AY AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Figure 4-50: FFVC1760 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A 10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22 A
VC 93
V C 69
B 9 9 10 11 11 10 11 10 11 11 16 18 20 22 24 20 22 23 24 22 22 21 19 8 10 14 14 17 20 20 S 23 23 24 B
C
O
O
VC 94
VC 91
VC 68
V C 71
VC 70
C 6 8 8 7 7 8 12 10 9 15 S 18 20 23 19 20 22 S 23 23 21 19 8 12 12 15 16 S 19 19 24 C
C
O
O
VC 94
V C 69
3
D 4 6 5 5 9 7 8 12 9 8 15 14 19 21 23 19 17 18 S S S 17 17 7 11 13 15 16 D
C
3
O
131
2
E 4 3 3 2 2 9 7 4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13 3
131
3
131
2 E
V C 68
VC 71
V C 70
1
F 1 1 1 5 6 4 5 6 6 13 12 11 10 15 16 14 14 18 14 15 15 5 4 3 3 2 2 F
C
1
O
131 131
VC 93
VC 69
3 0
G 1 5 6 5 2 3 4 7 12 11 10 12 13 13 10 12 13 13 5 4 1 1 G
C
3 0
O
231 131 131
V C 91
3
H 3 3 2 3 1 2 3 4 7 8 9 11 11 12 10 12 11 11 6 2 0 0 H
C
3
O
231 131 130
VC 68
V C 71
V C 70
2 1 2
J 2 2 2 3 1 12 12 11 8 S 9 7 9 10 9 9 8 7 6 1 2 3 3 J
C
2 1 2
O
231 231 131 130 130
1
K 1
231
1 10 10 7 11 5 5 6 7 8 9 10 4 S 8 7 1 2
130
2
130
1 K
VC 90
1 0 0
L 0 0 9 7 8 8 4 6 2 3 8 S 6 4 2 26 28 27 30 1 1 L
C
1 0 0
O
231 231 131 130 130
VC 90
0 3
M 3 3 9 6 6 5 4 3 3 2 3 6 6 6 2 29 31 32 0 0 M
C
0 3
O
231 230 130 129
VC 501
3 1 2
N 2 2 1 1 2 5 4 1 2 1 4 4 5 5 3 3 1 33 35 37 3 3 N
C
3 1 2
O
230 230 130 129 129
2 1
P 2
230
1
230
1 2 3 4 1 2 1 5 5 1 34 40 39 41 2
129
2
129
1 P
1 1 0 0
R 1
230
0
230
0 1
231
3 38 44 43
130
0 1
129
1
129
0 R
0 0 3
T G T
V
0 3 3 0 36 47 45 42 0 0 3
230 229 231 129 128
VC 501
3 1 1 2
U 2 2 EO 46 49 3 3 U
C
3 1 1 2
O
229 229 230 129 128 128
2 0 1
V 2
229
1
229
1 0
230
IN ES 50 48 2
128
2
128
1 V
VC 503
1 1 0 0
W 0 0 PR 52 51 1 1 W
C
1 1 0 0
O
229 229 229 129 128 128
0 0
Y 0
229
3
228
3 0
229
PG DN 54 53 0
128
0 Y
3 1 1 3 3
AA 3
228
2
228
2 1
228
MD MD 56
128
1
505
3
505
3 AA
2 0 0
AB 2
228
1
228
1 0
228
SR MD 55 57
128
0 3
505
3 AB
VC 502
1 1 2 2
AC 0 0 CK RC MD 58 59 61 AC
C
1 1 2 2
O
228 228 227 505 505
VC 503
0 0
AD 3 3 DI MS DO 60 63 62 64 66 13 15 2 2 AD
C
0 0
O
228 227 227 505
3 1 1 1
AE G AE
V
3 2 2 1 PO PI 65 67 69 68 18 19 1 1
227 227 226 505 505
VC 500
2 0
AF 1 1 70 71 72 75 21 1 1 AF
C
2 0
O
227 227 226 505
VC 502
1 1 0 0
AG 0 0 73 77 74 25 23 G AG
C
1 1 0 0
O
227 227 225 505 505
0 0
AH 0
227
3
226
3
0
225
76 22 24 20 0
505
0 AH
3 1
AJ 3
226
2
226
2 1
224
24 20 22 19 23 23 24 24 17 16 14 12 46 44 P 60 AJ
2 0
AK 2
226
1
226
1 0
224
24 20 22 19 22 22 24 23 24 10 11 8 9 47 N 42 43 62 63 61 AK
1
AL 1
226
0
226
0 21 19 23 S 20 S 21 21 23 7 6 5 4 45 DM 40 41 P N DM AL
VC 500
0
AM 3 3 18 17 23 21 19 23 20 19 20 20 22 21 S 15 17 1 3 2 0 RS PA AL 57 56 58 59 AM
C
0
O
226 225
VC 504
3
AN 2 2 18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16 31 30 28 ZQ BA BA 39 36 32 33 AN
C
3
O
225 225
V C 67
VC 66
2
AP 1 1 14 S 16 22 S 24 S 18 17 16 15 20 20 S 16 17 18 19 29 A BG BG A 38 P 35 34 AP
C
2
O
225 225
V C 64
V C 65
VC 504
VC 504
1
AR 0 0 14 13 13 15 15 17 16 18 17 S 19 14 14 13 18 DM P P DM A A AC 37 DM N 48 AR
C
C
1
O
O
225 225
0
AT 0
225
3
224
3 12 12 11 11 14 18 17 16 14 13 13 19 12 12 13 18 N 20 N 26 A A OD CE 51 49 50 AT
V C 67
VC 504
VC 5 0 4
3
AU 2 2 S 8 10 12 14 18 15 14 12 11 7 7 11 11 10 23 21 22 25 27 A A CS DM P N AU
C
C
3
O
O
224 224
V C 66
VC 64
VC 65
2
AV 10 10 8 7 10 12 13 13 15 12 11 8 7 7 8 9 10 0 12 14 15 24 C CN 55 54 53 52 AV
C
2
O
224
VC 504
VC 504
1
AW 1 1 3 1 9 9 7 11 11 3 3 9 9 S 8 1 S 8 9 2 1 3 13 A A A A 71 69 70 68 AW
C
1
O
224 224
V C 67
AY 0 0 3 1 7 5 5 1 10 10 4 2 2 1 3 5 5 DM P P N DM A CS CE P N DM AY
C
O
224
VC 66
VC 64
VC 65
0
BA 5 4 4 9 8 7 6 4 2 1 6 4 3 3 1 3 4 6 N 7 9 10 A C CN A 67 65 66 BA
C
0
O
224
BB 6 6 5 2 2 9 8 6 S 4 2 6 5 5 1 2 2 4 6 6 5 4 8 11 A A A OD 64 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B B
C C
D D
E E
F V F
G V G
H E V H
J V J
K V E V K
L V V L
M V E V M
N V V N
V
P V V P
R V V R
T V E V T
V
U V V U
V
V V E V V
V
W V E W
Y V E E Y
AA V E 24 21 E E AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E V AD
AE V PL E AE
AF V E FP PL PL DP E AF
V
AG V FP AU AD DP AU AG
AH V E 13 15 LP AU BT AD AU AH
V
AJ V FP FP LP AD AD AJ
AK V E 33 FP DD LP LP AK
AL V 34 FP FP DD DD AL
AM V 35 AM
AN V AN
AP V AP
AR V AR
AT V AT
AU AU
AV V AV
AW 38 AW
AY AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
3 3
A 3
234
3
234
3 12 12 11 10 10 24 23 23 24 24 23 24 24 23 22 52 53 3
134
3
134
3 A
V C 91
1 2 1 2
B 9 9 8 8 11 24 22 22 21 22 23 21 21 23 22 20 54 55 2 2 B
C
1 2 1 2
O
234 234 134 134 134
VC 71
VC 70
VC 69
0 1
C 2 2 7 6 6 20 20 21 22 20 21 21 19 19 20 56 57 1 1 C
C
0 1
O
234 234 134 134
3 0 0
D 3
233
1
234
1 0
234
0 7 5 5 4 19 19 S 20 19 19 S S 18 18 58 59
134
0 0
134
0
134
0 D
VC 91
VC 502
2 3
E 3 3 3 3 4 S 18 18 S S 17 17 17 17 16 16 60 3 3 E
C
2 3
O
233 233 133 133
VC 71
VC 70
VC 69
1 1 2
F 2 2 1 1 2 1 1 17 16 16 18 18 16 16 15 15 14 61 62 2 2 F
C
1 1 2
O
233 233 233 133 133 133
0 1
G 0
233
0
233
0 12 12 2 17 15 15 14 15 15 14 14 13 14 12 63 64 1
133
1
133
1 G
V C 90
3 0 0
H 2 2 3 3 11 10 10 13 13 14 13 13 12 11 13 11 12 65 66 0 0 H
C
3 0 0
O
232 232 232 133 133 133
V C 71
V C 70
VC 69
2 3
J 1 1 11 9 9 7 12 11 11 10 12 11 9 11 10 10 67 68 3 3 J
C
2 3
O
232 232 132 132
VC 502
1 1 1 2
K 0 0 8 8 7 10 10 12 10 8 8 9 9 9 8 8 69 2 2 K
C
1 1 1 2
O
232 232 234 132 132 132
0 1
L 0
232
3
231
3 6 6 5 5 9 8 7 7 7 S 7 7 S 70 71 1
132
1
132
1 L
VC 90
3 0 0 0
M 2 2 4 9 S 8 7 6 6 5 6 6 72 73 0 0 M
C
3 0 0 0
O
231 231 234 132 132 132
2 1 3
N 2
231
1
231
1 1
233
4 3 6 6 5 5 4 4 5 4 5 5 74 75 3
131
3
131
3 N
1 0 1 2
P 1
231
0
231
0 0
233
2 3 3 4 4 2 3 3 1 4 3 2 2 76 77
131
1 2
131
2
131
2 P
0 1 1
R 0
231
3
230
3 1
232
2 1 1 1 3 2 2 2 1 3 1 1 EO 1
131
1
131
1 R
3 0 0 0
T 3
230
2
230
2 0
232
1 PR ES
131
0 0
131
0
131
0 T
VC 503
2 1 3
U 1 1 PG 3 3 U
C
2 1 3
O
230 230 231 130 130
1 0 1 2
V 1
230
0
230
0
0
231
MD IN
130
1
2
130
2
130
2 V
0 1 1
W 0
230
3
229
3 1
230
SR DN 1
130
1
130
1 W
3 0 0 0
Y 3
229
2
229
2 0
230
MD
130
0 0
130
0
130
0 Y
2 1 3
AA 2
229
1
229
1 1
229
RC MD 3
129
3
129
3 AA
VC 503
1 0 1 2
AB 0 0 MD 2 2 AB
C
1 0 1 2
O
229 229 229 129 129 129
0 1 1
AC G AC
V
0 3 3 1 CK MS 1 1 1
229 228 228 129 129
3 0 0 0
AD 3
228
2
228
2 0
228
DI DO PI
129
0 0
129
0
129
0 AD
2 1 3
AE 2
228
1
228
1 1
227
PO 3
128
3
128
3 AE
1 0 1 2
AF 1
228
0
228
0 0
227 128
1 2
128
2
128
2 AF
0 1 1
AG G AG
V
0 3 3 1 1 1 1
228 227 226 128 128
3 0 0 0
AH 3
227
2
227
2 0
226
24 24 24 23 26 27 28 29 0 1
128
0 0
128
0
128
0 AH
2 1
AJ 2
227
1
227
1 1
225
24 23 22 23 21 30 31 10 11 AJ
1 0 3 3
AK 1
227
0
227
0 0
225
22 23 21 22 21 32 33 34 12 13 G 505
3 3
505
3
505
3 AK
V C 501
0 1 2 2
AL 3 3 22 21 20 20 19 35 36 14 15 16 2 2 AL
C
0 1 2 2
O
VC 500
3 0 1 1
AM 2 2 20 20 S S 19 37 38 39 17 18 19 2 20 1 1 AM
C
3 0 1 1
O
226 226 224 505 505 505
V C 500
2 0 0
AN 1 1 S S 19 19 18 17 17 40 41 21 22 23 24 25 3 0 0 AN
C
2 0 0
O
226 226 505 505 505
VC 66
VC 501
1
AP 0 0 3 3 17 18 18 18 16 16 15 42 43 4 5 6 7 8 9 62 AP
C
1
O
VC 504
0
AR 2 2 17 16 16 14 14 15 44 45 46 P 19 24 30 PA BA AL ZQ RS 32 33 34 36 47 46 60 61 63 AR
C
C
0
O
O
226 225
3
AT 3
225
1
225
1 0
225
0 15 15 14 14 13 13 12 47 23 DM N 17 26 31 A A AC BG P N DM 45 44 DM P AT
VC 66
VC 504
VC 504
2
AU 3 3 13 13 12 11 11 12 48 49 22 21 18 P N DM A A A A 38 35 P N 56 59 N AU
C
C
2
O
O
225 224
VC 65
1
AV 2 2 11 11 10 12 9 10 9 9 50 51 20 6 16 27 28 CN A A BA BG 39 37 DM 42 57 58 AV
C
1
O
225 224
VC 504
VC 504
0
AW 1 1 8 8 10 7 9 10 8 8 7 6 7 5 4 25 29 12 C A CE A OD 71 40 41 43 50 48 AW
C
C
0
O
O
225 224
VC 66
3 2
AY S 7 6 6 S 7 5 6 DM P 9 DM 13 CN OD A A CS 67 70 69 52 P DM 49 AY
C
3 2
O
224 224
V C 65
VC 504
VC 504
1
BA 0 0 5 2 4 4 1 4 4 3 5 3 2 N 8 P 14 C A A CS CE DM P N 55 N 51 BA
C
C
1
O
O
224 224
0
BB 0
224
5 2 3 3 1 2 2 3 1 1 1 0 10 11 N 15 A A A A 64 65 66 68 54 53 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A E V A
B E B
C E V C
D V E D
E V E V E
F V E F
G V V E V G
H V V H
J V E E V J
K V V K
L V E E V L
M V V M
N V E E V N
P V E V P
V
R V E V R
T V E V T
V V
U V V U
V
V V V V
V
W V E V W
Y V E V Y
V
AA V E 24 21 V AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E E AD
V
AE V LP PL BT E V AE
V
AF V LP PL AD AD AU E AF
AG V 13 15 LP PL DP DP AU E V AG
AH V E 33 LP FP AU AU E AH
AJ V E 34 FP FP FP AD AD AJ
AK V E FP FP DD V AK
AL V E FP DD DD E AL
AM V 35 E V AM
AN V E E V AN
AP V AP
AR V V AR
AT V AT
AU V AU
AV V AV
AW AW
AY V 38 AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A C C 12 12 5 5 11 11 22 24 23 23 24 24 23 23 20 22 24 24 23 28 26 3
131
3 A
228 230
VC 87
3
B C C 11 10 4 4 8 8 22 24 21 21 22 22 21 19 20 22 21 21 23 29 27 B
C
3
O
131
2
C C C 9 11 10 3 7 7 10 20 20 S 19 18 20 21 19 S 17 19 19 35 30 2
131
2
131
2 C
229 231
VC 89
V C 69
1
D S 228 S C C 9 8 2 2 3 10 16 18 18 19 16 18 20 17 18 S 17 34 33 31 32 D
C
1
O
131
VC 8 7
V C 68
VC 67
0
E 7 7 8 1 6 9 9 16 S 17 17 16 S S 17 18 15 13 36 37 1 1 E
C
0
O
131 131
VC 501
3
F 3 231 3 2 231 2 6 6 1 12 12 6 12 14 14 15 12 14 14 15 16 16 15 13 40 0 0 F
C
3
O
131 130
VC 89
VC 69
2
G 4 5 5 10 12 12 12 10 13 15 12 10 15 13 14 14 11 43 38 3 3 G
C
2
O
130 130
VC 88
VC 68
VC 67
1
H 1 231 1 0 231 0 3 3 4 10 11 11 8 10 9 13 11 10 11 11 13 12 12 11 42 2 2 H
C
1
O
131 130
VC 88
VC 501
1
J 2 2 9 9 8 8 8 9 11 8 S 9 8 10 10 9 46 39 1 1 J
C
1
O
130 130
V C 69
0
K 3 230 3 2 230 2 1 1 6 6 7 7 S 7 7 8 9 6 8 S 9 44 49 41 0 0 K
C
0
O
131 130
V C 68
VC 67
0
L 5 5 4 6 5 7 7 6 7 7 45 47 3 3 L
C
0
O
129 130
1
M 1 230 1 0 230 0 3 2 1 4 6 5 3 6 6 4 3 5 5 50 51 48
130
1 2
129
2 M
VC 503
3
N 3 2 1 4 3 3 3 5 5 4 3 54 56 53 DN 1 1 N
C
3
O
129 129
0
P 3 229 3 2 229 2 2 4 1 2 4 1 52 55 IN PG
130
0 0
129
0 P
VC 502
2
R 2 1 1 1 2 4 2 2 1 57 58 SR PR 3 3 R
C
2
O
128 129
1
T 1 229 1 0 229 0 61 63 59 CK
129
1 2
128
2 T
1
U R 60 64 DI RC 1
128
1
129
1 U
0
V 3 228 3 2 228 2 62 66 65 DO
129
0 0
128
0 V
VC 502
0
W G W
V
67 69 MS PI
C
0
O
129
1 3
Y 1 228 1 0 228 0 68 74 MD PO
128
1
128
3 Y
0 2
AA 70 73 77 MD
128
0
128
2 AA
3 1
AB 71 76 MD MD
505
3
128
1 AB
VC 503
2 0
AC 3 227 3 2 227 2 72 75 EO ES AC
C
2 0
O
505 128
1
AD 505
1 AD
3
AE 1 227 1 0 227 0 3
505
3
505
3 AE
0
AF R 505
0 2
505
2 AF
2
AG 3 226 3 2 226 2 1
505
1
505
2 AG
1
AH V 227 V V 225 V 22 24 24 23 24 0
505
0 G 505
1 AH
0
AJ 1 226 1 0 226 0 V 226 V V 224 V 24 20 22 23 19 23 24 22 505
0 AJ
V C 66
AK 24 23 23 20 19 21 21 19 23 21 22 38 P 36 33 32 43 AK
C
O
VC 500
AL 3 225 3 2 225 2 20 22 18 18 19 S S 17 20 21 C
O
22 24 39 37 N 34 41 44 DM 42 47 AL
VC 65
AM 20 22 21 S 16 17 17 S 17 20 16 23 25 16 18 BA PA BG DM 35 40 P N 46 AM
C
O
V C 66
AN 1 225 1 0 225 0 18 S 21 19 16 15 13 13 15 18 18 16 21 DM 19 17 A A AC BG BA 62 63 61 45 AN
C
O
VC 64
VC 66
AP 12 12 11 18 S 19 14 14 15 11 13 15 14 12 20 18 P 28 31 30 A A A A DM P 60 AP
C
C
O
O
VC 65
VC 500
VC 504
VC 504
AR 3 224 3 2 224 2 10 11 9 16 17 17 15 12 12 11 13 14 10 12 19 22 N 29 DM OD AL ZQ RS 57 56 N 59 AR
C
C
O
O
VC 84
VC 65
AT 10 9 12 16 14 15 8 10 10 9 11 11 10 15 17 23 21 P N A CS A 53 51 P 58 AT
C
C
O
O
VC 64
VC 504
VC 504
AU 1 224 1 0 224 0 7 8 8 12 14 13 13 8 9 9 9 7 8 13 14 16 20 24 25 26 C A A 54 N 50 48 AU
C
C
O
O
VC 64
VC 500
AV 6 7 5 8 10 11 11 4 6 S 7 6 8 10 12 3 2 0 27 15 CN CE 55 52 DM 49 AV
C
C
O
O
VC 84
VC 504
VC 504
AW C C 6 5 S 8 10 9 9 4 6 7 S 6 9 8 11 4 1 12 14 13 A A CE 70 69 71 AW
C
C
O
O
225 227
AY C C 3 4 4 6 6 7 7 3 5 7 5 4 4 6 7 DM P N DM P CN C A DM P N 67 AY
VC 504
BA C C 3 2 3 3 5 5 2 2 3 5 5 3 3 2 1 4 5 6 8 11 N A
C
O
A CS 64 66 68 BA
224 226
BB C C 2 1 1 1 1 4 4 2 2 1 1 1 1 2 2 0 3 7 5 9 10 A OD A A 65 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A DO
Figure 4-55: FFVF1760 and FSVF1760 Packages—XCZU29DR and XCZU39DR I/O Bank Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A DAC DAC DAC DAC A
B DAC DAC DAC DAC DAC V B
C DAC DAC DAC DAC DAC C
D DAC DAC DAC V D
E DAC DAC DAC DAC DAC DAC DAC E
F DAC DAC DAC V F
G DAC DAC DAC DAC DAC DAC DAC E G
H DAC DAC DAC V H
J DAC DAC DAC DAC DAC DAC DAC E V J
K DAC DAC DAC DAC DAC E K
L DAC DAC DAC DAC DAC DAC DAC DAC DAC E V L
M DAC DAC DAC DAC DAC DAC DAC DAC E M
V
N DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC V N
DAC DAC DAC DAC VCC
P DAC DAC AUX AUX AUX AUX DAC DAC AMS E P
DAC DAC DAC DAC DAC
V
R DAC DAC DAC DAC DAC DAC AUX AUX AUX AUX DAC SUB V R
VCC
T DAC DAC DAC DAC DAC DAC DAC DAC AMS E T
DAC DAC DAC DAC
U DAC DAC DAC DAC DAC DAC VTT VTT VCC VCC DAC E V U
DAC DAC DAC DAC VCC
V DAC DAC VTT VTT DAC VCC VCC DAC AMS V
DAC DAC DAC DAC
W DAC DAC DAC DAC DAC DAC VTT VTT DAC VCC VCC DAC E W
DAC DAC DAC DAC VCC
Y DAC DAC VTT VTT DAC VCC VCC DAC AMS Y
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC 24 21 AA
VCC
AB ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AMS 22 23 AB
ADC ADC ADC ADC
AC ADC ADC AUX AUX ADC VCC VCC ADC 8 7 E AC
ADC ADC ADC ADC VCC
AD ADC ADC ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
AMS
AU AU AU AU V AD
ADC ADC ADC ADC
AE ADC ADC AUX AUX ADC VCC VCC ADC BT AD AD PL E V AE
ADC ADC ADC ADC VCC
AF ADC ADC ADC ADC ADC ADC AUX AUX VCC VCC ADC AMS FP DP DP AD PL V AF
ADC
AG ADC ADC ADC ADC ADC ADC ADC SUB FP LP AD PL PL E AG
VCC
AH ADC ADC ADC ADC ADC ADC ADC ADC AMS 13 15 35 34 33 FP LP LP LP AH
AJ ADC ADC ADC ADC FP FP FP LP LP AJ
VCC
AK ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AMS FP DD DD DD DD AK
AL ADC ADC ADC ADC ADC ADC ADC DD DD DD AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AM
AN ADC ADC ADC ADC AN
AP ADC ADC ADC ADC ADC ADC ADC ADC AP
AR ADC ADC ADC ADC AR
AT ADC ADC ADC ADC ADC ADC ADC ADC AT
AU ADC ADC ADC AU
AV ADC ADC ADC ADC ADC ADC ADC 38 AV
AW ADC ADC ADC ADC ADC AW
AY ADC ADC ADC ADC ADC AY
BA ADC ADC ADC ADC ADC BA
BB ADC ADC ADC ADC BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A 3 3 4 4 6 12 12 12 12 10 10 22 22 24 23 23 24 24 24 23 23 17 17 18 24 23 23 22 17 S A
VC 94
V C 93
3
B 2 5 6 8 11 11 11 9 9 21 21 23 24 21 24 22 22 21 21 19 15 18 24 21 21 22 17 24 S B
C
3
O
234
VC 94
1 2
C 2 5 8 11 8 8 7 7 20 20 19 23 19 21 22 22 20 20 19 15 16 16 19 19 20 16 24 23 23 C
C
1 2
O
234 234
VC 72
0
D 1 1 7 7 6 6 5 5 17 S S 19 19 S 20 20 S S 18 18 14 14 S S 20 16 15 22 21 21 D
C
0
O
234
VC 93
VC 73
VC 74
VC 71
3
E 3 3 9 9 10 4 2 2 1 17 16 18 18 S 18 18 17 17 16 16 13 13 11 12 12 14 15 22 20 20 E
C
3
O
233 234
2
F 2
233
2
234
2 10 4 3 3 1 15 15 16 14 17 17 15 15 15 14 14 10 10 9 11 12 14 13 13 19 18 18 F
V C 72
VC 70
1 1
G 1 1 12 12 11 11 11 13 13 14 14 15 16 13 11 12 12 7 9 8 8 12 11 11 10 19 24 G
C
1 1
O
233 234 234
V C 91
V C 73
V C 74
VC 71
0 0
H 0 0 9 10 10 10 11 12 12 14 13 16 13 11 9 10 7 S 8 8 9 9 10 23 23 24 H
C
0 0
O
233 234 234
VC 71
3 1
J 3 3 9 8 8 10 9 9 8 11 13 12 12 7 9 8 10 6 6 6 6 S 7 7 20 22 22 J
C
3 1
O
232 233 233
VC 72
VC 70
2 0
K 2 2 5 7 7 6 6 7 8 9 11 10 10 S 7 8 4 4 3 4 5 5 19 20 21 21 K
C
2 0
O
232 233 233
VC 73
VC 74
VC 70
1 1
L 1 1 5 3 4 4 S 7 9 8 8 7 5 6 6 3 5 5 4 3 12 12 19 S 18 18 L
C
1 1
O
232 233 232
VC 91
0 0
M 0 0 1 3 2 2 3 6 6 5 7 S 5 4 4 2 2 1 2 2 3 11 14 14 S 17 M
C
0 0
O
232 233 232
VC 90
3
N 2 2 3 3 1 12 12 11 3 5 5 5 3 6 3 3 1 1 1 9 9 11 13 15 16 16 17 N
C
3
O
231 232 232
VC 69
2 1
P 1 1 9 10 10 11 1 4 4 1 3 2 6 2 2 1 5 8 8 10 13 15 9 5 5 P
C
2 1
O
231 232 231
VC 69
1
R 0 0 3 3 9 8 8 7 7 1 2 2 1 2 4 4 1 3 3 5 S 7 7 10 12 9 S 4 R
C
1
O
231 232 231
VC 9 0
V C 69
0 0
T 2 2 6 6 5 5 1 4 4 6 6 15 13 13 12 4 2 T
C
0 0
O
231 231 231
VC 68
3
U 0 0 1 1 4 4 3 3 1 2 2 19 18 18 15 11 8 8 6 2 U
C
3
O
230 231 231
VC 68
2 1
V 3 3 1 2 2 22 22 19 17 17 14 11 7 6 3 1 V
C
2 1
O
230 230 230
VC 68
1
W 1 1 2 2 1 24 23 21 21 16 16 14 10 10 7 3 1 W
C
1
O
230 230 230
VC 67
0 0
Y 0 0 24 23 20 20 S S 13 13 9 S 6 Y
C
0 0
O
230 230 230
VC 67
3
AA 2 2 3 3 22 22 S S 14 12 12 9 5 6 4 AA
C
3
O
229 229 229
VC 67
2 1
AB 1 1 23 23 20 18 18 14 11 8 8 5 4 AB
C
2 1
O
229 229 229
1
AC 1
229
3
228
3 0
229
0 24 21 21 20 16 16 15 11 7 3 3 2 AC
0 0
AD 0
229
2
228
2 0
229
CK MD EO ES 28 24 19 19 17 17 15 10 10 7 1 2 AD
VC 503
VC 501
3
AE 0 0 1 1 PR MD MD 30 29 31 26 33 32 52 53 55 58 60 1 AE
C
3
O
228 228 228
VC 501
VC 502
2 1
AF 3 3 PG MD MS DI 27 40 39 37 34 54 56 57 61 66 67 69 AF
C
2 1
O
228 227 228
VC 503
VC 501
VC 502
VC 502
1
AG 1 1 2 2 SR RC PI 47 46 50 35 38 36 59 63 62 64 65 68 AG
C
1
O
228 227 227
0 0
AH 0
228
0
227
0 0
228
DN IN DO PO 48 51 45 44 42 41 70 71 72 75 73 77 74 76 AH
3
AJ 3
227
2
226
2 3
226
3 43 49 AJ
2 1 3 3
AK 2
227
1
226
1 1
227
24 24 24 19
505
3 G 3
505
3
505
3 AK
1 0 2 2
AL G 24 24 21 23 23 24 23 23 AL
V
1 0 0 0 21 13 2 2 2 2
227 226 227 505 505 505
0 1 1 1
AM 0
227
3
225
3 1
226
23 23 22 21 22 22 22 22 18 15
505
1 1
505
1
505
1 AM
3 0 0 0
AN 3
226
2
225
2 0
226
21 22 19 19 20 20 21 21 23
505
0 0
505
0
505
0 AN
VC 65
2 1
AP 1 1 21 20 19 18 20 S 20 19 19 14 AP
C
2 1
O
VC 5 0 0
1 0
AR 0 0 20 19 17 18 S 18 18 S 16 20 22 20 29 30 31 ZQ 38 36 32 33 47 46 62 63 AR
C
1 0
O
0 1
AT 3 3 S S 17 15 15 16 15 S 17 17 23 21 P 28 DM RS AL 37 P 34 45 44 60 61 P AT
C
0 1
O
3 0
AU 2 2 18 16 16 13 14 16 16 15 17 25 22 DM N P N 26 BG 39 DM N P N DM DM N AU
C
3 0
O
VC 500
VC 504
2
AV 1 1 17 17 18 15 13 12 14 16 14 14 13 24 19 17 16 25 27 A BA PA BA 35 43 42 57 56 59 AV
C
C
2
O
O
225 224
VC 66
VC 64
VC 504
VC 504
1
AW 0 0 12 12 14 13 13 15 12 11 12 12 11 13 1 12 18 0 14 24 A BG A A 40 41 53 52 48 58 AW
C
C
1
O
O
225 224
VC 65
VC 504
3
AY 9 10 11 11 14 9 9 10 11 10 10 9 11 4 10 3 2 13 15 A A AC A CE OD 54 DM P 50 AY
C
C
3
O
O
224
VC 500
0 2
BA 9 8 10 7 7 7 7 10 8 8 8 9 7 7 3 11 1 P 12 DM A A C A CS 67 55 N 51 49 BA
C
0 2
O
225 224
VC 64
VC 504
1
BB 8 6 6 S 5 5 S S 8 5 5 1 2 7 8 N P N 11 A A CN OD 66 DM 70 71 BB
C
1
O
224
VC 504
VC 504
BC 1 3 3 2 5 3 3 6 6 2 6 3 3 1 6 9 DM 7 8 10 A A C A CE 65 68 69 BC
C
C
O
O
0
BD 0
224
1 2 4 4 5 1 1 4 4 2 2 2 6 4 4 0 5 6 5 4 9 A A A CN CS 64 P N BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
# # EO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A A
B B
C C
D D
E E
F V F
G V G
H V E H
J V E J
K V E K
L V E L
M V E M
N V E N
P V V P
R V E R
T V V T
U V E U
V V V V
V
W V W
Y V V Y
V
AA V AA
AB V V 24 21 AB
V
AC V 22 23 AC
AD V V 8 7 AD
V
AE V AE
AF V V AF
AG V E AG
AH V V AH
AJ V E PL PL DP AU AU AJ
AK V E 13 15 FP PL DP AD AU AK
AL V 34 33 FP BT AD AU AD E V AL
AM V E FP FP LP AD LP E AM
AN V E FP LP FP LP LP V AN
AP V E 35 FP DD DD DD LP AP
AR V E AR
AT V E AT
AU V AU
AV V AV
AW AW
AY AY
BA BA
BB 38 BB
BC BC
BD BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Chapter 5
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the Zynq®
UltraScale+™ devices. Table 5-1 and Table 5-2 cross-reference to the mechanical drawings
by device and package combination. See Package Specifications Designations in Chapter 3
for definitions of Evaluation Only, Engineering Sample, and Production mechanical
drawings.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q. For the
mechanical drawings, refer to the Pb-free version of these packages.
Table 5-1: Cross-Reference to Zynq UltraScale+ MPSoC Mechanical Drawings by Package (Cont’d)
Device
XCZU5CG XCZU7CG
XCZU3CG XCZU4CG
Package XCZU2CG XCZU3EG XCZU4EG XCZU5EG XCZU6CG XCZU7EG XCZU9CG XCZU11EG XCZU15EG
XCZU2EG XCZU5EV XCZU7EV XCZU17EG XCZU19EG
XAZU2EG XAZU3EG XCZU4EV XAZU5EV XCZU6EG XAZU7EV XCZU9EG XAZU11EG XQZU15EG
XQZU3EG XAZU4EV
XQZU5EV XQZU7EV
Figure 5-13 Figure 5-13
FFRC1156
Production Production
Figure 5-14 Figure 5-14
FFVC1156
Production Production
Figure 5-19
FFRB1517
Production
Figure 5-20 Figure 5-20
FFVB1517
Production Production
Figure 5-20 Figure 5-20
FFVF1517
Production Production
Figure 5-25 Figure 5-25
FFRC1760
Production Production
Figure 5-24 Figure 5-24
FFVC1760
Production Production
Figure 5-24
FFVD1760
Production
Figure 5-29
FFVE1924
Production
ug1075_c5_112918
Figure 5-1: Package Dimensions for SBVA484 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
ug1085_c5_061419
ug1075_c5_073116
Figure 5-3: Package Dimensions for SFVA625 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
ug1075_c5_121918
ug1075_c5_073117
Figure 5-5: Package Dimensions for SFVC784 (XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV,
XCZU5, and XAZU5EV)
ug1075_c5_120717
ug1075_c5_073117
Figure 5-7: Package Dimensions for FBVB900 (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV)
ug1075_c5_080818
ug1075_c5_100318
Figure 5-9: Package Dimensions for FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG)
ug1075_c5_073116
Figure 5-10: Package Dimensions for FFVC900 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and
XCZU15EG)
ug1075_c5_100318
ug1075_c5_073116
Figure 5-12: Package Dimensions for FFVB1156 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and
XCZU15EG)
ug1075_c5_100318
ug1075_c5_073116
Figure 5-14: Package Dimensions for FFVC1156 (XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG)
ug1085_c5_061419
ug1085_c5_061419
ug1075_ffvd1156_ffve1156_030518
ug1075_fsve1156_030518
Figure 5-18: Package Dimensions for FSVE1156 (XCZU25DR, XCZU27DR, and XCZU28DR)
ug1085_c5_061419
ug1075_c5_073117
Figure 5-20: Package Dimensions for FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and
FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG, and XAZU11EG)
ug1085_c5_061419
ug1075_ffvg1517_030518
Figure 5-22: Package Dimensions for FFVG1517 (XCZU25DR, XCZU27DR, and XCZU28DR)
ug1075_fsvg1517_030618
Figure 5-23: Package Dimensions for FSVG1517 (XCZU25DR, XCZU27DR, and XCZU28DR)
ug1075_c5_073116
Figure 5-24: Package Dimensions for FFVC1760 and FFVD1760 (XCZU11EG, XCZU17EG, and XCZU19EG)
ug1085_c5_061419
ug1075_ffvf1760_030518
ug1085_c5_061419
ug1075_fsvf1760_030618
ug1075_c5_073117
Package Marking
Introduction
The package top-markings for the XC and XA Zynq® UltraScale+™ devices are similar to the
examples shown in Figure 6-1. In addition to the markings explained in Table 6-1, refer to
the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424)
[Ref 17].
The package top-markings for the XQ Zynq UltraScale+ devices are as shown in Figure 6-2.
On XQ products only the Xilinx logo and the 2D bar code are marked.
Device Type
2D Bar Code
XILINX ®
ZYNQ ®
UltraScale+ TM
TM
Device Type XCZU9EG
Package FFVB1156xxxXXXX Date Code
Operating Range
Country of Origin
ug1075_ch6_01_121517
ug1075_c6_121918
Introduction
Zynq® UltraScale+™ devices are packed in trays. Trays are used to pack most of Xilinx
surface-mount devices since they provide excellent protection from mechanical damage. In
addition, they are manufactured using antistatic material to provide limited protection
against ESD damage and can withstand a bake temperature of 125°C.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example:
FFQE1156).
Soldering Guidelines
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the
solder reflow process and how each element of the process is related to the end result must
be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes
using package samples.
The peak reflow temperature of a surface-mount component body should not be more than
250°C maximum (260°C for dry rework only) for Pb-free packages and 220°C for eutectic
packages, and is package size dependent. For multiple BGAs in a single board and because
of surrounding component differences, Xilinx recommends checking all BGA sites for
varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading.
Components might overheat due to lack of thermal constraints. Unbalanced loading can
lead to significant temperature variation on the board. These guidelines are intended to
assist users in avoiding damage to the components; the actual profile should be
determined by those using these guidelines. For complete information on package
moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC
Standard J-STD-020C.
IMPORTANT: Following the initial reflow process, devices should not be reworked more than once. Any
additional rework beyond that is likely to cause irreparable damage to the device.
t183
<1°C/s
Time (s)
ug1075_c7_02_111218
Xilinx does not recommend soldering SnAgCu BGA packages with SnPb solder paste using
a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow
temperature of 220°C. At this temperature range, the SnAgCu BGA solder balls do not
properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields
can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board,
the density of the components on the board, and the mix between large components and
smaller, lighter components. Profiles should be established for all new board designs using
thermocouples at multiple locations on the component. In addition, if there is a mixture of
devices on the board, then the profile should be checked at various locations on the board.
Ensure that the minimum reflow temperature is reached to reflow the larger components
and at the same time, the temperature does not exceed the threshold temperature that
might damage the smaller, heat sensitive components.
Table 8-1 and Figure 8-2 provide guidelines for profiling Pb-free solder reflow.
In general, a gradual, linear ramp into a spike has been shown by various sources to be the
optimal reflow profile for Pb-free solders (Figure 8-2). This profile has been shown to yield
better wetting and less thermal shock than conventional ramp-soak-spike profile for the
Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235°C. When profiling,
identify the possible locations of the coldest solder joints and ensure that those solder
joints reach a minimum peak temperature of 235°C for at least 10 seconds. Reflowing at
high peak temperatures of 260°C and above can damage the heat sensitive components
and cause the board to warp. Users should reference the latest IPC/JEDEC J-STD-020
standard for the allowable peak temperature on the component body. The allowable peak
temperature on the component body is dependent on the size of the component. Refer to
Table 8-1 for peak package reflow body temperature information. In any case, use a reflow
profile with the lowest peak temperature possible.
t 217
Wetting time = 60–150 s
150–200°C
Ramp up 2°C/s maximum
1°C/s maximum for lidless packages
with stiffener ring
Preheating
60–120s
Time (s)
ug1075_c7_01_022818
Notes:
1. See the Zynq UltraScale+ MPSoC data sheet [Ref 8] or the Zynq UltraScale+ RFSoC data sheet [Ref 9] for the
most up-to-date specifications.
2. For devices with the Pb-free signifier in the package name (labeled as Q vs. V) use the temperatures and MSL
listed for the XQ product category.
For sophisticated boards with a substantial mix of large and small components, it is critical
to minimize the ΔT across the board (<10°C) to minimize board warpage and thus, attain
higher assembly yields. Minimizing the ΔT is accomplished by using a slower rate in the
warm-up and preheating stages. Xilinx recommends a heating rate of less than 1°C/s during
the preheating and soaking stages, in combination with a heating rate of not more than
3°C/s throughout the rest of the profile.
It is also important to minimize the temperature gradient on the component, between top
surface and bottom side, especially during the cooling down phase. The key is to optimize
cooling while maintaining a minimal temperature differential between the top surface of
the package and the solder joint area. The temperature differential between the top surface
of the component and the solder balls should be maintained at less than 7°C during the
critical region of the cooling phase of the reflow process. This critical region is in the part of
the cooling phase where the balls are not completely solidified to the board yet, usually
between the 200°C–217°C range. To efficiently cool the parts, divide the cooling section
into multiple zones, with each zone operating at different temperatures.
Post Reflow/Cleaning/Washing
Many PCB assembly subcontractors use a no-clean process in which no post-assembly
washing is required. Although a no-clean process is recommended, if cleaning is required,
Xilinx recommends a water-soluble paste and a washer using a deionized-water. Baking
after the water wash is recommended to prevent fluid accumulation.
Cleaning solutions or solvents are not recommended because some solutions contain
chemicals that can compromise the lid adhesive, thermal compound, or components inside
the package.
Conformal Coating
Xilinx does not have information regarding the reliability of flip-chip BGA packages on a
board after exposure to any specific conformal coating process. Therefore, any process
using conformal coating should be qualified for the specific use case to cover the materials
and process steps.
Note: Ruggedized XQ packages are designed to support conformal coating, with vented lids that
ensure proper cleaning can occur after the etching process and prior to conformal coating.
IMPORTANT: When a conformal coating is required, Parylene-based material should be used to avoid
potential risk of weakening the lid adhesive used in Xilinx packages.
BGA Packages
Xilinx provides the diameter of a land pad on the package side. This information is required
prior to the start of the board layout so the board pads can be designed to match the
component-side land geometry. The typical values of these land pads are described in
Figure 9-1 and summarized in Table 9-1 for 1.0 mm pitch packages. For Xilinx BGA
packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a
clearance between the land metal (diameter L) and the solder mask opening (diameter M)
as shown in Figure 9-1. An example of an NSMD PCB pad solder joint is shown in Figure 9-2.
It is recommended to have the board land pad diameter with a 1:1 ratio to the package
solder mask defined (SMD) pad for improved board level reliability. The space between the
NSMD pad and the solder mask as well as the actual signal trace widths depend on the
capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces
are smaller.
X-Ref Target - Figure 9-1
M
L
Opening in
Solder Mask (M)
Solder Mask
Solder Land (L)
e
UG1075_c8_01_101315
Figure 9-1: Suggested Board Layout of Soldered Pads for BGA Packages
BGA Package
SMD
BGA Solder Ball
Land Pad
Solder Mask
L
PCB M
UG1075_c8_02_101315
Notes:
1. Controlling dimension in mm.
Thermal Specifications
Introduction
Zynq® UltraScale+™ devices are offered exclusively in thermally efficient flip-chip BGA
packages. These flip-chip packages range in pin-count from the smaller 19 x 19 mm
SBVA484 to the 45 x 45 mm FFVE1924. This suite of packages is used to address the various
power requirements of the Zynq UltraScale+ devices. Zynq UltraScale+ devices are
implemented in the 16 nm process technology.
Unlike features in an ASIC, the combination of Zynq UltraScale+ device features used in a
user application is not known to the component supplier. Therefore, it remains a challenge
for Xilinx to predict the power requirements of a given Zynq UltraScale+ device when it
leaves the factory. Accurate estimates are obtained when the board design takes shape. For
this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to
help users quickly and accurately estimate their design power requirements. Zynq
UltraScale+ devices are supported similarly to previous products. The uncertainty of design
power requirements makes it difficult to apply canned thermal solutions to fit all users.
Therefore, Xilinx devices do not come with preset thermal solutions. Your design’s
operating conditions dictate the appropriate solution.
IMPORTANT: The data in Table 10-1 is for device/package comparison purposes only. Attempts to
recreate this data are only valid using the transient 2-phase measurement techniques outlined in
JESD51-14.
TIP: The thermal data query for all available devices by package is available on the Xilinx website:
www.xilinx.com/cgi-bin/thermal/thermal.pl.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example:
FFQE1156). Refer to the Pb-free version of these packages for their thermal resistance data and thermal
models.
Notes:
1. This data is for device/package comparison purposes only. Attempts to recreate this data are only valid using the
transient 2-phase measurement techniques outlined in JESD51-14.
2. All θ JA-Effective values assume no heat sink and include thermal dissipation through a standard JEDEC four-layer
board. The Xilinx power estimation tools (Vivado® Power Analysis, and Xilinx Power Estimator), which require
detailed board dimensions and layer counts, are useful for deriving more precise θ JA-Effective values.
Though Xilinx continues to support these figures of merit data, for Zynq UltraScale+
devices, boundary conditions independent thermal resistor network (Delphi) models are
offered for all Zynq UltraScale+ devices. These compact models seek to capture the thermal
behavior of the packages more accurately at predetermined critical points (junction, case,
top, leads, and so on) with the reduced set of nodes as illustrated in Figure 10-1.
Unlike a full 3D model, these are computationally efficient and work well in an integrated
system simulation environment. Delphi models are available for download on the Xilinx
website (under the Device Model tab).
X-Ref Target - Figure 10-1
Rjc
Junction
SIDE Junction
Rjb
BI BO UG1075_c9_01_101415
RECOMMENDED: Xilinx recommends the use of the Delphi thermal model. Xilinx also recommends a
best practice review of manufacturing variations on the thermal performance of the device from both
the thermal interface material parameters and thermal solution variations. Examples of manufacture
variations include the tolerance in airflow from a fan, the tolerance on performance of the heat pipe
and vapor chamber, and manufacturing variations of the attachment of fins to the heat-sink base and
the flatness of the surface.
Introduction
As described in this section, Xilinx relies on a multi-pronged approach to consuming less
power and dissipating heat for systems using Zynq® UltraScale+™ devices.
Flip-Chip Packages
Zynq UltraScale+ devices are offered in flip-chip BGA packages, which present a low
thermal path. With the exception of the bare-die packages, the flip-chip BGA packages
incorporate a heat spreader with an additional thermal interface material (TIM), as shown in
Figure 11-1.
X-Ref Target - Figure 11-1
Lid-Heat Spreader
Die
Substrate
UG1075_c10_01_101415
A parallel effort to ensure optimized package electrical return paths produces the added
benefit of enhanced power and ground plane arrangement in the packages. A boost in
copper density on the planes improves the overall thermal conductivity through the
laminate. In addition, the extra dense and distributed via fields in the package increase the
vertical thermal conductivity.
• For lidless packages, the nominal stiffener height can be different from the height of
the die. Therefore, the heat sink must have an island to contact the die.
• Especially for lidless packages, Xilinx advises against direct use of the θ JC parameters
(see Table 10-1) to determine the thermal performance of the device in your
application. The calculation of these parameters are done in accordance with the JEDEC
standard JESD51 where system parameters differ greatly from most applications.
Instead, run thermal simulations of the system in worst-case environmental conditions
using Delphi thermal models, which more accurately represent the device thermal
performance under all boundary conditions.
• Consider the mechanical specifications of the package as well as the selection of the
thermal interface between the die and the thermal management solution to ensure the
lowest thermal contact resistance.
• The total thermal contact of the thermal interface material is determined based on
parameters from the thermal interface supplier’s data sheet.
• See the applied pressure recommendation on page 221. Lower pressure runs the risk of
poor thermal contact and higher pressure runs the risk of damaging the device;
therefore, strict control of pressure is required.
• Consider all uncertainties in thermal modeling, including manufacturing variations
from the thermal solutions (for example, fan airflow tolerance, heat pipe or vapor
chamber performance tolerance, variation of the attachment of fins to heat sink base,
and surface flatness).
For bare-die flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded
flip-chip BGAs, the lid contacts the heat sink. The surface size of the bare-die flip-chip BGA
and lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal
material for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot
effectively cool an Zynq UltraScale+ device unless there is good physical contact between
the base of the heat sink and the top of the Zynq UltraScale+ device. The surfaces of both
the heat sink and the Zynq UltraScale+ device silicon are not absolutely smooth. This
surface roughness is observed when examined at a microscopic level. Because surface
roughness reduces the effective contact area, attaching a heat sink without a thermal
interface material is not sufficient due to inadequate surface contact.
The selection of the thermal interface (TIM) between the package and the thermal
management solution is critical to ensure the lowest thermal contact resistance. Therefore,
the following parameters must be considered.
1. The flatness of the lid and the flatness of the contact surface of the thermal solution.
2. The applied pressure of the thermal solution on the package, which must be within the
allowable maximum pressure that can be applied on the package.
3. The total thermal contact of the thermal interface material. This value is determined
based on the parameters in step 1 and step 2, which are published in the data sheet of
the thermal interface supplier.
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface
materials are listed.
• Thermal grease
• Thermal pads
• Phase change material
• Thermal paste
• Thermal adhesives
• Thermal tape
Ease of Application
A spreadable thermal grease requires the surface mount supplier to carefully use the
appropriate amount of material. Too much or too little material can cause problems. The
thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Applied Pressure from Heat Sink to the Package via Thermal Interface
Materials
RECOMMENDED: Xilinx recommends that the applied pressure on the package be in the range of 20 to
50 PSI for optimum performance of the thermal interface material (TIM) between the package and the
heat sink. Thermocouples should not be present between the package and the heat sink, as their
presence will degrade the thermal contact and result in incorrect thermal measurements. The best
practice is to select the appropriate pressure (in the 20 to 50 PSI range) for the optimum thermal
contact performance between the package and the thermal system solution, and the mechanical
integrity of the package (with the thermal solution to pass all mechanical stress and vibration
qualification tests).
RECOMMENDED: Xilinx recommends using dynamic mounting around the four corners of the device
package. On the PCB, use a bracket clip as part of the heat sink attachment to provide mechanical
package support. See Figure 11-2.
PKG
X15431-111316
Figure 11-2: Dynamic Mounting and Bracket Clips on Heat Sink Attachment
Phase Change
Thermal Interface Heat Sink
Material
Zynq
UltraScale+
Device
X20431-022818
Figure 11-3: Breaking the Bond between Thermal Interface Material and Mated Components
For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free
easily at room temperature. For larger components, in situations where minimal movement
is available, or if using fragile components, heat the component (preferred) or heat sink to
about 40°C–60°C before removal.
The guideline is 40°C–60°C, however, you might find that for your application, heating to
35°C is adequate. You might prefer to heat to 70°C which makes the phase-change thermal
interface material very soft and the components can be easily separated.
• Toluene (easiest)
• Acetone (very good)
• Isoparaffinic hydrocarbon: Isopar, Soltrol (trade names) (very good)
• Isopropyl alcohol (OK)
Measurement Debug
When performing in-system thermal testing, to ensure accurate data and not incur damage
to the device, do not place a thermocouple in between the device and the heat sink. On the
extreme side, it might cause additional mechanical and/or thermal stress to the device,
leading to damage. Even if damage does not occur, it often leads to a thicker and or uneven
thermal interface material thickness, leading to a thermal performance difference from a
system without a thermocouple. To obtain the device temperature, use the System Monitor
as a non-invasive means to get accurate device measurements while debugging the system.
Decoupling
Capacitor Silicon Underfill Substrate
UG1075_c11_01_101415
• Thermal tape
• Thermally conductive adhesive or glue
• Wire form Z-clips
• Plastic clip-ons
• Threaded stand-offs (PEMs) and compression springs
• Push-pins and compression springs
• No additional space required on the PCB. • Because of the small contact area, the tape
might not provide sufficient bond strength.
• Tape is a moderate to low thermal
conductor that could affect the thermal
performance.
Thermally • Outstanding mechanical adhesion. • Adhesive application process is
conductive • Fairly inexpensive, costs a little more than challenging and it is difficult to control the
adhesive or glue tape. amount of adhesive to use.
Metal Metal
Decoupling Tip Decoupling Tip
Capacitor Nozzle Silicon Substrate Capacitor Nozzle Silicon Substrate
Soft Tips
Metal Pick Up Tip Nozzle with Soft Tips or Metal Pick Up Tip Nozzle Can Damage
Suction Cups is Preferred the Exposed Silicon
UG1075_c11_02_101415
Decoupling Decoupling
Capacitor Capacitor
Silicon Silicon
Substrate Substrate
Decoupling
Heat Sink
Capacitor
Silicon
Substrate Silicon
Substrate
Mother Board
Preferred application of heat sink Improper application of heat sink can cause damage
1. Heat sink is aligned parallel to silicon to heat sink
2. Even bond line thickness of TIM 1. Heat sink is not aligned parallel to silicon
3. Even compressive force is applied on all sides 2. Uneven bond line thickness of TIM
3. Uneven force is applied
UG1075_c11_03_101415
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on
the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of
silicon in a pattern using automated dispensing equipment. Automated dispensers are
often used to provide a stable process speed at a relatively low cost. The optimum
dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat
transfer.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is
normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer’s specifications.
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on
the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the
heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to
help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force
transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a
defined time.
Note: The thermal adhesive tape hold time is based on manufacturer’s specifications.
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM)
Application
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on
the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
Note: The jig or fixture needs to account for the push pin depth of the heat sink.
2. PCM tape, cut to the size of the heat sink, is applied on the underside of the heat sink
at a modest angle with the use of a squeegee rubber roller. Apply pressure to help
reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking
action with the PCB holes. The compression load from springs applies the appropriate
mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the
mechanical locking action which requires manual handling. The PCB drill hole tolerances need to
be close enough to eliminate any issues concerning the heat sink attachment.
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
• From the Vivado® IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:
• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.
References
1. Zynq UltraScale+ MPSoC Overview (DS891)
2. Zynq UltraScale+ RFSoC Overview (DS889)
3. XQ UltraScale Architecture Data Sheet: Overview (DS895)
4. XA Zynq UltraScale+ MPSoC Data Sheet: Overview (DS894)
5. Zynq UltraScale+ device Packaging Specifications
6. UltraScale Architecture SelectIO Resources User Guide (UG571)
7. UltraScale Architecture Clocking Resources User Guide (UG572)
8. Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
9. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
10. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
11. UltraScale Architecture GTH Transceiver User Guide (UG576)
12. UltraScale Architecture GTY Transceiver User Guide (UG578)
13. UltraScale Architecture System Monitor User Guide (UG580)
14. UltraScale Architecture PCB Design Guide (UG583)
15. UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
16. UltraScale Architecture Configuration User Guide (UG570)
17. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424)
18. The following websites contain additional information on heat management and contact
information.
° Wakefield: www.wakefield-vette.com
° Aavid: www.aavid.com
° CTS: www.ctscorp.com
° Henkel: www.henkel.com
° Chomerics: www.chomerics.com
° Kester: www.kester.com
20. Refer to the following websites for CFD tools Xilinx supports with thermal models.
° Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, “Printed Circuit
Board Trace Thermal Analysis and Effective Conductivity”, ASME J. Electronic
Packaging, Vol. 114, pp. 413 - 419.50.