International Journal of Information and Electronics Engineering, Vol. 9, No.

1, March 2019

Bandgap Reference Layout Analysis and Design

Shi Jun


can be written, or
Abstract—Analog circuits incorporate voltage and current
2I out 2I out
reference extensively. Such references are dc quantities that + VTH1 = + VTH2 + I out RS (1)
μnCox (W / L)N μnCox Κ(W / L)N
exhibit little dependence on supply and process parameters
and a well-defined dependence on the temperature. In systems
such as A/D and D/A converters and so on, a reference is Neglecting body effect, we have
required to define the input and output full-scale range. In this
paper, the analysis and layout design of reference generator in 2I out 1
（1 - ）= I out RS (2)
CMOS technology are deal with, being focused on μnCox (W / L)N Κ
well-establishing “bandgap” technique. First,
supply-independent biasing is studied. Next, And hence
temperature-independent references are described and issues
such as the effect voltage are examined. Third, bandgap 2 1 1
I out = ? 2（1 - ） (3)
reference layouts are designed and the results are given. μnCox (W / L)N RS Κ
Finally, an example of state-of-the-art bandgap references are
studied.

Index Terms—Bandgap, layout, supply-independence,

temperature-independence, mismatch, matching.

I. INTRODUCTION
The objective of reference generation is to establish a dc
voltage or current that is independence of the supply and
process and has a well-defined behavior with temperature.
In most applications, the required temperature dependence
assumes one of three forms: (a) proportional to absolute
temperature (PTAT); (b) Constant-Gm behavior. i.e., such
that the transconductance of certain transistor remains
constant; (c) temperature independent. Therefor the task is
divided into two design problems: supply-independence
biasing and definition of the temperature variation.
II. SUPPLY-INDEPENDENT BIASING
The use of bias current and current mirrors has implicitly
assumed that a “golden” reference current is available. As
shown in Fig. 1(a) and (b), if IREF does not vary with VDD
and channel-length modulation of M2 and M3 is neglected,
then IOUT remains independent of the supply voltage.
In order to arrive at a less sensitive solution, the circuit
must bias itself, i.e., IREF must be somehow derived from
IOUT. Fig. 1 illustrates an implementation where M3 and M4
copy Iout, thereby defining IREF. Since Iout and IREF in Fig. 1
are relatively independent on VDD. If M1-M4 operate in
saturation λ≈0 where λ is the channel-length modulation
coefficient, then the circuit is governed by only one equation,
Iout=ΚIREF, and hence can support any current level! To
uniquely define the current, resister RS decreases the current
of M2 while the PMOS devices require that Iout=IREF
because they have identical dimensions. VGS1=VGS2+ID2RS
Manuscript received February 9, 2019; revised March 11, 2019.
The author is with School of Mechanical and Electronics Shanghai
Jianqiao University Shanghai P.R. China (e-mail: jshi@gench.edu.cn).
(a) (b)
(a) Addition of RS to the currents
(b) Alternative implementation eliminating body effect
Fig. 1. Establishing Supply-Independent Current using RS.
The assumption VTH1=VTH2 introduces some errors in
the foregoing calculations because the sources of M1 and
M2 are at different voltage. Shown in Fig. 1(b), a simple
remedy is to place the resistor in the source of M3 while
eliminating body effect by tying the source and bulk of each
PMOS transistor. The circuit of Fig. 1(a) and (b) exhibit
little supply dependence if channel-length modulation is
negligible. For this reason, relatively long channels are used
for all of the transistors in the circuit.
III. TEMPERATURE-INDEPENDENT REFERENCE
Reference voltage or currents that exhibit little
dependence on temperature prove essential in many analog
circuits. It is interesting to note that, since most process
parameters vary with temperature, if a reference is
temperature-independent, then it is usually
process-independent as well.
A. Negative-TC (Temperature Coefficient) Voltage
The base-emitter voltage of bipolar transistors or, more
generally, the forward voltage of a PN-junction diode
exhibits a negative.

doi: 10.18178/ijiee.2019.9.1.695 1
 International Journal of Information and Electronics Engineering, Vol. 9, No. 1, March 2019

For a bipolar device we have IC = I S exp(VBE / VT ) , =VT ln n (12)

where VT =T / q , The saturation current IS is proportional
Thus, the VBE difference exhibits a positive temperature
to Tni2 , where μ denotes the mobility of minority coefficient as follow (13).
carriers, κ is Boltzmann constant and ni is the intrinsic V BE 
= ln n (13)
minority carrier concentration of silicon. T q

E g This TC is independent of the temperature or behavior of

I S =bT 4  m exp (4) the collector current. Specially, when the circuit likes that
T shown as in Fig. 3, neglecting IB (base current), the equation
where b is a proportionally factor, Eg≈1.12eV is the can be written as (14) and (15).
bandgap energy of silicon and m≈-3/2. Writing nI 0 I
IC V BE =VT ln  VT ln 0 (14)
V BE  VT ln , we can compute the TC of the base-emitter IS 1 mI S 2
IS
voltage as follow. =VT ln nm (15)
V BE V I V I S C. Bandgap Reference
 T ln C  T (5)
T T I S I S T With the negative- and positive-TC voltages obtained
above, a reference having a nominally zero temperature
From (4), the equation (6) is obtained.
coefficient can be developed. The equation is written as
I S E E E (6) follow
 b(4  m )T 3  m exp g  bT 4  m(exp g )( g 2 )
T T T T
VREF  1VBE  2(VT ln n )
Therefore,
where VT ln n is the difference between the base-emitter
VT I S V E
 (4  m ) T  g 2 VT (7) voltages of the two bipolar transistors operating at different
I S T T T temperature
current densities. Since at room
With the aid of (5) and (7), the equation (8) and (9) are V BE / T  1.5mV /  whereas VT / T  0.087mV /  ,
obtained. we may set 1 =1 and choose 2 ln n such that
V BE V I V E ( 2 ln n )(0.087 mV / =1.5mV /  ). That is, 2 ln n  17.2 ,
 T ln C  (4  m ) T  g 2 VT (8)
T T IS T T indicating that for zero TC:

V  (4  m )VT  E g / q VREF  VBE  17.2VT  1.25V (16)

= BE (9)
T As shown in Fig. 2, it is an implementation
The equation (9) gives the temperature coefficient of the accomplishing both to guarantee VX=VY and to arrive at a
base-emitter voltage at a given temperature T, revealing current equal to VT ln n / R 3 through the right branch,
dependence on the magnitude of VBE itself. With because of VBE 1  VBE 2  VT ln n , and hence an output voltage
VBE≈750mV and T=300°K, ∂VBE/∂T≈1.5mV/°K.
of the reference voltage is obtained as follow (17):
B. Positive-TC Voltage
If two bipolar transistors operate at unequal current
densities, then the difference between their base-emitter
voltages is directly proportional to the absolute temperature
[1]. As shown in Fig. 2, if two identical transistors (IS1=IS2)
are biased at collector currents of nIO and IO and their base
currents are negligible. From the equation
IC
IC  I S exp(VBE / VT ) , then V BE =VT ln
IS . Therefore, the
equation (10), (11) and (12) are obtained.

VBE =VBE 1  VBE 2 (10)

Fig. 2. Conceptual generation of temperature-independent voltage.

nI I
=VT ln 0  VT ln 0 (11)
IS 1 IS 2 VT ln n
Vout  V BE 2  (R 2  R 3 ) (17)
R3

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 International Journal of Information and Electronics Engineering, Vol. 9, No. 1, March 2019

R2 temperature, raising the temperature coefficient of the

 V BE 2  VT ln n(1  ) (18)
output voltage [2].
R3

For a zero TC, must be obtained by

n=31 and R 3 / R 2  4 .

D. Collector Current Variation

From Fig. 2, if the collector current of Q1 and Q2, given
by(VT ln n ) / R 3 , are PTAT, whereas V BE / T  1.5mV / K
was derived for a constant current, then the formation (19)

can obtained by IC 1  IC 2  (VT ln n / R 3 ). Fig. 3. Realization of a pnp bipolar transistor in CMOS technology.

V BE V I 1 I C 1 I S
 T ln C  VT (  ) (19)
T T IS I C T I S T

Since IC / T  (VT ln n ) / R 3T  IC / T , so (19)

can be written as (20)
V BE V I V V I S (20)
 T ln C  T  T
T T IS T T T
Therefore equation (9) is modified as (21), indicating that
TC is slightly negative than 1.5mV / K .

V BE V  (3  m )VT  E S / q
 BE (21)
T T Fig. 4. Effect of OPAMP offset on the reference voltage.

E. Compatibility with CMOS Technology

In n-well processes, a pnp transistor can be formed as G. Other Elements
depicted in Fig. 3 in which exhibits the exponential Feedback Polarity: The feedback signal produced by the
characteristics of bipolar devices for both negative and OPAMP in the circuit of Fig. 2 returns to both of its input.
positive-TC quantities on which the derivation of a The negative feedback factor is given by (24).
temperature-independent voltage relies.
1  R3
A p+ diffusion inside an n-well serves as the emitter and gm2 (24)
the n-well itself as the base. The p-substrate acts as the N 
1  R3  R2
collector and it is inevitably connected to the most negative gm2
supply that is usually ground. So the npn in Fig. 2 can be
replace by pnp of which base and emitter are grounded. And the positive feedback factor by (25).

F. OPAMP Offset and Output Impedance 1

g m1
The output voltage of the OPAMP is not zero if the input P  (25)
is set to zero because of asymmetries, OPAMPs suffer from 1  R1
g m1
input “offsets”. As shown in Fig. 4, the input offset voltage
of the OPAMP introduces errors in the output voltage,
which is quantified as VBE 1  VOS  VBE 2  R 3IC 2 (if A1 is large)
To ensure an overall negative feedback, P must be

and Vout  VBE 2  (R 3  R 2 )IC 2 . Thus, less than N , perfectly by roughly a factor of two so that the
circuit’s transient response remains well-behaved with large
V  V BE 2  VOS capacitive loads.
Vout  V BE 2  (R 3  R 2 ) BE 1 (22)
R2 Bandgap Reference: The voltage generated according to
(16) is called a “bandgap reference”. The output voltage is
R2 written as follow:
 V BE 2  (1  （) V ln n  VOS） (23)
R3 T VREF  VBE  VT ln n (26)

where assuming IC 2  IC 1 despite the offset voltage. The And hence:

R 2 , introducing errors VREF V BE V
result is that VOS is amplified by 1+   T ln n (27)
R3 T T T
in Vout . More importantly, VOS itself varies with

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 International Journal of Information and Electronics Engineering, Vol. 9, No. 1, March 2019

Setting this to zero and substituting for VBE from (9), A. Layout Matching for Two Current Sources
T
The widely used approach for predicting the effects of the
(28) can be obtained.
threshold voltage gradient is based upon deriving an
Eg equivalent threshold voltage for the device as given by the
V BE  (4  m )VT  VT
q   ln n (28) following equation [5].
T T
(29) can be obtained from (26) and (28).  VTH (X ,Y )dxdy
VTHeq  Active _ Area (32)
Eg Active _ Area
VREF   (4  m )VT (29)
q where VTHeq can be viewed as the equivalent threshold
Supply Dependence and Start-Up: As shown in Fig. 2, the voltage at the moment of the device. The most interesting
output voltage is relatively independent of the supply topology is shown in Fig. 5. With totally four symmetric
voltage so long as the open-loop gain of the OPAMP is axes, its performance is definitely better than those of other
sufficiently high. The circuit may require a start-up topology [6], [9]. And the Four-Segment layout has the
mechanism because if VX and VY are equal to zero, the input performance as shown in TABLE I. Assuming that the
differential pair of the OPAMP may turn off. mismatch of the threshold voltage is equally distributed
between the M1 and M2 transistors, the first-order
expression of the current ratio is obtained as follows (33)
IV. MISMATCH
IO 2VTHN
In general, the mismatches caused by manufacturing  1 (33)
processes can be classified into systematic mismatch and ID1 (VGS  VTHN )
random mismatch. The random mismatch can only be
reduced by increasing layout area, but the systematic From (32), with the decrease of VGS, the offset between
mismatch can always be alleviated through proper layout current will increase due to the mismatch of threshold
techniques [3]. voltage. Because the threshold voltage is very sensitive to
Expressing the characteristics of a MOSFET in saturation the gradient variation of process parameters, the current
as I D  (1 / 2)C OX (W / L )(VGS  VTH )2 , mismatches between deviation caused by the threshold voltage mismatch will be
especially serious when the distance between MOS
 , C OX , W, L, and VTH result in mismatch between drain transistors is very large [8].
current (for a given VGS ) or gate-source voltages (for a
given drain current) of two nominally-identical transistors. It
is assumed that the dominating effects in random
mismatches of a transistor are two independent variables:
current factor differences (  C OX W / L ) and
threshold voltage differences VTH . (30) and (31) are
obtained.
AK
 = (30)
WL

AVTH
VTH  (31)
Fig. 4. Four segment rectangular layout.
WL
TABLE I: THE PERFORMANCE OF FOUR-SEGMENT LAYOUT
where AVTH and AK are proportionality factors. AVTH has Worst Mismatch (%)
Simple integral Segmented Distributed Effective
been observed to scale down with the gate oxide thickness model integral model simulator Resolution
[4]. Mismatch lead to three significant phenomena: dc offset, 0 2.0966e-14 1.4090e-4 18-bit
finite even-order distortion, and lower common-mode
rejection.
B. Layout Matching for Differential Pair
The performance of the differential pair is closely related
V. LAYOUT MATCHING to the matching between the devices. Using the centroid
layout technology, the first order mismatch caused by oxide
As previously analyzed and modeled,VREF , I D are always gradient, stress gradient and other process deviations is
minimization.
mismatched by  , C OX , W, L, and VTH . Simple layout An algorithm that is used to determine the number of
are prone to process variation, e.g. VTH , KP , C OX . rows and columns required for the matrix is based on the
following equation (34) [7].
Matched transistor requires elaborated layout techniques.

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 International Journal of Information and Electronics Engineering, Vol. 9, No. 1, March 2019

2  Wtotal  R  C  K 3 structures are used in order to prevent the latchup effect.

Ar  (34)
C 2  K1  C  K 2
where Ar is the aspect ratio, Wtotal is the total width of the VI. A CASE STUDY OF BANDGAP REFERENCE
largest transistor, R is number of rows, C is the number of As shown in Fig. 6, it is a bandgap reference circuit used
columns, K1 is a function of the transistor length, K2 for LDO(Low-Drop linear regulator). And Its corresponding
corresponds to the space for vertical routing, and K3 is the layout is shown in Fig. 7.
space for horizontal routing. C(column) can then be
determined using a optimization algorithm based on the
requirements that the number of columns is even and both
the number of R and C are integers [8]. Fig. 5 illustrates the
layout of the differential input pair. Note that each device
has the exact same metal and poly routing and that the
layout is completely symmetrical about the center of the
circuit.

Fig. 6. A Bandgap reference circuit.

After analysis and design, the layout results are ideal.

Post simulation were showed that the output reference
voltage was 1.2156 and its temperature coefficient was 0.43
×10-6/℃ at the range of -40℃ ~ 125℃. The power supply
rejection ratio (PSRR) was lower than -83dB at low
frequency.

Fig. 5. Interdigitated differential input pair layout.

The offset voltage VOS of the differential input pair caused

by the mismatch of threshold voltage ∆VTHN, geometric size
∆(W/L) and load resistance ∆RL can be calculated by (35).
VGS  VTHN R L (W / L ) (35)
VOS  VTHN  [  ]
2 RL (W / L )

The mismatch of threshold voltage must be reduced by

optimized layout design. The mismatch between geometric
size and load resistance can be reduced by using smaller VGS
(making VGS close to VTHN). This conclusion can be
compared with (32). (32) is shown that the use of smaller
VGS in current mirrors will lead to larger current mirror
errors. Fig. 7. Bandgap reference layout.

C. Other Layout Matching

Another layout matching technique is that the dummy
MOS on the ends of the rows used to reduce the
undercutting of the gate oxide on the end devices.
Latchup is a parasitic effect in CMOS technology, it is a
PNPN parasitic structure formed by at least two coupled
bipolar transistor. When a transitory voltage/current
overshoot/undershoot at a input/output node occurs, PNP
structure can be turned on and a low impedance guardring
VII. CONCLUSION
A practical case study of bandgap reference is studied
from analysis, design to layout implementation. The study
shows that VBE, threshold voltage and VGS are important
factors affecting bandgap reference, and shows how to
analyze and design layout to satisfy these circuit
requirements. The simulation results & layout can provide
design reference for circuit or layout engineer.

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Shi Jun was obtained the master degree of science,
[5] M. F. Lan, A. Tammineedi, and R. Geiger, “A new current layout
major in computer & microelectronics in HIT(Harbin
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& circuits analysis and layout designs in Xi'an
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Afterwards she engaged in professional teaching in
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high school and so far in SJQU Shanghai, P. R.
China.