#TUTORIALSPOINT

Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.
Block diagram –

It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into
two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest)
mode or in mode 0 of input-output mode of 8255. Port B can work in either mode or in mode 1 of
input-output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of port A
and port C upper. Control group B consists of port C lower and port B.
Depending upon the value if CS’, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).

CS’ A1 A0 SELECTION ADDRESS

0 0 0 PORT A 80 H
 CS’ A1 A0 SELECTION ADDRESS

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Seletion X

Pin diagram –

 PA0 – PA7 – Pins of port A

 PB0 – PB7 – Pins of port B
 PC0 – PC7 – Pins of port C
 D0 – D7 – Data pins for the transfer of data
 RESET – Reset input
 RD’ – Read input
 WR’ – Write input
 CS’ – Chip select
 A1 and A0 – Address pins
Operating modes –
1. Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are
used for set or reset.
2. Input-Outpt mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into
three modes:

 Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function
or simple output function. In this mode there is no interrupt handling capacity.
 Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port
B can work as simple input port or simple output port, and port C bits are used for
handshake signals before actual data transmission. It has interrupt handling capacity
and input and output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of
processor is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of the speed of
the CPU and the peripherals.
  Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can
work either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also
has interrupt handling capacity.

Let us first take a look at the pin diagram of Intel 8255A −

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus.
Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and
status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It
accepts the input from the CPU address and control buses, and in turn issues command to both
the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A 0 & A1 are
connected to the microprocessor address lines.
Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register
 1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.

RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.

RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table showing
their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

Describe the types of interrupts in 8086

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that interrupt
with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on
how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin
to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and
INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called
interrupt acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the
stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts
are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag
instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then
the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first
‘0’ means INTA informs the external device to get ready and during the second ‘0’ the
microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address are pushed on to
the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts. These
interrupt instructions can be used to test the working of various interrupt handlers. It includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt
type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2
is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program
so that when the processor reaches there, then it stops the normal execution of program and follows
the break-point procedure.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
  CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the
name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is
set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag
is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0

#8259PIC
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and
8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259,
we can increase the interrupt handling capability. This chip combines the multi-interrupt input source
to single interrupt output. This provides 8-interrupts from IR0 to IR7. Let us see some features of
this microprocessor.
 This chip is designed for 8085 and 8086.
 It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed.

The pin level diagram and functional pin diagram is like below -
The block diagram is like below -
We can see through above diagram that there are total 28 pins in 8259 PIC microprocessor where
Vcc :5V Power supply and Gnd: ground. Other pins use are explained below.
Block Diagram of 8259 PIC microprocessor –
The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as
a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the
control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259
microprocessor, it transfer the opcode of the selected Interrupt and address of the Interrupt
service sub routine to the other connected microprocessor. The data bus buffer consists of 8
bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data
can be transferred at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins
are active low pins used for read and write operations.
3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block. It has pin
INTR which is connected with other microprocessor for taking interrupt request and pin INT
for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high
then this causes the value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
 5. Interrupt service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins by
using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave
and in Buffered mode, SP/EN pin is used as an output to enable data bus.

Interrupt Vector Table :::::::::::

Now the question is “How to get the values of CS and IP register ?” The 8086 gets the new
values of CS and IP register from four memory addresses. When it responds to an interrupt,
the 8686 goes to memory locations to get the CS and IP values for the start of the interrupt
service routine. In an 8086 Interrupt system the first 1 Kbyte of memory from 00000H to
003FFH is reserved for storing the starting addresses of interrupt service routines. This block
of memory is often called the interrupt vector table or the interrupt pointer table. Since 4
bytes are required to store the CS and IP values for each interrupt service procedure, the
table can hold the starting addresses for 256 interrupt service routines. Fig. 9.2 shows how
the 256 interrupt pointers are arranged in the memory table.
An interrupt vector table (IVT) is a data structure that associates a list of interrupt
handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the
interrupt vector table, called an interrupt vector, is the address of an interrupt handler.
While the concept is common across processor architectures, IVTs may be implemented
in architecture-specific fashions. For example, a dispatch table is one method of
implementing an interrupt vector table.

Each interrupt type is given a number between 0 to 255 and the address of each interrupt js
found by multiplying the type by 4 e.g. for type 11, interrupt address is 11 x 4 = 4410= 0002CH
Only first five types have explicit definitions such as divide by zero and non maskable
interrupt. The next 27 interrupt types, from 5 to 31, are reserved by Intel for use in future
microprocessors. The upper 224 interrupt types, from 32 to 255, are available for user for
hardware or software interrupts.
When the 8086 Interrupt responds to an interrupt, it automatically goes to the specified
location in the interrupt vector table to get the starting address of interrupt service routine.
So user has to load these starting addresses for different routines at the start of the program.