EE 3CL4, §6

1 / 101
Tim Davidson

Compensators

Lead
compensation
Design via Root
EE3CL4:
Locus
Lead Compensator
example
Introduction to Linear Control Systems
Cascade
compensation
Section 6: Design of Lead and Lag Controllers using
and
steady-state
Root Locus
errors

Lag
Compensation
Design via Root
Tim Davidson
Locus
Lag compensator
example
McMaster University
Prop. vs Lead
vs Lag

Insights Winter 2020

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
2 / 101
Tim Davidson Outline
Compensators 1 Compensators
Lead
compensation 2 Lead compensation
Design via Root
Locus Design via Root Locus
Lead Compensator
example
Lead Compensator example
Cascade
compensation
and
3 Cascade compensation and steady-state errors
steady-state
errors 4 Lag Compensation
Lag
Compensation
Design via Root Locus
Design via Root
Locus
Lag compensator example
Lag compensator
example
5 Prop. vs Lead vs Lag
Prop. vs Lead
vs Lag
6 Insights
Insights

Lead-Lag 7 Lead-Lag compensation

compensation
Lead-Lag Lead-Lag Compensator example
Compensator
example

A prelude
8 A prelude
EE 3CL4, §6
4 / 101
Tim Davidson Compensators
Compensators
• Early in the course we provided some useful guidelines
Lead regarding the relationships between the pole positions
compensation
Design via Root
of a system and certain aspects of its performance
Locus
Lead Compensator
example
• Using root locus techniques, we have seen how the
Cascade pole positions of a closed loop can be adjusted by
compensation
and varying a parameter
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example • What happens if we are unable to obtain that
Prop. vs Lead
vs Lag
performance that we want by doing this?
• Ask ourselves whether this is really the performance
Insights

Lead-Lag
that we want
compensation • Ask whether we can change the system,
Lead-Lag
Compensator
example
say by buying different components
• seek to compensate for the undesirable aspects of the
A prelude
process
EE 3CL4, §6
5 / 101
Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors
• Usually, the plant is a physical process
Lag • If commands and measurements are made electrically,
Compensation
Design via Root
compensator is often an electric circuit
Locus
Lag compensator • General form of the (linear) compensators we will consider is
example

Prop. vs Lead
Kc M (s + zi )
Q
vs Lag Gc (s) = Qn i=1
Insights j=1 (s + pj )

Lead-Lag
compensation
Lead-Lag
• Therefore, the cascade compensator adds open loop poles and
Compensator
example open loop zeros
A prelude • These will change the shape of the root locus
EE 3CL4, §6
6 / 101
Tim Davidson Compensator design
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation • Where should we put new poles and zeros to achieve desired
and
steady-state
performance?
errors • That is the art of compensator design
Lag
Compensation • We will consider first order compensators of the form
Design via Root
Locus
Lag compensator Kc (s + z) K̃c (1 + s/z)
example Gc (s) = = , where K̃c = Kc z/p
Prop. vs Lead
(s + p) (1 + s/p)
vs Lag

Insights • with the pole −p in the left half plane

Lead-Lag • and the zero, −z in the left half plane, too
compensation
Lead-Lag
Compensator
• For reasons that will soon become clear
example
• when |z| < |p|: phase lead network
A prelude
• when |z| > |p|: phase lag network
EE 3CL4, §6
8 / 101
Tim Davidson Lead compensation
Compensators

Lead
compensation
Design via Root
Locus Kc (s + z)
Lead Compensator Gc (s) =
example
(s + p)
Cascade
compensation with |z| < |p|. That is, zero closer to origin than pole
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights Let p = 1/τp and z = 1/(αlead τp ). Since z < p, αlead > 1.

Lead-Lag
compensation
Define K̃c = Kc z/p = Kc /αlead . Then
Lead-Lag
Compensator
example Kc (s + z) K̃c (1 + αlead τp s)
Gc (s) = =
A prelude (s + p) (1 + τp s)
EE 3CL4, §6
9 / 101
Tim Davidson Lead compensation
Kc (s+z) K̃c (1+αlead τp s)
With |z| < |p|, αlead > 1, Gc (s) = (s+p) = (1+τp s)
Compensators

Lead
• Frequency response:
compensation
Design via Root K̃c (1 + jωαlead τp )
Locus
Lead Compensator
Gc (jω) =
example (1 + jωτp )
Cascade
compensation
and • Bode diagram (in the figure, K1 = K̃c )
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
• Between ω = z and ω = p, |Gc (jω)| ≈ K̃c ωαlead τp
Lead-Lag
Compensator
• What kind of operator has a frequency response with
example

A prelude
magnitude proportional to ω? Differentiator
• Note that the phase is positive. Hence “phase lead”
EE 3CL4, §6
10 / 101
Tim Davidson A passive phase lead network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
V2 (s)
Insights Homework: Show that V1 (s) has the phase lead
Lead-Lag
compensation
characteristic
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
11 / 101
Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
12 / 101
Tim Davidson Principles of Lead design via
Compensators Root Locus
Lead
compensation
• The compensator adds poles and zeros to the P(s) in
Design via Root
Locus the root locus procedure.
Lead Compensator
example
• Hence we can change the shape of the root locus.
Cascade
compensation
and • If we can capture desirable performance in terms of
steady-state
errors positions of closed loop poles
Lag
Compensation
• then compensator design problem reduces to:
Design via Root
Locus
• changing the shape of the root locus so that these
Lag compensator
example
desired closed-loop pole positions appear on the root
Prop. vs Lead locus
vs Lag • finding the gain that places the closed-loop pole
Insights positions at their desired positions
Lead-Lag
compensation
Lead-Lag • What tools do we have to do this?
Compensator
example
• Phase criterion and magnitude criterion, respectively
A prelude
EE 3CL4, §6
13 / 101
Tim Davidson Root Locus Principles
Compensators
• The point s0 is on the root locus of P(s) if 1 + KP(s0 ) = 0.
KG M
Q
(s+zi )
Lead • In first order compensator design with G(s) = Qn i=1
compensation j=1 (s+pj )
Design via Root QM
Kc (s+z) (s+z) Qi=1 (s+zi )
Locus
and Gc (s) = (s+p) , we have P(s) = (s+p) n and
j=1 (s+pj )
Lead Compensator
example

Cascade
K = Kc KG . We will restrict attention to the case of K > 0
compensation
and • Phase cond. s0 is on root locus if ∠P(s0 ) = 180◦ + ` 360◦ :
steady-state
errors
M
X n
X
Lag
Compensation (angle from −zi to s0 ) − (angle from −pj to s0 )
Design via Root
Locus i=1 j=1
Lag compensator
example + (angle from −z to s0 ) − (angle from −p to s0 )
Prop. vs Lead
vs Lag = 180◦ + ` 360◦
Insights • Mag. cond. If s0 satisfies phase condition, the gain that puts
Lead-Lag
compensation
a closed-loop pole at s0 is K = 1/|P(s0 )|:
Lead-Lag Qn
j=1 (dist from −pj to s0 ) (dist from −p to s0 )
Compensator
example
K = QM ×
A prelude (dist from −zi to s0 ) (dist from −z to s0 )
i=1
EE 3CL4, §6
14 / 101
Tim Davidson RL design: Basic procedure
Compensators 1 Translate design specifications into desired positions of
Lead
dominant poles
compensation
Design via Root 2 Sketch root locus of uncompensated system to see if desired
Locus
Lead Compensator positions can be achieved
example

Cascade 3 If not, choose the positions of the pole and zero of the
compensation
and
compensator so that the desired positions lie on the root
steady-state locus (phase criterion), if that is possible
errors

Lag 4 Evaluate the gain required to put the poles there

Compensation
Design via Root
(magnitude criterion)
Locus
Lag compensator
example
5 Evaluate the total system gain so that the steady-state error
Prop. vs Lead
constants can be determined
vs Lag
6 If the steady state error constants are not satisfactory, repeat
Insights

Lead-Lag This procedure enables relatively straightforward design of

compensation systems with specifications in terms of rise time, settling time, and
Lead-Lag
Compensator
example
overshoot; i.e., the transient response.
A prelude For systems with steady-state error specifications, Bode (and
Nyquist) methods may be more straightforward (later)
EE 3CL4, §6
15 / 101
Tim Davidson Lead Comp. example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade 1
compensation Consider a case with G(s) = s(s+2) and H(s) = 1.
and
steady-state
Design a lead compensator to achieve:
errors
• damping coefficient ζ ≈ 0.45 and
Lag
Compensation
Design via Root
• velocity error constant Kv = lims→0 sGc (s)G(s) ≥ 20
Locus
Lag compensator
example • swift transient response (small settling time)
Prop. vs Lead
vs Lag
What to do?
Insights

Lead-Lag
• Can we achieve this with proportional control?
compensation
Lead-Lag
Compensator
• If not we will attempt lead control
example

A prelude
EE 3CL4, §6
16 / 101
Tim Davidson Attempt prop. control
Compensators

Lead • Closed loop poles that correspond to ζ = 0.45 lie on

compensation
Design via Root
Locus
rays of angle cos−1 (0.45) ≈ 60◦ to neg. real axis
Lead Compensator
example • Sketch them
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
17 / 101
Tim Davidson Attempt prop. control, II
Compensators • Add sketch of root locus of 1
s(s+2)
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
• Is there an intersection? Yes
Lead-Lag
Compensator
example
• What is the value of K = Kamp KG that puts closed-loop
A prelude poles at intersection point?
EE 3CL4, §6
18 / 101
Tim Davidson Attempt prop. control, III
Q
Compensators distances from OL poles
Lead
• That gain is K = Q
compensation
distances from OL zeros
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag • K = d1 d2 = 5.
Compensator
example
• Since KG = 1, Kamp = 5.
A prelude
EE 3CL4, §6
19 / 101
Tim Davidson Assessing our prop. design
• Kamp = 5.
Compensators
• Place actual closed loop poles on the root locus (asterisks)
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights • As expected, they are at the target locations (open squares)

Lead-Lag
compensation • What is the corresponding Kv ?
• Kv = lims→0 sGc (s)G(s) = Kamp
Lead-Lag
Compensator
example 2
= 2.5 :(
A prelude
• Do the closed-loop poles have responses that decay quickly?
No, Ts ≈ 4s
EE 3CL4, §6
20 / 101
Tim Davidson Prop. control, step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
21 / 101
Tim Davidson Lead compensated design
Compensators
• Where should the closed-loop poles be? cos−1 (0.45) ≈ 60◦
Lead
• Note that the settling time is not specified; it only needs to be
compensation
Design via Root
small. This provides design flexibility.
Locus
Lead Compensator
• However, we need a large Kv which will require large gain.
example
Need desired positions far from open loop poles.
Cascade
compensation • Let’s start with desired roots at −4 ± j8 (purple squares)
and √
steady-state • This pair has Ts = 1s and ωn = 42 + 82 ≈ 8.9
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
22 / 101
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
• Lead design questions:
Insights
• How do we choose z and p to ensure that there exists a
Lead-Lag
compensation gain that will put closed loop poles at the squares?
Lead-Lag
Compensator • Once we have done that, how do we find the gain that
example

A prelude
puts the closed-loop poles at the squares?
EE 3CL4, §6
23 / 101
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus • We want squares to be on the root locus
Lag compensator
example
• That is, if s0 denotes the position of one of the squares,
Prop. vs Lead
vs Lag
we want 1 + Gc (s0 )G(s0 ) = 1 + KP(s0 ) = 0
Insights • In other words, we want P(s0 ) = −1/K
Lead-Lag
compensation
• Separating that complex-valued equation into magnitude and
Lead-Lag
Compensator
phase components, we want
example
• ∠P(s0 ) = 180◦ ; phase criterion
A prelude
• |P(s0 )| = 1/K ; magnitude criterion
EE 3CL4, §6
24 / 101
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example
• To find z and p we use the phase criterion
Prop. vs Lead
vs Lag X X
(angles from OL zeros) − (angles from OL poles) = 180◦
Insights

Lead-Lag =⇒ θz − θ0 − θ2 − θp = 180◦
compensation
Lead-Lag • Then, to find Kc we use the magnitude criterion
Compensator
example
Q
distances from OL poles d0 d2 dp
A prelude K = Kc KG = Q =
distances from OL zeros dz
EE 3CL4, §6
25 / 101
Tim Davidson How to choose z and p
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
• Can we start to think of this geometrically, rather than algebraically?
Design via Root
Locus
• Phase condition equation at s0 : θz − θp = 180◦ + θ0 + θ2
Lag compensator
example • One linear equation, two unknowns. Many solutions
Prop. vs Lead • However, we can find out something about ∠Gc (s0 )
vs Lag
• s+z
Since Gc (s) = Kc s+p , with Kc > 0,
Insights
∠Gc (s0 ) = ∠(s0 + z) − ∠(s0 + p) = θz − θp
Lead-Lag
compensation Can you see this angle in the figure? It is φc
Lead-Lag
Compensator
• Since 90◦ < θ0 , θ2 < 180, =⇒ 0 < φc < 180
example
• That is, we need a phase lead compensator
A prelude
• What does that say about z and p? −p < −z
EE 3CL4, §6
26 / 101
Tim Davidson Simplifying rule of thumb
• What are good choices for z and p amongst those that provide the
Compensators
right amount of phase lead?
Lead
compensation • Simplifying rule of thumb: When amount of phase lead required at
Design via Root
Locus s0 is less than 90◦ , place zero on the real axis “underneath” the
Lead Compensator
example desired closed-loop pole positions.
Cascade • When applicable, this reduces the complexity of the design
compensation
and procedure; now we only have to design the pole position; often a
steady-state reasonable choice
errors
• Can iterate on zero position as needed
Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
27 / 101
Tim Davidson How to choose p
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example
With rule of thumb in place
Prop. vs Lead
vs Lag • Find θp using
Insights X X
angles from OL zeros − angles from OL poles = 180◦
Lead-Lag
compensation
Lead-Lag
∼ 90 − (116 + 104 + θp ) = 180
Compensator
example =⇒ θp ≈ 50
A prelude
• Hence, pole at −p = −4 − 8/ tan(θp ) ≈ −10.86
EE 3CL4, §6
28 / 101
Tim Davidson Checking our work
Compensators

Lead
compensation Does the root locus for the compensated system go through
Design via Root
Locus the desired positions?
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
29 / 101
Tim Davidson How to choose Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
• What is the gain that puts closed-loop poles in the
example
boxes? Recall
Prop. vs Lead Q
vs Lag distances from OL poles d0 d2 dp
Insights K = Kc KG = Q =
distances from OL zeros dz
Lead-Lag
compensation
Lead-Lag
Compensator
example
• In this example KG = 1
A prelude d0 d2 dp 8.94(8.25)(10.54)
• Therefore, Kc = dz ≈ 8 ≈ 97.1
EE 3CL4, §6
30 / 101
Tim Davidson Summarizing initial design
97.1(s+4)
Compensators
• Our compensator is Gc (s) = (s+10.86)
97.1(s+4)
Lead • The compensated open loop is Gc (s)G(s) = s(s+2)(s+10.86)
compensation
Design via Root
Locus • Mark all closed-loop poles on the root locus (asterisks)
Lead Compensator
example Note that conjugate pair hit the target (as designed),
Cascade and that the real pole is not far from the (open/closed loop) zero
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude • Velocity constant: Kv = lims→0 sGc (s)G(s) ≈ 17.9 :(

EE 3CL4, §6
31 / 101
Tim Davidson What to do now?
Compensators
• We tried hard, but did not achieve the design specs
Lead
compensation
Design via Root
• Let’s go back and re-examine our choices
Locus
Lead Compensator
example • Zero position of compensator was chosen via rule of thumb
Cascade
compensation • Can we do better?
and
steady-state
Yes, but two parameter design becomes trickier.
errors
• What were other choices that we made?
Lag
Compensation
Design via Root
• We chose desired poles to be of magnitude ωn ≈ 8.9
Locus
Lag compensator
example • We could choose them to be further away;
Prop. vs Lead larger gain to get there (and faster transient response)
vs Lag

Insights
• By how much?
Lead-Lag
compensation
• Show that when desired poles have ωn = 10 as well as the
Lead-Lag
Compensator
required ζ ≈ 0.45, then the choice of z ≈ 4.47, p ≈ 12.5 and
example
KC ≈ 125 results in Kv ≈ 22.3
A prelude
EE 3CL4, §6
32 / 101
Tim Davidson Root Locus, new lead comp.
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
33 / 101
Tim Davidson Comparisons to prop. design
Compensators

Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
34 / 101
Tim Davidson Comparisons
Compensators Prop.-contr. Lead contr.
Lead
compensation 125(s+4.47)
Design via Root
Controller, GC (s) 5 (s+12.5)
Locus
Lead Compensator
5 125(s+4.47) 1
example OL TF, GC (s)G(s) s(s+2) (s+12.5) s(s+2)
Cascade
compensation Y (s) 5 125(s+4.47)
and CL TF, R(s) s(s+2)+5 s(s+2)(s+12.5)+125(s+4.47)
steady-state
errors
CL poles −1 ± j2 −4.47 ± j8.94, −5.59
Lag
Compensation
Design via Root
CL zeros ∞, ∞ −4.47, ∞, ∞
Locus
Lag compensator
5 131(1+0.013s) 1.71
example CL TF, again s2 +2s+5 s2 +8.94s+100
− s+5.59
Prop. vs Lead
vs Lag

Insights • Complex conjugate poles still dominate

Lead-Lag
compensation • Closed-loop zero at -4.47 (which is also an open-loop
Lead-Lag
Compensator
example
zero) reduces impact of closed-loop pole at -5.59;
A prelude
residue of that pole in partial fraction expansion is small
EE 3CL4, §6
35 / 101
Tim Davidson New lead comp., ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
36 / 101
Tim Davidson New lead comp., ramp
Compensators response, detail
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
37 / 101
Tim Davidson New lead comp., step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag Note faster settling time than prop. controlled loop,

compensation
Lead-Lag
Compensator
However, the CL zero has increased the overshoot a little
example

A prelude Perhaps we should go back and re-design for ζ ≈ 0.40

in order to better control the overshoot
EE 3CL4, §6
38 / 101
Tim Davidson Outcomes
Compensators
• Root locus approach to phase lead design was
Lead reasonably successful in terms of putting dominant
compensation
Design via Root
poles in desired positions; e.g., in terms of ζ and ωn
Locus
Lead Compensator
example • We did this by positioning the pole and zero of the lead
Cascade
compensation
compensator so as to change the shape of the root
and
steady-state
locus
errors

Lag
• However, root locus approach does not provide
Compensation
Design via Root
independent control over steady-state error constants
Locus
Lag compensator
(details upcoming)
example

Prop. vs Lead • That said, since lead compensators reduce the DC gain
vs Lag

Insights
(they resemble differentiators), they are not normally
Lead-Lag
used to control steady-state error.
compensation
Lead-Lag
Compensator
• The goal of our lag compensator design will be to
example
increase the steady-state error constants, without
A prelude
moving the other poles too far
EE 3CL4, §6
40 / 101
Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors • Throughout this lecture, and all the discussion on cascade
Lag compensation, we will consider the case in which H(s) = 1.
Compensation
Design via Root
Locus • We will consider first order compensators of the form
Lag compensator
example

Prop. vs Lead
Kc (s + z)
vs Lag
Gc (s) =
(s + p)
Insights

Lead-Lag with the pole, −p, and the zero, −z, both in the left half plane
compensation
Lead-Lag
Compensator
• when |z| < |p|: phase lead network
example

A prelude • when |z| > |p|: phase lag network

EE 3CL4, §6
41 / 101
Tim Davidson Steady-state errors
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
If closed loop stable, steady state error for input R(s):
example
R(s)
Cascade ess = lim e(t) = lim s
compensation t→∞ s→0 1 + GC (s)G(s)
and
steady-state Q
KG i (s+zi ) KC (s+z)
errors Let G(s) = Q and consider GC (s) =
j (s+pj ) (s+p)
Lag
Compensation • Consider the case in which G(s) is a type-0 system.
Design via Root
Locus • Steady state error due to a step r (t) = Au(t):
Lag compensator
example
ess = 1+KAposn , where
Prop. vs Lead Q
vs Lag
KC z KG i zi
Insights Kposn = GC (0)G(0) = Q
p j pj
Lead-Lag
compensation • Note that for a lead compensator, z/p < 1,
Lead-Lag
Compensator
example • So lead compensation may degrade steady-state error
A prelude performance
EE 3CL4, §6
42 / 101
Tim Davidson Steady-state error
Compensators • Now, consider the case
Q in which G(s) is a type-1
Lead K i (s+zi )
compensation system, G(s) = sGQ (s+p j)
Design via Root
j
Locus
Lead Compensator
• Steady-state error due to a ramp r (t) = At: ess = A/Kv ,
example

Cascade
where the velocity constant is
compensation
and
Q
steady-state KC z KG i zi
errors Kv = lim sGc (s)G(s) = Q
s→0 p j pj
Lag
Compensation
Design via Root
Locus
Lag compensator • Once again, lead compensation may degrade
example

Prop. vs Lead steady-state error performance

vs Lag

Insights
• Is there a way to increase the value of these error
Lead-Lag
compensation constants while leaving the closed loop poles in
Lead-Lag
Compensator
example
essentially the same place as they were in an
A prelude uncompensated system? Perhaps |z| > |p|?
EE 3CL4, §6
44 / 101
Tim Davidson Lag compensation
Compensators

Lead
compensation
Design via Root
Locus Kc (s + z)
Lead Compensator Gc (s) =
example
(s + p)
Cascade
compensation with |z| > |p|. That is, pole closer to origin than zero
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights Let z = 1/τz and p = 1/(αlag τz ). Since z > p, αlag > 1.

Lead-Lag
compensation Define K̃c = Kc z/p = Kc αlag . Then
Lead-Lag
Compensator
example Kc (s + z) K̃c (1 + τz s)
Gc (s) = =
A prelude (s + p) (1 + αlag τz s)
EE 3CL4, §6
45 / 101
Tim Davidson Frequency response
Compensators
K̃C (1 + jωτz )
Lead
compensation
Gc (jω) =
Design via Root
(1 + jωαlag τz )
Locus
Lead Compensator
example Magnitude
Cascade
compensation
• Low frequency gain: K̃C
and
steady-state • Corner freq. in denominator at ωp = p = 1/(αlag τz )
errors

Lag
• Corner freq. in numerator at ωz = z = 1/τz
Compensation
Design via Root
• ωp < ωz
Locus
Lag compensator
example
• High frequency gain: K̃C /αlag = KC
Prop. vs Lead
vs Lag
Phase
Insights • φ(ω) = atan(ωτz ) − atan(αlag ωτz )
Lead-Lag
compensation
• At low frequency: φ(ω) = 0
Lead-Lag
Compensator
example
• At high frequency: φ(ω) = 0
√
A prelude • In between: negative, with max. lag at ω = zp
EE 3CL4, §6
46 / 101
Tim Davidson Bode Diagram, with K̃c = 1
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example
Note integrative characteristic
A prelude
EE 3CL4, §6
47 / 101
Tim Davidson A passive phase lag network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
48 / 101
Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
49 / 101
Tim Davidson Lag compensator design
• Lag compensator: Gc (s) = Kc s+z
Compensators s+p . with |z| > |p|.
Lead
compensation
• Recall position error constant for compensated type-0
Design via Root
Locus
system and velocity error constant for compensated type-1
Lead Compensator
example
system:
Cascade Q Q
compensation KC z KG i zi KC z KG i zi
and Kposn = Q , Kv = Q
steady-state p j pj p j pj
errors

Lag where in the latter case the product in the denominator is

Compensation
Design via Root over the non-zero poles.
Locus
Lag compensator
example
Design Principles
Prop. vs Lead
vs Lag
• We don’t try to reshape the uncompensated root locus.
Insights

Lead-Lag
• We just try to increase the value of the desired error constant
compensation
Lead-Lag
by a factor αlag = z/p without moving the existing
Compensator
example
closed-loop poles (well not much)
A prelude • Reshaping was the goal of lead compensator design
EE 3CL4, §6
50 / 101
Tim Davidson Lag compensator design
Compensators

Lead
compensation Design principles:
Design via Root
Locus • Don’t reshape the root locus
Lead Compensator
example • Adding the open loop pole and zero from the
Cascade
compensation
compensator should only result in a small change to the
and angle criterion for any (important) point on the
steady-state
errors uncompensated root locus
Lag
• Angles from compensator pole and zero to any
Compensation
Design via Root
(important) point on the locus must be similar
Locus • Pole and zero must be close together
Lag compensator
example

Prop. vs Lead • Increase value of error constant:

vs Lag

Insights
• Want to have a large value for αlag = z/p.
• How can that happen if z and p are close together?
Lead-Lag
compensation • Only if z and p are both small, i.e., close to the origin
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
51 / 101
Tim Davidson Lag comp. design via Root
Compensators Locus
Lead
1 Obtain the root locus of uncompensated system
compensation
Design via Root
2 From transient performance specs, locate suitable
Locus
Lead Compensator dominant pole positions on that locus
example

Cascade
3 Obtain the loop gain for these points, Kunc = Kamp KG ;
compensation
and
hence the (closed-loop) steady-state error constant
steady-state
errors
4 Calculate the necessary increase. Hence αlag = z/p
Lag 5 Place pole and zero close to the origin (with respect to
Compensation
Design via Root desired pole positions), with z = αlag p.
Locus
Lag compensator
example
Typically, choose z and p so that their angles to desired
Prop. vs Lead poles differ by less than 1◦ .
vs Lag
6 Set KC = Kamp
Insights

Lead-Lag What if there is nothing suitable at step 2?

compensation
Lead-Lag
Compensator
• Perhaps do lead compensation first,
example
• then lag compensation on lead compensated plant.
A prelude
i.e., design a lead-lag compensator
EE 3CL4, §6
52 / 101
Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state 1
errors Let’s consider, again, the case with G(s) = s(s+2) .
Lag
Compensation
Design a lag compensator to achieve damping coefficient
Design via Root
Locus
ζ ≈ 0.45 and velocity error constant Kv ≥ 20
Lag compensator
example

Prop. vs Lead Note: we will get a different closed loop from our lead
vs Lag
design.
Insights

Lead-Lag
compensation First step, obtain uncompensated root locus, and locate
Lead-Lag
Compensator
example
desired dominant pole locations
A prelude
EE 3CL4, §6
53 / 101
Tim Davidson Uncompensated root locus
In this example, this step is the same as the first step in our
Compensators

Lead
lead design example
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
• So, yes, it is possible to achieve a damping coefficient
Compensator
example ζ ≈ 0.45 using proportional control
A prelude
• What is the gain that puts the closed loop poles there?
EE 3CL4, §6
54 / 101
Tim Davidson Finding the gain for prop. control
Q
Compensators distances from OL poles
Lead
• That gain is K = Kamp KG = Q
compensation
distances from OL zeros
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag • K = d1 d2 = 5.
Compensator
example
• Since KG = 1, Kamp = 5.
A prelude
EE 3CL4, §6
55 / 101
Tim Davidson Evaluate the velocity error
Compensators constant, and choose z/p
Lead
compensation
Design via Root • Velocity error constant of uncompensated loop:
Locus
Lead Compensator
example
Kv ,unc = lims→0 sGc (s)G(s) = Kamp KG /2
Cascade
compensation • Since KG = 1 and Kamp = 5, Kv ,unc = 2.5
and
steady-state
errors • In order to obtain Kv ≥ 20, the factor by which we need
Lag
Compensation
to increase Kv ,unc by at least 20/2.5 = 8
Design via Root
Locus
Lag compensator • That implies that in the design of our lag controller, we
example

Prop. vs Lead
should choose pole and zero such that z/p ≥ 8,
vs Lag
• where z is chosen to be close to the origin with respect
Insights

Lead-Lag
to dominant closed-loop poles, so that the root locus
compensation doesn’t change too much near those dominant
Lead-Lag
Compensator
example
closed-loop poles
A prelude
EE 3CL4, §6
56 / 101
Tim Davidson Positioning zero and pole
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator with z/p ≥ 8
example

A prelude
EE 3CL4, §6
57 / 101
Tim Davidson Zooming in
Compensators
• Try −z = −0.1, along with −p = −1/80.
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag • Angles from new open-loop zero and open-loop pole to
Insights desired closed-loop pole position are pretty close.
Lead-Lag • Therefore, their effects will nearly cancel out in phase
compensation
Lead-Lag
Compensator
criterion at values of s near box
example
• As a result, compensated root locus should pass close by
A prelude
the desired positions
EE 3CL4, §6
58 / 101
Tim Davidson Lag compensated root locus
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
• Yes, indeed, the lag compensated root locus does pass
Compensator
example close by the desired positions
A prelude
EE 3CL4, §6
59 / 101
Tim Davidson Lag compensated root locus,
Compensators zoomed in
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
60 / 101
Tim Davidson Choosing Kc
Compensators
• Choose Kc to be the same as Kamp from the
Lead uncompensated design
compensation
Design via Root
Locus
• That is, Kc = 5
Lead Compensator
example • Plot actual closed loop poles on the locus (asterisks)
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
61 / 101
Tim Davidson Zoomed in
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
62 / 101
Tim Davidson Comparisons to prop. design
Compensators

Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
63 / 101
Tim Davidson Comparisons
Compensators Prop.-contr. Lag contr.
Lead
5(s+0.1)
compensation
Design via Root
Controller, GC (s) 5 (s+1/80)
Locus
Lead Compensator 5 5(s+0.1) 1
example OL TF, GC (s)G(s) s(s+2) (s+1/80) s(s+2)
Cascade
compensation Y (s) 5 5(s+0.1)
and CL TF, R(s) s(s+2)+5 s(s+2)(s+1/80)+5(s+0.1)
steady-state
errors
CL poles −1 ± j2 −0.955 ± j1.979, −0.104
Lag
Compensation
Design via Root
CL zeros ∞, ∞ −0.1, ∞, ∞
Locus
Lag compensator
5 4.999(1+7×10−4 s) −0.004
example
CL TF, again s2 +2s+5 s2 +1.909s+4.827
+ s+0.104
Prop. vs Lead
vs Lag

Insights • Complex conjugate poles still dominate

Lead-Lag
compensation • Closed-loop zero at -0.1 (which is also an open-loop
Lead-Lag
Compensator
example
zero) reduces impact of closed-loop pole at -0.104;
A prelude residue of that pole in partial fraction expansion is small
EE 3CL4, §6
64 / 101
Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
65 / 101
Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
66 / 101
Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator Note longer settling time of lag controlled loop,
example

A prelude
and slight increase in overshoot, due to extra closed-loop
pole-zero pair that do not quite cancel each other out
EE 3CL4, §6
68 / 101
Tim Davidson Prop, Lead, Lag Design
Compensators Comparisons
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation Recall the design example that we have considered for lead and lag
and
steady-state designs:
errors
1
Lag
For G(s) = s(s+2)
and with H(s) = 1, design a compensator to achieve:
Compensation
Design via Root
• damping coefficient ζ ≈ 0.45 and
Locus
Lag compensator • velocity error constant Kv = lims→0 sGc (s)G(s) ≥ 20
example

Prop. vs Lead • swift transient response (small settling time)

vs Lag

Insights We have done

Lead-Lag • Proportional design (blue), which failed to meet specifications
compensation
Lead-Lag
Compensator
• Lead design (green)
example

A prelude
• Lag design (red)
EE 3CL4, §6
69 / 101
Tim Davidson Prop, Lead, Lag Design
Compensators Comparisons
Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
70 / 101
Tim Davidson Bode, open loop, Gc (jω)G(jω)
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag • Recall Kv = lims→0 sGc (s)G(s)
Insights • Low freq’s: curves approx linear with slope -20dB/dec.
Lead-Lag
compensation
• That is 20 log10 (|Gc (jω)G(jω)|) ≈ 20 log10 (A) − 20 log10 (ω)
Lead-Lag
Compensator • That means Gc (jω)G(jω) ≈ jω A
; Gc (s)G(s) ≈ As ; =⇒ Kv = A
example
• Thus, when low freq. slope is -20dB/dec, “higher” curves mean
A prelude
larger Kv
EE 3CL4, §6
71 / 101
Tim Davidson Low freq. analysis
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
• Let’s now do that analytically
example
• For each design, for small s, Gc (s)G(s) ≈ A
Cascade s
compensation
and • G(s) = 1
steady-state s(s+2)
errors

Lag
Compensation
• Prop: Gc (s) = 5. Hence, A = 2.5
Design via Root
Locus
125(s+4.47)
Lag compensator
example
• Lead: Gc (s) = (s+12.5) . Hence, A = 22.3
Prop. vs Lead
vs Lag 5(s+0.1)
• Lag: Gc (s) = (s+1/80) . Hence, A = 20
Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
72 / 101
Tim Davidson Prop, Lead, Lag Design
Compensators Comparisons
Lead
1
compensation For given example: G(s) = s(s+2) , ζ ≈ 0.45
Design via Root
Locus
Lead Compensator Prop.-contr. Lead contr. Lag contr.
example

Cascade 125(s+4.47) 5(s+0.1)

GC (s) 5 (s+12.5) (s+1/80)
compensation
and
steady-state Y (s) 5 131(1+0.013s) 1.71 4.999(1+7×10−4 s) −0.004
R(s) s2 +2s+5 s2 +8.94s+100
− s+5.59 s2 +1.909s+4.827
+ s+0.104
errors

Lag CL poles −1 ± j2 −4.47 ± j8.94, −5.59 −0.955 ± j1.979, −0.104

Compensation
Design via Root
Locus CL zeros ∞, ∞ −4.47, ∞, ∞ −0.1, ∞, ∞
Lag compensator
example
1/Kv 0.4 0.045 0.05
Prop. vs Lead
vs Lag • Lag design retains similar CL poles to prop. design,
Insights
plus a “slow” pole with a small residue
Lead-Lag
compensation • CL poles of lead design quite different
Lead-Lag
Compensator
example • Lead and lag meet Kv specification (1/Kv = ess,unit ramp )
A prelude
EE 3CL4, §6
73 / 101
Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
74 / 101
Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
75 / 101
Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
76 / 101
Tim Davidson Step response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
77 / 101
Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
78 / 101
Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state With H(s) = 1,
errors

Lag Gc (s)G(s) G(s)

Compensation Y (s) = R(s) + Td (s)
Design via Root 1 + Gc (s)G(s) 1 + Gc (s)G(s)
Locus
Lag compensator Gc (s)G(s)
example
− N(s)
Prop. vs Lead
1 + Gc (s)G(s)
vs Lag

Insights
1 G(s)
Lead-Lag E(s) = R(s) − Td (s)
compensation 1 + Gc (s)G(s) 1 + Gc (s)G(s)
Lead-Lag
Compensator Gc (s)G(s)
example
+ N(s)
A prelude 1 + Gc (s)G(s)
EE 3CL4, §6
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Tim Davidson Response to step disturbance
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
80 / 101
Tim Davidson Response to step disturbance,
Compensators detail early
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
81 / 101
Tim Davidson Response to step disturbance,
Compensators detail late
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example
Homework: Show that ess for a step disturbance is 0.2,
A prelude
0.0225 and 0.025 for prop., lead, lag, respectively
EE 3CL4, §6
82 / 101
Tim Davidson Error due to Gaussian sensor
Compensators noise
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
83 / 101
Tim Davidson Bode diagram of
Compensators GC (s)G(s)/(1 + GC (s)G(s))
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag • Prop. and lag designs do a better job at filtering out the higher
compensation
Lead-Lag frequency noise components
Compensator
example
• You could also see this bandwidth diff. in open loop Bode plots
A prelude
• Reduced bandwidth also means slower step and ramp responses
EE 3CL4, §6
85 / 101
Tim Davidson Insights
Compensators • If we would like to improve the transient performance of
Lead
compensation
a closed loop
Design via Root
Locus
• We can try to place the dominant closed-loop poles in
Lead Compensator
example
desired positions
Cascade
• One approach to doing that is lead compensator design
compensation • However, that typically requires the use of an amplifier
and
steady-state in the compensator, and hence requires a power supply
errors
• Broadening of bandwidth improves transient
Lag
Compensation performance but exposes loop to noise
Design via Root
Locus
Lag compensator
example • If we would like to improve the steady-state error
Prop. vs Lead
vs Lag
performance of a closed loop without changing the
Insights
dominant transient features too much
Lead-Lag
• We can consider designing a lag compensator to
compensation provide the required gain
Lead-Lag
Compensator • However, that typically produces a “weak” slow pole that
example

A prelude
slows the decay to steady state
EE 3CL4, §6
87 / 101
Tim Davidson What if we want to do more?
Compensators
• What happens if we want to improve transient performance
Lead
compensation and improve steady-state error?
Design via Root
Locus
Lead Compensator
example • For example, what if we want to design a compensator for
1
Cascade G(s) = s(s+2) that achieves
compensation
and
steady-state 1 Specified maximum overshoot; minimum value for ζ
errors

Lag
2 Specified (2%) settling time; largest (least negative) real
Compensation part of closed loop pole
Design via Root
Locus
Lag compensator
3 Specified steady-state error for ramp input;
example
min. value for Kv , related to DC open loop “gain”
Prop. vs Lead
vs Lag

Insights
• Lead compensation gives (some) ability to address 1 and 2
Lead-Lag • Lag compensation gives (some) ability to address 3
compensation
Lead-Lag
Compensator
example • What should we do?
A prelude
EE 3CL4, §6
88 / 101
Tim Davidson Lead-lag compensation
Compensators

Lead
compensation • Here is one thing that we can do:
Design via Root
Locus
Lead Compensator
example
• Step 1: Design a lead compensator Gc,lead (s) for the
Cascade
process G(s) to change the shape of the root locus and
compensation choose the gain so that the poles are in the desired
and
steady-state position
errors
• Step 2: Design a lag compensator, Gc,lag (s) to leave
Lag
Compensation the dominant closed-loop poles of the
Design via Root
Locus lead-compensated process G̃(s) = Gc,lead (s)G(s) in
Lag compensator
example approximately the position but provide extra
Prop. vs Lead low-frequency gain
vs Lag

Insights
• This is called a lead-lag controller:
Lead-Lag
compensation Gc (s) = Gc,lead-lag (s) = Gc,lag (s)Gc,lead (s)
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
89 / 101
Tim Davidson Lead-Lag Comp. example
Compensators

Lead
compensation
Design via Root
Locus
1
Lead Compensator
example Consider a case with G(s) = s(s+2) and H(s) = 1.
Cascade Design a compensator to achieve:
compensation
and
steady-state
• damping coefficient ζ ≈ 0.45
errors
• dominant poles with real parts ≈ −4.5, so that they
Lag 4
Compensation correspond to a 2% setting time of ≈ 4.5 ∼ 0.9s
Design via Root
Locus
Lag compensator
• velocity error constant Kv = lims→0 sGc (s)G(s) ≥ 40
example

Prop. vs Lead
vs Lag What to do?
Insights • Our second lead compensator (with the green root locus),
Lead-Lag
compensation
Gc,lead (s) = 125(s+4.47)
(s+12.5) , achieves the first two requirements
Lead-Lag
Compensator
example
• However, that design has Kv ≈ 22.3
A prelude • Now design a lag compensator to increase Kv to 40
EE 3CL4, §6
90 / 101
Tim Davidson Lead-Lag Design
Compensators
• Gc,lead (s)G(s) has Kv ≈ 22.3.
Lead • Lag compensator must increase this to around 40.
compensation
Design via Root Therefore, we need zlag /plag ≈ 1.8.
Locus
Lead Compensator
example • Looking at the closed loop poles of lead compensated plant
Cascade (green, see also table on slide 33),
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example
we can try zlag = 0.18, plag = 0.1.
A prelude 125(s+0.18)(s+4.47)
• Therefore Gc,lead-lag (s) = (s+0.1)(s+12.5)
EE 3CL4, §6
91 / 101
Tim Davidson Prop, Lead, Lag, Lead-Lag
Compensators Design Comparisons
Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
92 / 101
Tim Davidson Bode, open loop, Gc (jω)G(jω)
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag • Recall Kv = lims→0 sGc (s)G(s)
Insights
• At low freq. slope is -20dB/dec. Hence Gc (s)G(s) ≈ As .
Lead-Lag Hence, Kv = A.
compensation
Lead-Lag
Compensator
• Since Gc,lead-lag (s) = 125(s+0.18)(s+4.47)
(s+0.1)(s+12.5)
, Alead-lag = 40.23
example
• By comparison with slide 70 (and as seen in plot),
A prelude
Alead-lag > Alead & Alag > Aprop
EE 3CL4, §6
93 / 101
Tim Davidson Lead, Lead-Lag Comparisons
Compensators Prop. and Lag designs are on slide 71
Lead
compensation Lead contr. Lead-Lag contr.
Design via Root
Locus
125(s+4.47) 125(s+0.18)(s+4.47)
Lead Compensator
example
GC (s) (s+12.5) (s+0.1)(s+12.5)
Cascade Y (s) 131(1+0.0130s) 1.71 131(1+0.0132s) 1.73 6.15×10−4
compensation R(s) s2 +8.94s+100
− s+5.59 s2 +8.82s+99.46
− s+5.60
+ s+0.1806
and
steady-state
errors CL poles −4.47 ± j8.94, −5.59 −4.41 ± j8.95, −5.60, −0.1806
Lag CL zeros −4.47, ∞, ∞ −4.47, −0.18, ∞, ∞
Compensation
Design via Root
Locus 1/Kv 0.045 0.0249
Lag compensator
example

Prop. vs Lead • Lead-lag design retains similar CL poles to lead design,

vs Lag

Insights
plus a “slow” pole with very small residue
Lead-Lag
compensation
• Lead-lag will have smaller steady-state error for a ramp
Lead-Lag
Compensator input.
example

A prelude • Anything else? Recall larger low-frequency gain

EE 3CL4, §6
94 / 101
Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
95 / 101
Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
96 / 101
Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
97 / 101
Tim Davidson Response to step disturbance
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator Note reduced steady-state disturbance error of lead-lag
example

A prelude
design. This is due to larger Kv , which comes from larger
low-frequency “gain”
EE 3CL4, §6
98 / 101
Tim Davidson Error due to Gaussian sensor
Compensators noise
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude
EE 3CL4, §6
99 / 101
Tim Davidson Bode diagram of
Compensators GC (s)G(s)/(1 + GC (s)G(s))
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Insights
• Prop. and lag designs do a better job at filtering out the higher
Lead-Lag
compensation frequency noise components
Lead-Lag
Compensator • You could also see this bandwidth diff. in open loop Bode plots
example

A prelude • Reduced bandwidth also means slower step and ramp responses
EE 3CL4, §6
101 / 101
Tim Davidson A prelude to frequency-domain
Compensators design
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade • In our design process there were connections between

compensation
and performance measures and the frequency responses of
steady-state
errors the open loop and the closed loop.
Lag
Compensation
Design via Root
• Perhaps we might be able to build a design technique
Locus
Lag compensator around Bode magnitude and phase diagrams of the
example

Prop. vs Lead
open-loop transfer function, rather than the open-loop
vs Lag poles and zeros
Insights

Lead-Lag
compensation
Lead-Lag
Compensator
example

A prelude