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Principles of Operation
SA22-7201-08
Enterprise Systems Architecture/390 IBM
Principles of Operation
SA22-7201-08
Note:
Before using this information and the product it supports, be sure to read the general information under “Notices” on page xvii.
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Contents v
Control Register 15 . . . . . . . . . . . . 5-68 Instruction-Length Code . . . . . . . . . . . 6-7
Linkage Stack . . . . . . . . . . . . . . . . . 5-68 Zero ILC . . . . . . . . . . . . . . . . . . 6-7
Entry Descriptors . . . . . . . . . . . . . 5-69 ILC on Instruction-Fetching Exceptions . 6-7
Header Entries . . . . . . . . . . . . . . 5-70 Exceptions Associated with the PSW . . . 6-9
Trailer Entries . . . . . . . . . . . . . . . 5-70 Early Exception Recognition . . . . . . . 6-9
State Entries . . . . . . . . . . . . . . . . 5-71 Late Exception Recognition . . . . . . . 6-9
Stacking Process . . . . . . . . . . . . . . . 5-73 External Interruption . . . . . . . . . . . . . . . 6-10
Locating Space for a New Entry . . . . 5-73 Clock Comparator . . . . . . . . . . . . . . 6-11
Forming the New Entry . . . . . . . . . . 5-74 CPU Timer . . . . . . . . . . . . . . . . . . 6-11
Updating the Current Entry . . . . . . . 5-75 Emergency Signal . . . . . . . . . . . . . . 6-11
Updating Control Register 15 . . . . . . 5-75 ETR . . . . . . . . . . . . . . . . . . . . . . 6-12
Recognition of Exceptions during the External Call . . . . . . . . . . . . . . . . . 6-12
Stacking Process . . . . . . . . . . . 5-75 Interrupt Key . . . . . . . . . . . . . . . . . 6-12
Unstacking Process . . . . . . . . . . . . . 5-75 Malfunction Alert . . . . . . . . . . . . . . . 6-12
Locating the Current Entry and Service Signal . . . . . . . . . . . . . . . . 6-12
Processing a Header Entry . . . . . 5-76 TOD-Clock Sync Check . . . . . . . . . . . 6-13
Checking for a State Entry . . . . . . . . 5-77 I/O Interruption . . . . . . . . . . . . . . . . . . 6-13
Restoring Information . . . . . . . . . . . 5-77 Machine-Check Interruption . . . . . . . . . . 6-14
Updating the Preceding Entry . . . . . . 5-77 Program Interruption . . . . . . . . . . . . . . 6-14
Updating Control Register 15 . . . . . . 5-77 Exception-Extension Code . . . . . . . . . 6-15
Recognition of Exceptions during the Data-Exception Code (DXC) . . . . . . . . 6-15
Unstacking Process . . . . . . . . . 5-78 Priority of Program Interruptions for
Sequence of Storage References . . . . . . . 5-78 Data Exceptions . . . . . . . . . . . 6-15
Conceptual Sequence . . . . . . . . . . 5-78 Program-Interruption Conditions . . . . . . 6-16
Overlapped Operation of Instruction Addressing Exception . . . . . . . . . . 6-16
Execution . . . . . . . . . . . . . . . 5-79 AFX-Translation Exception . . . . . . . . 6-19
Divisible Instruction Execution . . . . . . 5-79 ALEN-Translation Exception . . . . . . . 6-19
Interlocks for Virtual-Storage References . 5-79 ALE-Sequence Exception . . . . . . . . 6-19
Interlocks between Instructions . . . . . 5-80 ALET-Specification Exception . . . . . . 6-19
Interlocks within a Single Instruction . . 5-80 ASN-Translation-Specification
Instruction Fetching . . . . . . . . . . . . . 5-82 Exception . . . . . . . . . . . . . . . 6-19
ART-Table and DAT-Table Fetches . . . . 5-83 ASTE-Sequence Exception . . . . . . . 6-20
Storage-Key Accesses . . . . . . . . . . . 5-84 ASTE-Validity Exception . . . . . . . . . 6-20
Storage-Operand References . . . . . . . 5-85 ASX-Translation Exception . . . . . . . 6-21
Storage-Operand Fetch References . . 5-85 Crypto-Operation Exception . . . . . . . 6-21
Storage-Operand Store References . . 5-85 Data Exception . . . . . . . . . . . . . . 6-21
Storage-Operand Update References . 5-86 Decimal-Divide Exception . . . . . . . . 6-22
Storage-Operand Consistency . . . . . . . 5-87 Decimal-Overflow Exception . . . . . . . 6-22
Single-Access References . . . . . . . . 5-87 Execute Exception . . . . . . . . . . . . 6-22
Multiple-Access References . . . . . . . 5-87 EX-Translation Exception . . . . . . . . 6-22
Block-Concurrent References . . . . . . 5-88 Extended-Authority Exception . . . . . . 6-22
Consistency Specification . . . . . . . . 5-88 Fixed-Point-Divide Exception . . . . . . 6-23
Relation between Operand Accesses . . . 5-90 Fixed-Point-Overflow Exception . . . . . 6-23
Other Storage References . . . . . . . . . 5-90 HFP-Divide Exception . . . . . . . . . . 6-23
| Relation between Storage-Key Accesses . 5-90 HFP-Exponent-Overflow Exception . . . 6-23
Serialization . . . . . . . . . . . . . . . . . . . 5-91 HFP-Exponent-Underflow Exception . . 6-24
CPU Serialization . . . . . . . . . . . . . . 5-91 HFP-Significance Exception . . . . . . . 6-24
Channel-Program Serialization . . . . . . . 5-92 HFP-Square-Root Exception . . . . . . 6-24
LX-Translation Exception . . . . . . . . 6-24
Chapter 6. Interruptions . . . . . . . . . . . 6-1 Monitor Event . . . . . . . . . . . . . . . 6-24
Interruption Action . . . . . . . . . . . . . . . . 6-2 Operand Exception . . . . . . . . . . . . 6-25
Interruption Code . . . . . . . . . . . . . . . 6-5 Operation Exception . . . . . . . . . . . 6-25
Enabling and Disabling . . . . . . . . . . . 6-6 Page-Translation Exception . . . . . . . 6-26
Handling of Floating Interruption Conditions 6-6 PC-Translation-Specification Exception 6-27
Contents vii
LOAD HALFWORD IMMEDIATE . . . . . 7-80 TEST AND SET . . . . . . . . . . . . . . 7-129
LOAD MULTIPLE . . . . . . . . . . . . . . 7-80 TEST UNDER MASK . . . . . . . . . . . 7-130
LOAD NEGATIVE . . . . . . . . . . . . . . 7-80 TEST UNDER MASK HIGH . . . . . . . 7-130
LOAD POSITIVE . . . . . . . . . . . . . . . 7-81 TEST UNDER MASK LOW . . . . . . . . 7-130
LOAD REVERSED . . . . . . . . . . . . . . 7-81 TRANSLATE . . . . . . . . . . . . . . . . 7-131
MONITOR CALL . . . . . . . . . . . . . . . 7-82 TRANSLATE AND TEST . . . . . . . . . 7-132
MOVE . . . . . . . . . . . . . . . . . . . . . 7-83 TRANSLATE EXTENDED . . . . . . . . 7-132
MOVE INVERSE . . . . . . . . . . . . . . . 7-83 TRANSLATE ONE TO ONE . . . . . . . 7-134
MOVE LONG . . . . . . . . . . . . . . . . . 7-83 TRANSLATE ONE TO TWO . . . . . . . 7-135
MOVE LONG EXTENDED . . . . . . . . . 7-87 TRANSLATE TWO TO ONE . . . . . . . 7-135
MOVE LONG UNICODE . . . . . . . . . . 7-90 TRANSLATE TWO TO TWO . . . . . . . 7-135
MOVE NUMERICS . . . . . . . . . . . . . . 7-93 UNPACK . . . . . . . . . . . . . . . . . . 7-139
MOVE PAGE (Facility 1) . . . . . . . . . . 7-93 UNPACK ASCII . . . . . . . . . . . . . . 7-139
MOVE STRING . . . . . . . . . . . . . . . . 7-95 UNPACK UNICODE . . . . . . . . . . . . 7-140
MOVE WITH OFFSET . . . . . . . . . . . . 7-97 UPDATE TREE . . . . . . . . . . . . . . . 7-141
MOVE ZONES . . . . . . . . . . . . . . . . 7-97
MULTIPLY . . . . . . . . . . . . . . . . . . 7-98 Chapter 8. Decimal Instructions . . . . . . 8-1
MULTIPLY HALFWORD . . . . . . . . . . 7-98 Decimal-Number Formats . . . . . . . . . . . 8-1
MULTIPLY HALFWORD IMMEDIATE . . . 7-98 Zoned Format . . . . . . . . . . . . . . . . . 8-1
MULTIPLY LOGICAL . . . . . . . . . . . . 7-99 Packed Format . . . . . . . . . . . . . . . . 8-1
MULTIPLY SINGLE . . . . . . . . . . . . . 7-99 Decimal Codes . . . . . . . . . . . . . . . . 8-2
OR . . . . . . . . . . . . . . . . . . . . . . 7-100 Decimal Operations . . . . . . . . . . . . . . . 8-2
PACK . . . . . . . . . . . . . . . . . . . . 7-100 Decimal-Arithmetic Instructions . . . . . . . 8-2
PACK ASCII . . . . . . . . . . . . . . . . 7-101 Editing Instructions . . . . . . . . . . . . . . 8-3
PACK UNICODE . . . . . . . . . . . . . . 7-102 Execution of Decimal Instructions . . . . . 8-3
PERFORM LOCKED OPERATION . . . 7-103 Other Instructions for Decimal Operands . 8-3
ROTATE LEFT SINGLE LOGICAL . . . 7-116 Decimal-Operand Data Exception . . . . . 8-4
SEARCH STRING . . . . . . . . . . . . . 7-116 Instructions . . . . . . . . . . . . . . . . . . . . 8-4
SET ACCESS . . . . . . . . . . . . . . . 7-117 ADD DECIMAL . . . . . . . . . . . . . . . . 8-6
SET ADDRESSING MODE . . . . . . . . 7-117 COMPARE DECIMAL . . . . . . . . . . . . 8-6
SET PROGRAM MASK . . . . . . . . . . 7-118 DIVIDE DECIMAL . . . . . . . . . . . . . . 8-7
SHIFT LEFT DOUBLE . . . . . . . . . . . 7-118 EDIT . . . . . . . . . . . . . . . . . . . . . . 8-7
SHIFT LEFT DOUBLE LOGICAL . . . . 7-119 EDIT AND MARK . . . . . . . . . . . . . . 8-12
SHIFT LEFT SINGLE . . . . . . . . . . . 7-119 MULTIPLY DECIMAL . . . . . . . . . . . . 8-12
SHIFT LEFT SINGLE LOGICAL . . . . . 7-120 SHIFT AND ROUND DECIMAL . . . . . . 8-13
SHIFT RIGHT DOUBLE . . . . . . . . . . 7-120 SUBTRACT DECIMAL . . . . . . . . . . . 8-14
SHIFT RIGHT DOUBLE LOGICAL . . . 7-121 TEST DECIMAL . . . . . . . . . . . . . . . 8-14
SHIFT RIGHT SINGLE . . . . . . . . . . 7-121 ZERO AND ADD . . . . . . . . . . . . . . . 8-14
SHIFT RIGHT SINGLE LOGICAL . . . . 7-121
STORE . . . . . . . . . . . . . . . . . . . 7-122 Chapter 9. Floating-Point Overview and
STORE ACCESS MULTIPLE . . . . . . . 7-122 Support Instructions . . . . . . . . . . . . 9-1
STORE CHARACTER . . . . . . . . . . . 7-122 Registers And Controls . . . . . . . . . . . . . 9-2
STORE CHARACTERS UNDER MASK .7-122 Floating-Point Registers . . . . . . . . . . . 9-2
STORE CLOCK . . . . . . . . . . . . . . 7-123 Additional Floating-Point (AFP)
STORE CLOCK EXTENDED . . . . . . . 7-124 Registers . . . . . . . . . . . . . . . . 9-2
STORE HALFWORD . . . . . . . . . . . 7-126 Valid Floating-Point-Register
STORE MULTIPLE . . . . . . . . . . . . 7-126 Designations . . . . . . . . . . . . . . 9-2
STORE REVERSED . . . . . . . . . . . . 7-126 Floating-Point-Control (FPC) Register . . . 9-2
SUBTRACT . . . . . . . . . . . . . . . . . 7-127 AFP-Register-Control Bit . . . . . . . . . . 9-3
SUBTRACT HALFWORD . . . . . . . . . 7-127 Explicit Rounding Methods . . . . . . . . . 9-3
SUBTRACT LOGICAL . . . . . . . . . . . 7-127 Summary of Rounding Action . . . . . . 9-3
SUBTRACT LOGICAL WITH BORROW .7-128 Comparison of BFP and HFP Number
SUPERVISOR CALL . . . . . . . . . . . 7-129 Representations . . . . . . . . . . . . . . . . 9-4
TEST ADDRESSING MODE . . . . . . . 7-129 BFP and HFP Number Ranges . . . . . . 9-4
Contents ix
System Recovery . . . . . . . . . . . . 11-17 Channel-Report-Pending Subclass
Timing-Facility Damage . . . . . . . . 11-17 Mask . . . . . . . . . . . . . . . . . 11-26
External Damage . . . . . . . . . . . . 11-18 Recovery Subclass Mask . . . . . . . 11-26
Vector-Facility Failure . . . . . . . . . 11-18 Degradation Subclass Mask . . . . . . 11-26
Degradation . . . . . . . . . . . . . . . 11-18 External-Damage Subclass Mask . . . 11-26
Warning . . . . . . . . . . . . . . . . . 11-18 Warning Subclass Mask . . . . . . . . 11-26
Channel Report Pending . . . . . . . . 11-18 Machine-Check Logout . . . . . . . . . . . . 11-27
Service-Processor Damage . . . . . . 11-19 Summary of Machine-Check Masking . . . 11-27
Channel-Subsystem Damage . . . . . 11-19
Subclass Modifiers . . . . . . . . . . . . . 11-19 Chapter 12. Operator Facilities . . . . . . . 12-1
Vector-Facility Source . . . . . . . . . 11-19 Manual Operation . . . . . . . . . . . . . . . . 12-1
Backed Up . . . . . . . . . . . . . . . . 11-19 Basic Operator Facilities . . . . . . . . . . . . 12-1
Delayed Access Exception . . . . . . . 11-19 Address-Compare Controls . . . . . . . . . 12-1
Ancillary Report . . . . . . . . . . . . . 11-19 Alter-and-Display Controls . . . . . . . . . 12-2
Synchronous Architectural-Mode Indicator . . . . . . . . 12-2
Machine-Check-Interruption Conditions 11-20 Architectural-Mode-Selection Controls . . . 12-2
Processing Backup . . . . . . . . . . . 11-20 Check-Stop Indicator . . . . . . . . . . . . 12-2
Processing Damage . . . . . . . . . . 11-20 IML Controls . . . . . . . . . . . . . . . . . 12-3
Storage Errors . . . . . . . . . . . . . . . 11-20 Interrupt Key . . . . . . . . . . . . . . . . . 12-3
Storage Error Uncorrected . . . . . . . 11-21 Load Indicator . . . . . . . . . . . . . . . . 12-3
Storage Error Corrected . . . . . . . . 11-21 Load-Clear Key . . . . . . . . . . . . . . . . 12-3
Storage-Key Error Uncorrected . . . . 11-21 Load-Normal Key . . . . . . . . . . . . . . . 12-3
Storage Degradation . . . . . . . . . . 11-21 Load-Unit-Address Controls . . . . . . . . . 12-3
Indirect Storage Error . . . . . . . . . . 11-21 Manual Indicator . . . . . . . . . . . . . . . 12-3
Machine-Check Interruption-Code Power Controls . . . . . . . . . . . . . . . . 12-3
Validity Bits . . . . . . . . . . . . . . . 11-22 Rate Control . . . . . . . . . . . . . . . . . 12-4
PSW-MWP Validity . . . . . . . . . . . 11-22 Restart Key . . . . . . . . . . . . . . . . . . 12-4
PSW Mask and Key Validity . . . . . . 11-22 Start Key . . . . . . . . . . . . . . . . . . . 12-4
PSW Program-Mask and Stop Key . . . . . . . . . . . . . . . . . . . 12-4
Condition-Code Validity . . . . . . 11-22 Store-Status Key . . . . . . . . . . . . . . . 12-4
PSW-Instruction-Address Validity . . . 11-22 System-Reset-Clear Key . . . . . . . . . . 12-5
Failing-Storage-Address Validity . . . 11-22 System-Reset-Normal Key . . . . . . . . . 12-5
External-Damage-Code Validity . . . . 11-22 Test Indicator . . . . . . . . . . . . . . . . . 12-5
Floating-Point-Register Validity . . . . 11-23 TOD-Clock Control . . . . . . . . . . . . . . 12-5
General-Register Validity . . . . . . . . 11-23 Wait Indicator . . . . . . . . . . . . . . . . . 12-5
Control-Register Validity . . . . . . . . 11-23 Multiprocessing Configurations . . . . . . . . 12-6
Storage Logical Validity . . . . . . . . 11-23
Access-Register Validity . . . . . . . . 11-23 Chapter 13. I/O Overview . . . . . . . . . . 13-1
Extended-Floating-Point-Register Input/Output (I/O) . . . . . . . . . . . . . . . . 13-1
Validity . . . . . . . . . . . . . . . . 11-23 The Channel Subsystem . . . . . . . . . . . . 13-1
CPU-Timer Validity . . . . . . . . . . . 11-23 Subchannels . . . . . . . . . . . . . . . . . 13-2
Clock-Comparator Validity . . . . . . . 11-23 Attachment of Input/Output Devices . . . . . 13-2
Machine-Check Extended Interruption Channel Paths . . . . . . . . . . . . . . . . 13-2
Information . . . . . . . . . . . . . . . . . 11-24 Control Units . . . . . . . . . . . . . . . . . 13-4
Register Save Areas . . . . . . . . . . . . 11-24 I/O Devices . . . . . . . . . . . . . . . . . . 13-4
Machine-Check Extended Save Area . . 11-24 I/O Addressing . . . . . . . . . . . . . . . . . . 13-5
External-Damage Code . . . . . . . . . . 11-24 Channel-Path Identifier . . . . . . . . . . . 13-5
Failing-Storage Address . . . . . . . . . . 11-25 Subchannel Number . . . . . . . . . . . . . 13-5
Handling of Machine-Check Conditions . . 11-25 Device Number . . . . . . . . . . . . . . . . 13-5
Floating Interruption Conditions . . . . . 11-25 Device Identifier . . . . . . . . . . . . . . . 13-5
Floating Machine-Check-Interruption Execution of I/O Operations . . . . . . . . . . 13-6
Conditions . . . . . . . . . . . . . . 11-26 Start-Function Initiation . . . . . . . . . . . 13-6
Floating I/O Interruptions . . . . . . . . 11-26 Path Management . . . . . . . . . . . . . . 13-6
Machine-Check Masking . . . . . . . . . . . 11-26 Channel-Program Execution . . . . . . . . 13-7
Contents xi
Program-Controlled Interruption . . . . 16-23 Channel-Path Reset . . . . . . . . . . 17-13
Incorrect Length . . . . . . . . . . . . . 16-23 I/O-System Reset . . . . . . . . . . . . 17-13
Program Check . . . . . . . . . . . . . 16-24 Externally Initiated Functions . . . . . . . . 17-17
Protection Check . . . . . . . . . . . . 16-26 Initial Program Loading . . . . . . . . . . 17-17
Channel-Data Check . . . . . . . . . . 16-26 Reconfiguration of the I/O System . . . . 17-20
Channel-Control Check . . . . . . . . 16-27 Status Verification . . . . . . . . . . . . . . . 17-20
Interface-Control Check . . . . . . . . 16-28 Address-Limit Checking . . . . . . . . . . . 17-20
Chaining Check . . . . . . . . . . . . . 16-29 Configuration Alert . . . . . . . . . . . . . . 17-21
Count Field . . . . . . . . . . . . . . . . . 16-29 Incorrect-Length-Indication Suppression . . 17-21
Extended-Status Word . . . . . . . . . . . . 16-32 Concurrent Sense . . . . . . . . . . . . . . . 17-21
Extended-Status Format 0 . . . . . . . . 16-32 Channel-Subsystem Recovery . . . . . . . . 17-21
Subchannel Logout . . . . . . . . . . . 16-32 Channel Report . . . . . . . . . . . . . . . 17-22
Extended-Report Word . . . . . . . . . 16-36 Channel-Report Word . . . . . . . . . . . 17-23
Failing-Storage Address . . . . . . . . 16-37 Channel-Subsystem-I/O-Priority Facility . . 17-25
Secondary-CCW Address . . . . . . . 16-38 Number of
Extended-Status Format 1 . . . . . . . . 16-38 Channel-Subsystem-Priority Levels 17-26
Extended-Status Format 2 . . . . . . . . 16-38
Extended-Status Format 3 . . . . . . . . 16-39 Chapter 18. Hexadecimal-Floating-Point
Extended-Control Word . . . . . . . . . . . . 16-40 Instructions . . . . . . . . . . . . . . . . . 18-1
| Extended-Measurement Word . . . . . . . . 16-40 HFP Arithmetic . . . . . . . . . . . . . . . . . . 18-1
HFP Number Representation . . . . . . . . 18-1
Chapter 17. I/O Support Functions . . . . 17-1 Normalization . . . . . . . . . . . . . . . . . 18-3
Channel-Subsystem Monitoring . . . . . . . . 17-1 HFP Data Format . . . . . . . . . . . . . . 18-3
Channel-Subsystem Timing . . . . . . . . . 17-2 Instructions . . . . . . . . . . . . . . . . . . . . 18-4
Channel-Subsystem Timer . . . . . . . . 17-2 ADD NORMALIZED . . . . . . . . . . . . . 18-8
Measurement-Block Update . . . . . . . . 17-3 ADD UNNORMALIZED . . . . . . . . . . 18-10
Measurement Block . . . . . . . . . . . . 17-3 COMPARE . . . . . . . . . . . . . . . . . 18-10
| Measurement-Block Format . . . . . . . 17-7 CONVERT FROM FIXED . . . . . . . . . 18-11
Measurement-Block Origin . . . . . . . . 17-7 CONVERT TO FIXED . . . . . . . . . . . 18-11
| Measurement-Block Address . . . . . . 17-8 DIVIDE . . . . . . . . . . . . . . . . . . . 18-12
Measurement-Block Key . . . . . . . . . 17-8 HALVE . . . . . . . . . . . . . . . . . . . . 18-13
Measurement-Block Index . . . . . . . . 17-8 LOAD AND TEST . . . . . . . . . . . . . 18-14
Measurement-Block-Update Mode . . . 17-8 LOAD COMPLEMENT . . . . . . . . . . . 18-15
| Measurement-Block-Format Control . . 17-9 LOAD FP INTEGER . . . . . . . . . . . . 18-15
Measurement-Block-Update Enable . . 17-9 LOAD LENGTHENED . . . . . . . . . . . 18-16
Control-Unit-Queuing Measurement . . 17-9 LOAD NEGATIVE . . . . . . . . . . . . . 18-16
Control-Unit-Defer Time . . . . . . . . . 17-9 LOAD POSITIVE . . . . . . . . . . . . . . 18-17
Device-Active-Only Measurement . . . . 17-9 LOAD ROUNDED . . . . . . . . . . . . . 18-18
| Initial-Command-Response MULTIPLY . . . . . . . . . . . . . . . . . 18-18
| Measurement . . . . . . . . . . . . 17-10 | MULTIPLY AND ADD . . . . . . . . . . . 18-20
Time-Interval-Measurement Accuracy .17-10 | MULTIPLY AND SUBTRACT . . . . . . . 18-20
Device-Connect-Time Measurement . . . 17-10 SQUARE ROOT . . . . . . . . . . . . . . 18-21
Device-Connect-Time-Measurement SUBTRACT NORMALIZED . . . . . . . . 18-23
Mode . . . . . . . . . . . . . . . . . 17-10 SUBTRACT UNNORMALIZED . . . . . . 18-23
Device-Connect-Time-Measurement
Enable . . . . . . . . . . . . . . . . 17-11 Chapter 19. Binary-Floating-Point
| Extended Measurement Word . . . . . . 17-11 Instructions . . . . . . . . . . . . . . . . . 19-1
| Extended-Measurement-Word Enable 17-11 Binary-Floating-Point Facility . . . . . . . . . . 19-1
Signals and Resets . . . . . . . . . . . . . . 17-12 Floating-Point-Control (FPC) Register . . . 19-2
Signals . . . . . . . . . . . . . . . . . . . . 17-12 IEEE Masks and Flags . . . . . . . . . . 19-3
Halt Signal . . . . . . . . . . . . . . . . 17-12 FPC DXC Byte . . . . . . . . . . . . . . 19-3
Clear Signal . . . . . . . . . . . . . . . 17-12 Operations on the FPC Register . . . . 19-3
Reset Signal . . . . . . . . . . . . . . . 17-13 BFP Arithmetic . . . . . . . . . . . . . . . . . . 19-4
Resets . . . . . . . . . . . . . . . . . . . . 17-13 BFP Data Formats . . . . . . . . . . . . . . 19-4
Contents xiii
INSERT CHARACTERS UNDER MASK MULTIPLY (MD, MDR, MDE, MDER,
(ICM) . . . . . . . . . . . . . . . . . . . A-21 MXD, MXDR, MXR) . . . . . . . . . . . A-41
LOAD (L, LR) . . . . . . . . . . . . . . . . A-22 Hexadecimal-Floating-Point-Number
LOAD ADDRESS (LA) . . . . . . . . . . . A-22 Conversion . . . . . . . . . . . . . . . . A-42
LOAD HALFWORD (LH) . . . . . . . . . A-23 Fixed Point to Hexadecimal Floating
MOVE (MVC, MVI) . . . . . . . . . . . . . A-23 Point . . . . . . . . . . . . . . . . . . A-42
MVC Example . . . . . . . . . . . . . . A-23 Hexadecimal Floating Point to Fixed
MVI Example . . . . . . . . . . . . . . A-24 Point . . . . . . . . . . . . . . . . . . A-42
MOVE INVERSE (MVCIN) . . . . . . . . A-24 Multiprogramming and Multiprocessing
MOVE LONG (MVCL) . . . . . . . . . . . A-25 Examples . . . . . . . . . . . . . . . . . . A-43
MOVE NUMERICS (MVN) . . . . . . . . A-25 Example of a Program Failure Using OR
MOVE STRING (MVST) . . . . . . . . . . A-26 Immediate . . . . . . . . . . . . . . . . A-43
MOVE WITH OFFSET (MVO) . . . . . . A-26 Conditional Swapping Instructions (CS,
MOVE ZONES (MVZ) . . . . . . . . . . . A-27 CDS) . . . . . . . . . . . . . . . . . . . A-44
MULTIPLY (M, MR) . . . . . . . . . . . . A-27 Setting a Single Bit . . . . . . . . . . . A-44
MULTIPLY HALFWORD (MH) . . . . . . A-27 Updating Counters . . . . . . . . . . . A-45
OR (O, OC, OI, OR) . . . . . . . . . . . . A-28 Bypassing Post and Wait . . . . . . . . . A-45
OI Example . . . . . . . . . . . . . . . A-28 Bypass Post Routine . . . . . . . . . . A-45
PACK (PACK) . . . . . . . . . . . . . . . A-28 Bypass Wait Routine . . . . . . . . . . A-46
SEARCH STRING (SRST) . . . . . . . . A-29 Lock/Unlock . . . . . . . . . . . . . . . . . A-46
SRST Example 1 . . . . . . . . . . . . A-29 Lock/Unlock with LIFO Queuing for
SRST Example 2 . . . . . . . . . . . . A-29 Contentions . . . . . . . . . . . . . . A-46
SHIFT LEFT DOUBLE (SLDA) . . . . . . A-29 Lock/Unlock with FIFO Queuing for
SHIFT LEFT SINGLE (SLA) . . . . . . . A-30 Contentions . . . . . . . . . . . . . . A-47
STORE CHARACTERS UNDER MASK Free-Pool Manipulation . . . . . . . . . . A-48
(STCM) . . . . . . . . . . . . . . . . . . A-30 PERFORM LOCKED OPERATION (PLO) A-50
STORE MULTIPLE (STM) . . . . . . . . A-30 Sorting Instructions . . . . . . . . . . . . . . A-51
TEST UNDER MASK (TM) . . . . . . . . A-31 Tree Format . . . . . . . . . . . . . . . . . A-51
TRANSLATE (TR) . . . . . . . . . . . . . A-31 Example of Use of Sort Instructions . . . A-53
TRANSLATE AND TEST (TRT) . . . . . A-32
UNPACK (UNPK) . . . . . . . . . . . . . A-33 Appendix B. Lists of Instructions . . . . . B-1
UPDATE TREE (UPT) . . . . . . . . . . . A-34
Decimal Instructions . . . . . . . . . . . . . . A-34 Appendix C. Condition-Code Settings . . C-1
ADD DECIMAL (AP) . . . . . . . . . . . . A-34
COMPARE DECIMAL (CP) . . . . . . . . A-34 Appendix D. Comparison between
DIVIDE DECIMAL (DP) . . . . . . . . . . A-34 ESA/370 and ESA/390 . . . . . . . . . . . D-1
EDIT (ED) . . . . . . . . . . . . . . . . . . A-35 New Facilities in ESA/390 . . . . . . . . . . . D-1
EDIT AND MARK (EDMK) . . . . . . . . A-36 Access-List-Controlled Protection . . . . . D-1
MULTIPLY DECIMAL (MP) . . . . . . . . A-36 Additional Floating-Point . . . . . . . . . . D-1
SHIFT AND ROUND DECIMAL (SRP) . A-37 Additional Input/Output . . . . . . . . . . . D-2
Decimal Left Shift . . . . . . . . . . . . A-37 Branch and Set Authority . . . . . . . . . . D-2
Decimal Right Shift . . . . . . . . . . . A-37 Called-Space Identification . . . . . . . . . D-2
Decimal Right Shift and Round . . . . A-38 Checksum . . . . . . . . . . . . . . . . . . . D-2
Multiplying by a Variable Power of 10 . A-38 Compare and Move Extended . . . . . . . D-2
ZERO AND ADD (ZAP) . . . . . . . . . . A-38 Concurrent Sense . . . . . . . . . . . . . . D-2
Hexadecimal-Floating-Point Instructions . . A-39 Extended TOD Clock . . . . . . . . . . . . D-2
ADD NORMALIZED (AD, ADR, AE, AER, Extended Translation 1 . . . . . . . . . . . D-3
AXR) . . . . . . . . . . . . . . . . . . . . A-39 Extended Translation 2 . . . . . . . . . . . D-3
ADD UNNORMALIZED (AU, AUR, AW, Immediate and Relative Instruction . . . . D-3
AWR) . . . . . . . . . . . . . . . . . . . A-39 Move-Page Facility 2 . . . . . . . . . . . . D-3
COMPARE (CD, CDR, CE, CER) . . . . A-40 PER 2 . . . . . . . . . . . . . . . . . . . . . D-4
DIVIDE (DD, DDR, DE, DER) . . . . . . A-40 Perform Locked Operation . . . . . . . . . D-4
HALVE (HDR, HER) . . . . . . . . . . . . A-41 Program Call Fast . . . . . . . . . . . . . . D-4
Resume Program . . . . . . . . . . . . . . D-4
Contents xv
xvi ESA/390 Principles of Operation
Notices
References in this publication to IBM* products,
programs or services do not imply that IBM Trademarks
intends to make these available in all countries in
The following terms, denoted by an asterisk (*) at
which IBM operates. Any reference to an IBM
the first or most prominent occurrence in this pub-
product, program, or service is not intended to
lication, are trademarks of the International Busi-
state or imply that only IBM's product, program, or
ness Machines Corporation in the United States or
service may be used. Any functionally equivalent
other countries:
product, program, or service that does not infringe
any of IBM's intellectual property rights may be AIX/ESA
used instead of the IBM product, program, or BookMaster
service. Evaluation and verification of operation in CICS
conjunction with other products, except those DB2
expressly designated by IBM, is the user's respon- Enterprise Systems Architecture/370
sibility. Enterprise Systems Architecture/390
Enterprise Systems Connection Architecture
IBM may have patents or pending patent applica- ESA/370
tions covering subject matter in this document. ESA/390
The furnishing of this document does not give you ESCON
any license to these patents. You can send FICON
license inquiries, in writing, to the IBM Director of IBM
Licensing, IBM Corporation, 500 Columbus IBMLink
Avenue, Thornwood, NY, 10594 USA. MVS/ESA
OS/390
Processor Resource/Systems Manager
PR/SM
Sysplex Timer
System/370
VM/ESA
z/Architecture
z/OS
Enterprise Systems Architecture/390, ESA/390, System/370, Enterprise Systems Architecture/370, ESA/370, and z/Architecture
are trademarks of the International Business Machines Corporation.
Enterprise Systems Connection Architecture and ESCON are trademarks of the International Business Machines Corporation.
| ANSI is a registered trademark of the American National Standards Institute.
Preface xxi
ESA/390 are described in the publication IBM | due to activation of the load normal key
Enterprise Systems Architecture/390 Common | when the CPU is in the z/Architecture
I/O-Device Commands and Self Description, | architectural mode, are changed to save
SA22-7204. | the current z/Architecture PSW when
| switching to the ESA/390 architectural
Vector operations are described in the publication | mode. Also, code 2 of the order is added,
IBM Enterprise Systems Architecture/390 Vector | and this restores, for CPUs other than the
Operations, SA22-7207. | one executing SIGNAL PROCESSOR, the
| saved PSW when switching to the
The compression facility is described in the publi- | z/Architecture architectural mode, provided
cation IBM Enterprise Systems Architecture/390 | that the saved PSW has not been set to
Data Compression, SA22-7208. | all zeros by certain resets.
Preface xxiii
– The store-status and machine-check - ROTATE LEFT SINGLE LOGICAL
architectural-mode identification at real - SET ADDRESSING MODE
and absolute locations 163 is added. - STORE REVERSED
- SUBTRACT LOGICAL WITH
– The I/O-interruption-identification word at
BORROW
real locations 192-195 is described.
- TEST ADDRESSING MODE
In Chapter 4, “Control”:
– The following instructions of the extended-
– On a model on which z/Architecture is translation facility 2 are added:
installed, recognition of a storage-
- COMPARE LOGICAL LONG
alteration PER event causes no more than
UNICODE
4K bytes to be stored beginning with the
- MOVE LONG UNICODE
byte that caused the event, and this may
- PACK ASCII
result in partial completion of an interrup-
- PACK UNICODE
tible instruction.
- TRANSLATE ONE TO ONE
– BRANCH RELATIVE AND SAVE LONG - TRANSLATE ONE TO TWO
and BRANCH RELATIVE ON CONDITION - TRANSLATE TWO TO ONE
LONG are added to those instructions that - TRANSLATE TWO TO TWO
cause a successful-branching PER event. - UNPACK ASCII
– Storing of the architectural-mode identifi- - UNPACK UNICODE
cation during the store-status operation is – The definitions of PACK ASCII, PACK
described. UNICODE, UNPACK ASCII, and UNPACK
– The set-architecture order of the SIGNAL UNICODE are clarified as compared to
PROCESSOR instruction is added. This their definitions in z/Architecture Principles
can be used to set the architectural mode of Operation, SA22-7832-00.
of the configuration to z/Architecture. – It is clarified that the following instructions
In Chapter 5, “Program Execution”: perform multiple-access references to their
storage operands:
– The RSE, RSL, and RIL instruction
formats are added, and an M field is - CHECKSUM
described as an alternative in the RS - COMPARE AND FORM CODEWORD
format. - CONVERT UNICODE TO UTF-8
- CONVERT UTF-8 TO UNICODE
– The description of the ART-lookaside
buffer (ALB) is improved. – It is clarified that the following instructions
do not necessarily process their storage
In Chapter 6, “Interruptions,” the crypto- operands left to right as observed by other
operation exception is added. CPUs: MOVE LONG, MOVE LONG
In Chapter 7, “General Instructions”: EXTENDED, and MOVE LONG UNICODE
(which is new in the current edition of this
– The following new instructions that have publication but appears in SA22-7832-00
been placed in both z/Architecture and without this clarification). Special padding
ESA/390 are added: characters of MOVE LONG and MOVE
- ADD LOGICAL WITH CARRY LONG EXTENDED specify whether left-
- BRANCH RELATIVE AND SAVE to-right processing should be performed,
LONG as observed by other CPUs, and whether
- BRANCH RELATIVE ON CONDITION the data being moved should or should
LONG not be placed in the cache for availability
- DIVIDE LOGICAL for subsequent processing.
- EXTRACT PSW – The MOVE INVERSE instruction is
- LOAD ADDRESS RELATIVE LONG described as being basic in ESA/390, as
- LOAD REVERSED opposed to being provided by a move-
- MULTIPLY LOGICAL inverse facility.
Preface xxv
– The TOD-clock-sync-check external inter- – The AFP-register control and extended-
ruption is affected by the save-area control are added in the control
extended-TOD-clock facility. registers.
In Chapter 7, “General Instructions,” the – RESUME PROGRAM and TRAP cause
CONVERT UNICODE TO UTF-8, CONVERT branch trace entries to be made.
UTF-8 TO UNICODE, STORE CLOCK
– RESUME PROGRAM and TRAP cause
EXTENDED, and TRANSLATE EXTENDED
successful-branching PER events to occur
instructions are added.
and a valid ATMID (addressing-
In Chapter 10, “Control Instructions,” the SET and-translation-mode identification) to be
CLOCK PROGRAMMABLE FIELD and stored.
STORE SYSTEM INFORMATION instructions
– The use of an extended save area for
are added.
saving floating-point registers 0-15 and the
floating-point-control register by the store-
The above changes may affect other chapters
status operation is added.
besides the ones listed.
– The store-extended-status-at-address
SIGNAL PROCESSOR order is added.
Summary of Changes in Sixth In Chapter 5, “Program Execution”:
Edition
– The RRF, RXE, and RXF instruction
The sixth edition of this publication differs from the formats are added.
previous edition principally by containing the defi-
nitions of the basic floating-point, floating- – A trap-control-block address and
point-support, and hexadecimal-floating-point TRAP-enabled bit are added to the
(HFP) extension facilities and the binary- dispatchable-unit control table.
floating-point (BFP), program-call-fast, resume- In Chapter 6, “Interruptions”:
program, and trap facilities. The sixth edition con-
– The exception names “exponent overflow,”
tains minor clarifications and corrections and also
“exponent underflow,” “significance,”
the following significant changes relative to the
“floating-point divide,” and “square root”
previous edition:
are changed to “HFP exponent overflow,”
In Chapter 2, “Introduction,” 12 floating-point “HFP exponent underflow,” “HFP signif-
registers and the floating-point-control register icance,” “HFP divide,” and “HFP square
are added. root,” respectively.
In Chapter 3, “Storage”: – The reasons for recognizing a data excep-
– In the section “Prefixing,” the term “prefix tion are expanded to include reasons
area” is changed to mean the 4K-byte related to the new floating-point facilities.
area designated by the prefix instead of When a data exception is recognized for
real locations 0-4095. This change is con- an old reason related to decimal oper-
sistent with how the term has been used ands, it is called a decimal-operand data
in the definition of the SET PREFIX exception. The detailed description of the
instruction. reasons for recognizing a decimal-operand
data exception is moved from Chapter 6
– Assigned storage locations for the to Chapter 8, “Decimal Instructions.”
PCF-entry-table origin, data-exception
code, and machine-check and store-status – When a program interruption for a data
extended-save-area address are added. exception occurs, a data-exception code
(DXC) may be stored at real location 147
In Chapter 4, “Control”: and placed in the floating-point-control
– Bits 22 and 23 of the PSW are renamed (FPC) register to indicate the reason for
the HFP-exponent-underflow mask and the exception.
the HFP-significance mask, respectively. – The instruction ending for a data excep-
tion may be suppression when previously
Preface xxvii
In Chapter 7, “General Instructions,” the – The COMPARE LOGICAL LONG
PERFORM LOCKED OPERATION instruction EXTENDED and MOVE LONG
is added. EXTENDED instructions of the compare-
and-move-extended facility are added.
In Chapter 10, “Control Instructions,” the
BRANCH AND SET AUTHORITY instruction – The instructions of the immediate-
is added. and-relative-instruction facility are added.
These are:
The above changes may affect other chapters
besides the ones listed. - ADD HALFWORD IMMEDIATE
- BRANCH RELATIVE AND SAVE
- BRANCH RELATIVE ON CONDITION
Summary of Changes in Fourth - BRANCH RELATIVE ON COUNT
Edition - BRANCH RELATIVE ON INDEX
HIGH
The fourth edition of this publication differs from - BRANCH RELATIVE ON INDEX LOW
the previous edition principally by containing the OR EQUAL
definitions of the following facilities: called-space - COMPARE HALFWORD IMMEDIATE
identification, checksum, compare and move - LOAD HALFWORD IMMEDIATE
extended, and immediate and relative instruction. - MULTIPLY SINGLE (two instructions)
The fourth edition also contains additional informa- - MULTIPLY HALFWORD IMMEDIATE
tion about the PER-2 facility, and it describes the - TEST UNDER MASK HIGH
ancillary-report bit in certain fields. The fourth - TEST UNDER MASK LOW
edition contains minor clarifications and cor-
rections and also the following significant changes In Chapter 10, “Control Instructions,” in the
relative to the previous edition: STORE CPU ID definition, the term “model
number” is changed to “machine-type
In Chapter 4, “Control”: number,” and programming notes about the
– Descriptions of an additional bit in the version code and CPU identification number
PER code, the addressing- are added.
and-translation-mode identification, and In Chapter 11, “Machine-Check Handling,” the
the PER STD identification are added. ancillary-report bit in the machine-
– Leap second 20 is added. check-interruption code is described.
In Chapter 5, “Program Execution”: In Chapter 16, “I/O Interruptions,” the
ancillary-report bit in the subchannel logout is
– Instruction formats RI and RSI are added.
described.
– Relative branching is added.
In Chapter 17, “I/O Support Functions,” the
– The section “Condition-Code Alternative to ancillary-report bit in the channel-report word
Interruptibility” is added. is described.
– The called-space identification in the The above changes may affect other chapters
linkage-stack state entry formed by the besides the ones listed.
stacking PROGRAM CALL instruction is
added.
– It is clarified that a storage-operand fetch
Summary of Changes in Third
reference for an instruction can precede Edition
the execution of the instruction by an The third edition of this publication differs from the
unlimited amount of time. previous edition principally by containing the defi-
– A programming note showing effects when nition of the subspace-group facility. The third
CPU serialization is or is not performed is edition contains minor clarifications and cor-
added. rections and also the following significant changes
relative to the previous edition:
In Chapter 7, “General Instructions”:
In Chapter 3, “Storage”:
– The CHECKSUM instruction is added.
Preface xxix
In Appendix I, “EBCDIC and Other Codes,” a dinated Universal Time instead of
chart showing control codes and a Greenwich Mean Time.
94-character EBCDIC character set is
In Chapter 7, “General Instructions”:
replaced by a table showing control codes,
various EBCDIC character sets and code – The instructions of the string-instruction
pages, ASCII, ISO-8, and IBM-PC code facility, COMPARE LOGICAL STRING,
pages, and BookMaster* symbols. MOVE STRING, and SEARCH STRING,
are added.
The above changes may affect other chapters
besides the ones listed. – The COMPARE UNTIL SUBSTRING
EQUAL instruction is added. This instruc-
tion was introduced in ESA/370 but has
Summary of Changes in Second not previously been described.
Edition In Chapter 10, “Control Instructions,” the SET
The second edition of this publication contains ADDRESS SPACE CONTROL FAST instruc-
minor clarifications and corrections and also the tion is added.
following significant changes relative to the pre- In Chapter 12, “Operator Facilities,” a defi-
vious edition with TNL SN22-5400: nition of the effect of initial machine loading
In Chapter 3, “Storage”: (IML) on expanded storage is added.
– The standard epoch for the time-of-day The above changes may affect other chapters
(TOD) clock is described in terms of Coor- besides the ones listed.
This publication provides, for reference purposes, ison of the differences among ESA/390, ESA/370,
a detailed Enterprise Systems Architecture/390 370-XA, and System/370 appears in Appendixes
(ESA/390) description. D, E, and F.
The architecture of a system defines its attributes ESA/390 was announced in September, 1990.
as seen by the programmer, that is, the concep- Any extension added subsequently has the date of
tual structure and functional behavior of the its announcement in parentheses at the end of its
machine, as distinct from the organization of the summary.
data flow, the logical design, the physical design,
and the performance of any particular implementa- The following extensions are described in detail in
tion. Several dissimilar machine implementations this publication:
may conform to a single architecture. When the Access-list-controlled protection allows store-
execution of a set of programs on different type storage references to an address space
machine implementations produces the results to be prohibited by means of a bit in the
that are defined by a single architecture, the access-list entry used to access the space.
implementations are considered to be compatible Thus, different users having different access
for those programs. lists can have different capabilities to store in
the same address space.
AIX/ESA and CICS are trademarks of the International Business Machines Corporation.
| 1 These key lengths reflect the cryptographic strength. In subsequent chapters, they are referred to as 64-bit, 128-bit, or 192-bit,
| respectively, to include the DEA-key-parity bits.
MVS/ESA, VM/ESA, Sysplex Timer, and DB2 are trademarks of the International Business Machines Corporation.
Processor Resource/Systems Manager and PR/SM are trademarks of the International Business Machines Corporation.
┌───┐
Logically, a system consists of main storage, one /──────────┤ETR├──────────/
or more central processing units (CPUs), operator └─┬─┘
│
facilities, a channel subsystem, and I/O devices. ┌──────────────────┐ │
│ │ ┌─┴─────────┐ ┌──────────────┐
I/O devices are attached to the channel sub- │ │ │ ├──────┤ │
system through control units. The connection │ ├────┤ CPU ├──┐ │ │
│ │ │ ┌──────┤ │ │ │
between the channel subsystem and a control unit │ │ │ │Vector│ │ │ │
│ │ └─┬──┴──────┘ │ │ │
is called a channel path. │ │ │ │ │ │
│ Expanded Storage │ ┌─┴─────────┐ │ │ Main Storage │
│ │ │ ├──┼───┤ │
A channel path employs either a parallel- │ ├────┤ CPU ├──┤ │ │
│ │ │ ┌──────┤ │ │ │
transmission protocol or a serial-transmission pro- │ │ │ │Crypto│ │ │ │
tocol and, accordingly, is called either a parallel or │ │ └────┴──────┘ │ │ │
│ │ │ └───────┬──────┘
a serial channel path. A serial channel path may │ │ ┌───────────┘ │
└──────────────────┘ │ │
connect to a control unit through a dynamic switch │ ┌───────────────────┘
│ │
that is capable of providing different internal con- ┌─────────────────────────┴───┴────────────────────────┐
nections between the ports of the switch. │ │
│ Channel │
│ Subsystem │
Expanded storage may also be available in the └─┬───┬───┬──────┬───┬────────┬─┬─┬─┬───┬──────────────┘
│...│...│......│...│ │ │ │ │...│
system, a vector or cryptographic unit may be │ │ │ │ │ │ │ │ │ │
Serial Channel Paths Parallel Channel Paths
included in a CPU, and an external time reference │ │ │ │ │ │ │ │ │ │
(ETR) may be connected to the system. │ │ │ │ │ │ │ / / └──────────┬───────/
│ ┌─┴───┴─┐ ┌─┴───┴─┐ │ │ │
│ │Dynamic│ │Dynamic│ │ └──┬─────────/ │
│ │Switch │ │Switch │ │ ┌─┴┐ ┌─┴┐
The physical identity of the above functions may │ └─┬───┬─┘ └┬─┬───┬┘ │ │CU│ │CU├─┬─┬─┬─/
vary among implementations, called “models.” │ │...│ │ │...│ │ └─┬┘ ┌─┐ └─┬┘ O O O
│ │ └─────┼┐│ │ │ └──┤ │ │
Figure 2-1 depicts the logical structure of a │ │┌────────┘││ │ │ ┌──┤ ├─┬─┬─┬─/ │
│ ││ ││ │ │ ┌─┴┐ └─┘ O O O │
two-CPU multiprocessing system that includes ┴─┐┌┴┴┐ ┌┴┴┐ │ │ │CU│ │
expanded storage, a vector unit, and a ┌CU││CU│ │CU│ │ │ └─┬┘ │
│┬─┘└┬─┘ └┬─┘ │ └────┴──────┬────────┴───────/
cryptographic unit and that is connected to an └│ │ │ ┌┴─┐ ┌─┴┐
│ └─┬─┬─┬─/ │ │CU├─┬─┬─┬─/ │CU├─┬─┬─┬─/
ETR. │ O O O │ └──┘ O O O └──┘ O O O
└─┬─┬─┬─/ └─┬─┬─┬─/
O O O O O O
Specific processors may differ in their internal
characteristics, the installed facilities, the number Figure 2-1. Logical Structure of an ESA/390 System
of subchannels, channel paths, and control units with Two CPUs
which can be attached to the channel subsystem,
the size of main and expanded storage, and the A system viewed without regard to its I/O devices
representation of the operator facilities. is referred to as a configuration. All of the phys-
ical equipment, whether in the configuration or not,
is referred to as the installation.
Note: The arrows indicate that the two registers may be coupled as a double-register pair,
designated by specifying the lower-numbered register in the R field. For example, the floating-point
register pair 13 and 15 is designated by 1101 binary in the R field.
Figure 2-2. Control, Access, General, and Floating-Point Registers
ESCON and FICON are trademarks of the International Business Machines Corporation.
This chapter discusses the representation of infor- translated to another type of address. A list of
mation in main storage, as well as addressing, permanently assigned storage locations appears
protection, and reference and change recording. at the end of the chapter.
The aspects of addressing which are covered
include the format of addresses, the concept of Main storage provides the system with directly
address spaces, the various types of addresses, addressable fast-access storage of data. Both
and the manner in which one type of address is data and programs must be loaded into main
Key-controlled protection affords protection against When the access to storage is for the purpose of
improper storing or against both improper storing channel-program execution, the subchannel key
and fetching, but not against improper fetching associated with that channel program is the
alone. access key. The subchannel key for a channel
program is specified in the operation-request block
Key-Controlled Protection (ORB). When, for purposes of channel-subsystem
monitoring, an access to the measurement block
When key-controlled protection applies to a is made, the measurement-block key is the access
storage access, a store is permitted only when the key. The measurement-block key is specified by
storage key matches the access key associated the SET CHANNEL MONITOR instruction.
with the request for storage access; a fetch is per-
When a CPU access is prohibited because of key-
mitted when the keys match or when the fetch-
controlled protection, the execution of the instruc-
protection bit of the storage key is zero.
tion is terminated, and a program interruption for a
The keys are said to match when the four access- protection exception takes place. However, if the
control bits of the storage key are equal to the suppression-on-protection facility is installed, the
access key, or when the access key is zero. execution of the instruction may be suppressed.
When a channel-program access is prohibited, the
The protection action is summarized in Figure 3-3. start function is ended, and the protection-check
condition is indicated in the associated
┌─────────────────────────────┬──────────────────┐ interruption-response block (IRB). When a
│ Conditions │ Is Access to │
├────────────────┬────────────┤Storage Permitted?│
measurement-block access is prohibited, the I/O
│Fetch-Protection│ ├─────────┬────────┤ measurement-block protection-check condition is
│ Bit of │ │ │ │ indicated.
│ Storage Key │Key Relation│ Fetch │ Store │
├────────────────┼────────────┼─────────┼────────┤
│ │ Match │ Yes │ Yes │ When a store access is prohibited because of key-
│ │ Mismatch │ Yes │ No │ controlled protection, the contents of the protected
│ 1 │ Match │ Yes │ Yes │ location remain unchanged. When a fetch access
│ 1 │ Mismatch │ No │ No │
├────────────────┴────────────┴─────────┴────────┤ is prohibited, the protected information is not
│Explanation: │ loaded into a register, moved to another storage
│ │ location, or provided to an I/O device. For a pro-
│ Match The four access-control bits of the │
│ storage key are equal to the access │
hibited instruction fetch, the instruction is sup-
│ key, or the access key is zero. │ pressed, and an arbitrary instruction-length code is
│ │ indicated.
│ Yes Access is permitted. │
│ │
│ No Access is not permitted. On fetching, │ Key-controlled protection is independent of
│ the information is not made available │ whether the CPU is in the problem or the super-
│ to the program; on storing, the con- │ visor state and, except as described below, does
│ tents of the storage location are not │
│ changed. │ not depend on the type of CPU instruction or
└────────────────────────────────────────────────┘ channel-command word being executed.
Figure 3-3. Summary of Protection Action
Except where otherwise specified, all accesses to
storage locations that are explicitly designated by
When the access to storage is initiated by the
the program and that are used by the CPU to
CPU and key-controlled protection applies, the
store or fetch information are subject to key-
PSW key is the access key, except that the
controlled protection.
access key is specified in a general register for
the first operand of MOVE TO SECONDARY and
Key-controlled protection does not apply when the
MOVE WITH DESTINATION KEY, for the second
storage-protection-override control is one and the
operand of MOVE TO PRIMARY, MOVE WITH
value of the four access-control bits of the storage
| KEY, and MOVE WITH SOURCE KEY, and for
key is 9. Key-controlled protection for fetches
| either the first or the second operand of MOVE
If a protection-exception condition exists due to 3. AIX/ESA does not use key-controlled pro-
either access-list-controlled protection or page pro- tection. The virtual-address enhancement
tection but also exists due to either low-address extends the usefulness of suppression on pro-
protection or key-controlled protection, it is unpre- tection to other operating systems that do use
| dictable whether bit 29 is set to zero or one. key-controlled protection.
4. The results of suppression on protection are
Programming Notes: summarized in Figure 3-4 on page 3-14.
1. The suppression-on-protection facility is useful
in performing the AIX/ESA copy-on-write func-
tion, in which AIX/ESA causes the same page
of different address spaces to map to a single
page frame of real storage so long as a store
in the page is not attempted and then, when a
1 The virtual-address enhancement is always installed along with the suppression-on-protection facility except that, on 9121 models,
the virtual-address enhancement is installed only if SEC C35954 is installed.
Reference recording does not occur for operand It is unpredictable whether change recording takes
accesses of the following instructions since they place for the instruction PAGE IN.
directly refer to a storage key without accessing a
storage location: Change recording does not take place for the
operands of the following instructions since they
INSERT STORAGE KEY EXTENDED
(1) Real addresses in which bits 1-19 are equal to the prefix for this CPU (A or B).
(2) Absolute addresses of the block that contains for this CPU (A or B) the real locations 0-4095.
Figure 3-5. Relationship between Real and Absolute Addresses
All four bytes of the ASN-first-table entry appear to or when the AST-entry size is 64 bytes and bit
be fetched concurrently as observed by other positions 26-31 of the AFT entry do not contain
CPUs. The fetch access is not subject to pro- zeros, an ASN-translation-specification exception
tection. When the storage address which is gen- may be recognized. When no exceptions are
erated for fetching the ASN-first-table entry desig- recognized, the entry fetched from the AFT is
nates a location which is not available in the con- used to access the AST.
figuration, an addressing exception is recognized,
and the operation is suppressed. ASN-Second-Table Lookup
The ASX portion of the ASN, in conjunction with
Bit 0 of the four-byte AFT entry specifies whether the ASN-second-table origin contained in the
the corresponding AST is available. If this bit is ASN-first-table entry, is used to select an entry
one, an AFX-translation exception is recognized. from the ASN second table.
When the AST-entry size is 16 bytes and bit posi-
tions 28-31 of the AFT entry do not contain zeros, When the address-space-function (ASF) control,
┌─────────────────┬────────────┬────┬──
│ │ ATL ││ ASN-Authorization Process
└─────────────────┴────────────┴────┴──
32 48 6 64 This section describes the ASN-authorization
process as it is performed during the execution of
PROGRAM TRANSFER with space switching and
Authority-Table Origin (ATO): Bits 1-29, with
SET SECONDARY ASN with space switching.
two zeros appended on the right, are used to form
For these two instructions, the ASN-authorization
a 31-bit real address that designates the begin-
process is performed by using the authorization
ning of the authority table.
index currently in control register 4. Secondary
Authority-Table Length (ATL): Bits 48-59 authorization for PROGRAM RETURN, when the
specify the length of the authority table in units of restored secondary ASN does not equal the
four bytes, thus making the authority table variable restored primary ASN, and for LOAD ADDRESS
in multiples of 16 entries. The length of the SPACE PARAMETERS is the same, except that
authority table, in units of four bytes, is equal to the value which will become the new contents of
one more than the ATL value. The contents of control register 4 is used for the authorization
the length field are used to establish whether the index. Also, for LOAD ADDRESS SPACE
entry designated by the authorization index falls PARAMETERS, a secondary-authority exception
within the authority table. does not occur. Instead, such a condition is indi-
cated by the condition code.
┌───────┬───────┐
CR4 │ AX │ │
└───┬───┴───────┘
│(x1/4)
│
┌─────────────┘
│
│
│ ASN Second Table
│ ┌─────────────────────────────────────────────────────────────────────┐
│ │ │
│ │ │
│ │ASN-Second-Table Entry │
│ ├─┬────────────┬──┬────────┬──────┬─┬────────────────┬────────────────┤
│ │I│ ATO │B│ AX │ ATL ││ STD │ LTD │
│ ├─┴──────┬─────┴──┴────────┴──────┴─┴────────────────┴────────────────┤
│ │ │(x4) │
│ │ │ │
│ └────────┼────────────────────────────────────────────────────────────┘
┌─────┼────────────┘
│ │
│ │
│ │
│
│ ┌─┐ Authority Table
└───│+│ ┌───┐
└┬┘ │ │ For primary ASN authorization (PT-ss only):
│ │ │ Primary-authority exception if P bit
│ │ │ zero or table length exceeded.
└─├─┬─┤
R │P│S│ For secondary ASN authorization (PR and SSAR-ss only):
├─┴─┤ Secondary-authority exception if S bit
│ │ zero or table length exceeded.
│ │
└───┘ For secondary ASN authorization (LASP only):
Set condition code 2 if S bit zero or
table length exceeded.
R: Address is real
: ASTE is 64 bytes if ASF control is one; last 48 bytes are not shown
Figure 3-7. ASN Authorization
The translation process consists in a two-level Page-Table Length (PTL): Bits 28-31 specify the
lookup using two tables: a segment table and a length of the page table in units of 64 bytes (16
page table. These tables reside in real or abso- entries). The length of the page table, in units of
lute storage. 64 bytes, is one more than the PTL value. The
contents of the length field are used to establish
whether the entry designated by the page-index
Segment-Table Entries
portion of the virtual address falls within the page
The entry fetched from the segment table has the
table.
following format:
┌─┬─────────────────────────┬─┬─┬────┐ Bit 0 of the segment-table entry must be zero; if it
││ Page-Table Origin │I│C│PTL │ is not zero, a translation-specification exception is
└─┴─────────────────────────┴─┴─┴────┘
1 26 28 31 recognized as part of the execution of an instruc-
tion using that entry for address translation.
The fields in the segment-table entry are allocated
as follows: Page-Table Entries
The entry fetched from the page table has the fol-
Page-Table Origin (PTO): Bits 1-25, with six
lowing format:
zeros appended on the right, form the address
that designates the beginning of a page table. It
The page-index portion of the virtual address is Whenever access to real or absolute storage is
used to select an entry from the page table. This made during the address-translation process for
entry contains the leftmost bits of the real address the purpose of fetching an entry from a segment
that represents the translation of the virtual table or page table, key-controlled protection does
address and provides the page-protection bit. not apply.
┌─┐
│2│ Information, which may include portions of the virtual address and the
└─┘ effective segment-table origin, is used to search the TLB.
┌─┐
│3│ If a match exists, the page-frame real address from the TLB is used in
└─┘ forming the real address.
┌─┐
│4│ If no match exists, table entries in real or absolute storage are fetched.
└─┘ The resulting fetched entries, in conjunction with the search information,
are used to translate the address and may be used to form an entry in the
TLB.
Figure 3-10 (Part 2 of 2). Translation Process
This chapter describes in detail the facilities for load state during the initial-program-loading opera-
controlling, measuring, and recording the opera- tion. The CPU enters the check-stop state only as
tion of one or more CPUs. the result of machine malfunctions.
Address-Space Control (AS): Bits 16 and 17, in Bit positions 0, 2-4, and 24-31 are unassigned and
conjunction with PSW bit 5, control the translation must contain zeros. A specification exception is
mode. See “Translation Modes” on page 3-28. recognized when these bit positions do not contain
zeros. When bit 32 of the PSW specifies the
Condition Code (CC): Bits 18 and 19 are the 24-bit addressing mode, bits 33-39 of the instruc-
two bits of the condition code. The condition code tion address must be zeros; otherwise, a specifi-
is set to 0, 1, 2, or 3, depending on the result cation exception is recognized. A specification
obtained in executing certain instructions. Most exception is also recognized when bit position 12
arithmetic and logical operations, as well as some does not contain a one.
other operations, set the condition code. The
instruction BRANCH ON CONDITION can specify
any selection of the condition-code values as a Control Registers
criterion for branching. A table in Appendix C
The control registers provide for maintaining and
summarizes the condition-code values that may
manipulating control information outside the PSW.
be set for all instructions which set the condition
There are sixteen 32-bit control registers.
code of the PSW.
All control-register bit positions in all 16 control
Program Mask: Bits 20-23 are the four program-
registers are installed, regardless of whether the
mask bits. Each bit is associated with a program
bit position is assigned to a facility. One or more
exception, as follows:
specific bit positions in control registers are
┌────────────┬──────────────────────────┐ assigned to each facility requiring such register
│ Program- │ │ space.
│ Mask Bit │ Program Exception │
├────────────┼──────────────────────────┤
│ 2 │ Fixed-point overflow │ The LOAD CONTROL instruction causes all
│ 21 │ Decimal overflow │ control-register bit positions within those registers
│ 22 │ HFP exponent underflow │ designated by the instruction to be loaded from
│ 23 │ HFP significance │ storage. The instructions BRANCH AND SET
└────────────┴──────────────────────────┘ AUTHORITY, BRANCH IN SUBSPACE GROUP,
24-Bit Branch
┌────────┬─────────────────────────┐
││ Branch Address │
└────────┴─────────────────────────┘
8 31
PROGRAM CALL
┌────────┬────┬────────────────────┬─┬────────────────────────────┬─┐
│ │PSW │ │ │ │ │
│11│Key │ PC Number │A│ Return Address │P│
└────────┴────┴────────────────────┴─┴────────────────────────────┴─┘
8 12 32 63
PROGRAM RETURN
┌────────┬────┬────┬───────────────┬─┬────────────────────────────┬─┐
│ │PSW │ │ │ │ │ │
│111│Key ││ New PASN │A│ Return Address │P│
└────────┴────┴────┴───────────────┴─┴────────────────────────────┴─┘
8 12 16 32 63
┌─┬────────────────────────────────┐
│ │ │
│A│ Updated Instruction Address │
└─┴────────────────────────────────┘
64 95
PROGRAM TRANSFER
┌────────┬────┬────┬───────────────┬────────────────────────────────┐
│ │PSW │ │ │ │
│111│Key ││ New PASN │ R before │
└────────┴────┴────┴───────────────┴────────────────────────────────┘
8 12 16 32 63
Figure 4-4 (Part 1 of 2). Trace-Entry Formats
TRACE
┌────┬────┬────────┬────────────────────────────────────────────────┐
│111│ N ││ TOD-Clock Bits 16-63 │
└────┴────┴────────┴────────────────────────────────────────────────┘
4 8 16 63
┌──────────────────────────────────┬────────────────/───────────────┐
│ TRACE Operand │ (R) - (R) │
└──────────────────────────────────┴────────────────/───────────────┘
64 96 95 + 32(N+1)
Figure 4-4 (Part 2 of 2). Trace-Entry Formats
(R) - (R): The four-byte fields starting with bit If a program interruption takes place for a condi-
96 of the trace entry for TRACE contain the con- tion which is not a trace-exception condition and
tents of the general registers whose range is for which execution of an instruction is not com-
specified by the R and R fields of the TRACE pleted, it is unpredictable whether part or all of
instruction. The general registers are stored in any trace entry due to be made for such an inter-
ascending order of register numbers, starting with rupted instruction is stored in the trace table.
general register R and continuing up to and Thus, for a condition which would ordinarily cause
including general register R, with general register nullification or suppression of instruction exe-
0 following general register 15. cution, storage locations may have been altered
beginning at the location designated by control
Programming Note: The size of the trace entry
register 12 and extending up to the length of the
for TRACE in units of words is 3 + (N + 1). The
entry that would have been created.
maximum size of an entry is 19 words, or 76
bytes.
When PROGRAM RETURN unstacks a linkage-
stack state entry that was formed by BRANCH
Operation AND STACK and ASN tracing is on, trace
exceptions may be recognized, even though a
When an instruction which is subject to tracing is trace entry is not made and no part of a trace
executed and the corresponding tracing function is entry is stored.
turned on, a trace entry of the appropriate format
is made. The real address of the trace entry is The order in which information is placed in a trace
formed by appending two zero bits on the right to entry is unpredictable. Furthermore, as observed
the value in bit positions 1-29 of control register by other CPUs and by channel programs, the con-
12. The address in control register 12 is subse- tents of a byte of a trace entry may appear to
quently increased by the size of the entry created. change more than once before completion of the
instruction for which the entry is made.
No trace entry is stored if the incrementing of the
address in control register 12 would cause a carry The trace-entry address in control register 12 is
to be propagated into bit position 19 (that is, if the updated only on completion of execution of an
trace-entry address would be in the next 4K-byte instruction for which a trace entry is made.
block). If this would be the case for the entry to
be made, a trace-table exception is recognized. A serialization and checkpoint-synchronization
For the purpose of recognizing the trace-table function is performed before the operation begins
exception in the case of a TRACE instruction, the and again after the operation is completed.
maximum length of 76 bytes is used instead of the
actual length.
Program-Event Recording
The storing of a trace entry is not subject to key-
There are two versions of the program-event-
controlled protection (nor, since the trace-entry
recording (PER) facility. The version which is the
address is real, is it subject to access-list-
same as PER in ESA/370 is named PER 1, and
controlled protection or page protection), but it is
the other version is named PER 2. A model pro-
subject to low-address protection; that is, if the
vides either PER 1 or PER 2.
address of the trace entry due to be created is in
the range 0-511 and bit 3 of control register 0 is Unless otherwise noted, the descriptions in this
one, a protection exception is recognized, and section apply to both PER 1 and PER 2. The dif-
instruction execution is suppressed. If the ferences between PER 1 and PER 2 are pointed
address of a trace entry is invalid, an addressing out in the section.
exception is recognized, and instruction execution
is suppressed.
The information for controlling PER resides in Branch-Address Control (B): With PER 2, bit 8
control registers 9, 10, and 11 and the segment- of control register 9 specifies, when one, that
table designation. The information in the control successful-branching events occur only for
registers has the following format: branches that are to a location within the desig-
nated storage area. With PER 1, or with PER 2
PER-1 Control Register 9 when bit 8 is zero, successful-branching events
┌─────┬───────────┬────────────────┐ occur regardless of the branch-target address. Bit
│ EM │ │Gen.-Reg. Masks │ 8 is ignored by PER 1.
└─────┴───────────┴────────────────┘
5 16 31
Storage-Alteration-Space Control (S): With
PER 2, bit 10 of control register 9 specifies, when
PER-2 Control Register 9 one, that storage-alteration events occur as a
┌─────┬────┬─┬─┬─┬────────────────┐ result of references to the designated storage area
│ EM │ │B│ │S│ │
└─────┴────┴─┴─┴─┴────────────────┘ only within designated address spaces. An
5 8 1 31 address space is designated as one for which
Storage-Alteration-Event Bit (S): With PER 2, An interruption due to a PER event normally
when the storage-alteration-space control in occurs after the execution of the instruction
control register 9 is one, bit 24 of the segment- responsible for the event. The occurrence of the
table designation specifies, when one, that the event does not affect the execution of the instruc-
address space defined by the segment-table des- tion, which may be completed, partially completed,
ignation is one for which storage-alteration events terminated, suppressed, or nullified. However, on
can occur. Bit 24 is examined when the segment- a model on which z/Architecture is installed,
table designation is used to perform dynamic- recognition of a storage-alteration event causes no
address translation for a storage-operand store more than 4K bytes to be stored beginning with
reference. The segment-table designation may be the byte that caused the event, and this may
the PSTD, SSTD, or HSTD in control register 1, 7, result in partial completion of an interruptible
or 13, respectively, or it may be obtained from an instruction.
ASN-second-table entry during access-register
translation. Instead of being obtained from an When the CPU is disabled for a particular PER
ASN-second-table entry in main storage, bit 24 event at the time it occurs, either by the PER
Bits 9-13 of real locations 150-151 are named the PER STD Identification (SI): With PER 2, if a
addressing-and-translation-mode identification storage-alteration event is indicated in the PER
(ATMID). Bit 9 is named the ATMID-validity bit. code (bit 2 is one and bit 4 is zero) and this event
When bit 9 is zero, it indicates that an invalid occurred when DAT was on, bits 14 and 15 of
ATMID (all zeros) was stored. locations 150-151 are set to identify the segment-
table designation (STD) that was used to translate
The meanings of the bits of a valid ATMID are as the reference that caused the event, as follows:
follows:
Bits
Bit Meaning 14-15 Meaning
9 ATMID-validity bit 00 Primary STD was used.
10 PSW bit 32 01 An AR-specified STD was used. The PER
11 PSW bit 5 access id, real location 161, can be exam-
12 PSW bit 16 ined to determine the STD used.
13 PSW bit 17 However, if the primary, secondary, or
A valid ATMID is necessarily stored only if the home STD was used, bits 14 and 15 may
PER event was caused by one of the following be set to 00, 10, or 11, respectively,
instructions: instead of to 01.
10 Secondary STD was used.
BRANCH AND SAVE AND SET MODE 11 Home STD was used.
(BASSM)
BRANCH AND SET AUTHORITY (BSA) The CPU may avoid setting bits 14 and 15 to 01
BRANCH AND SET MODE (BSM) by recognizing that access-list-entry token (ALET)
BRANCH IN SUBSPACE GROUP (BSG) 00000000 or 00000001 hex was used or that the
LOAD PSW (LPSW) ALET designated, through an access-list entry, an
PROGRAM CALL (PC) ASN-second-table entry containing an STD equal
PROGRAM CALL FAST (PCF) to the primary STD, secondary STD, or home
PROGRAM RETURN (PR) STD.
PROGRAM TRANSFER (PT)
If a storage-alteration event is not indicated in the
RESUME PROGRAM (RP)
PER code (bit 2 is zero or bit 4 is one) or DAT
SET ADDRESS SPACE CONTROL (SAC)
was off, zeros are stored in bit positions 14 and
SET ADDRESS SPACE CONTROL FAST
15.
(SACF)
SET SYSTEM MASK (SSM)
With PER 1, zeros are stored in bit positions 4-15
STORE THEN AND SYSTEM MASK
of locations 150-151. With PER 2, zeros are
(STNSM)
stored in bit positions 3 and 5-8 of locations
STORE THEN OR SYSTEM MASK (STOSM)
150-151.
SUPERVISOR CALL (SVC)
TRAP (TRAP2, TRAP4) PER Address: The PER-address field at
It is unpredictable whether a valid ATMID is stored locations 152-155 contains the instruction address
if the PER event was caused by any other instruc- used to fetch the instruction in execution when
tion. one or more PER events were recognized. When
the instruction is the target of EXECUTE, the
In the case of an instruction-fetching PER event instruction address used to fetch the EXECUTE
caused by SET ADDRESS SPACE CONTROL or instruction is placed in the PER-address field. A
SET ADDRESS SPACE CONTROL FAST, bits 12 zero is stored in bit position 0 of real location 152.
and 13 of the ATMID, which correspond to bits 16
and 17 of the PSW, may indicate that the CPU PER Access Identification (PAID): If a storage-
was in the primary-space mode when it actually alteration event is indicated in the PER code, an
was in the primary-space, secondary-space, or indication of the address space to which the event
access-register mode. In any of those modes, the applies may be stored at location 161. If the
┌─────────────────────────────┬──────┬────────────────────────────────────┐
│ │ │ PER Event │
│ │ Type ├──────┬──────┬───────┬───────┬──────┤
│ │ of │ │Instr │Storage│ GR │ │
│ Concurrent Condition │Ending│Branch│Fetch │Alter. │Alter.│STURA │
├─────────────────────────────┼──────┼──────┼──────┼───────┼───────┼──────┤
│Specification │ │ │ │ │ │ │
│ Odd instruction address │ S │ No │ No │ No │ No │ No │
│ in the PSW │ │ │ │ │ │ │
│Instruction access │N or S│ No │ U │ No │ No │ No │
│Specification │ │ │ │ │ │ │
| │ EXECUTE target address odd│ S │ No │ U │ No │ No │ No │
| │EXECUTE target access │N or S│ No │ U │ No │ No │ No │
│Other nullifying │ N │ No │ Yes │ No │ No │ - │
│Other suppressing │ S │ No │ Yes │ No │ No │ No │
│All terminating │ T │ No │ Yes │ Yes │ Yes │ - │
│All completing │ C │ Yes │ Yes │ Yes │ Yes │ - │
├─────────────────────────────┴──────┴──────┴──────┴───────┴───────┴──────┤
│Explanation: │
│ │
│ - The condition does not apply. │
│ │
│ With PER 2, PER general-register-alteration events do not occur │
│ and are not indicated. │
│ │
| │ It is unpredictable whether the PER event is indicated for the │
| │ target instruction, and it is unpredictable whether the PER event│
| │ is indicated for the EXECUTE instruction. │
│ │
│ Although PER events of this type are not indicated for the cur- │
│ rent unit of operation of an interruptible instruction, PER │
│ events of this type that were recognized on completed units of │
│ operation of the interruptible instruction are indicated. │
│ │
│ This event may be indicated, depending on the model, if the │
│ event has not occurred but would have been indicated if execu- │
│ tion had been completed. │
│ │
│ C The operation or, in the case of the interruptible instructions, │
│ the unit of operation is completed. │
│ │
│ N The operation or, in the case of the interruptible instructions, │
│ the unit of operation is nullified. │
│ │
│ S The operation or, in the case of the interruptible instructions, │
│ the unit of operation is suppressed. │
│ │
│ T The execution of the instruction is terminated. │
│ │
│ Yes The PER event is indicated with the other program-interruption │
| │ condition if the event has occurred; that is, the instruction │
| │ address in the PSW was replaced and the branch-address control │
| │ and designated storage area allow the event occurrence, an │
| │ attempt was made to execute an instruction whose first byte is │
| │ located in the designated storage area, or the contents of the │
| │ the designated storage area or a designated general register were│
| │ altered. │
└─────────────────────────────────────────────────────────────────────────┘
Figure 4-5 (Part 1 of 2). Indication of PER Events with Other Concurrent Conditions
Programming Notes:
TOD-Clock Synchronization
1. TOD-clock synchronization provides for syn-
In a configuration with more than one CPU, each chronizing and checking only bits 32 through
CPU may have a separate TOD clock, or more the rightmost incremented bit of the TOD
than one CPU may share a TOD clock, depending clock. When more than one clock exists in
on the model. In all cases, each CPU has access the configuration, the program must check for
to a single clock. synchronization of the leftmost bits and must
communicate the leftmost bit values from one
The TOD-clock-synchronization facility, in conjunc- CPU to another in order to correctly set the
tion with a clock-synchronization program, makes
When the reset function in the CPU is initiated at 2. All floating interruption conditions in the con-
the time the CPU is executing an I/O instruction or figuration are cleared.
is performing an I/O interruption, the current oper- As part of I/O-system reset, pending
ation between the CPU and the channel sub- I/O-interruption conditions are cleared, and system
system may or may not be completed, and the reset is signaled to all control units and devices
resultant state of the associated channel- attached to the channel subsystem (see
subsystem facility may be unpredictable. “I/O-System Reset” on page 17-13). The effect of
Programming Note: Most operations which system reset on I/O control units and devices and
would change a state, a condition, or the contents the resultant control-unit and device state are
of a field cannot occur when the CPU is in the described in the appropriate System Library publi-
stopped state. However, some signal-processor cation for the control unit or device. A system
functions and some operator functions may reset, in general, resets only those functions in a
change these fields. To eliminate the possibility of shared control unit or device that are associated
losing a field when CPU reset is issued, the CPU with the particular channel path signaling the
reset.
Restart: The addressed CPU performs the The set-prefix order is completed as follows:
restart operation (see “Restart Interruption” on If the addressed CPU is not in the stopped
page 6-46). The CPU does not necessarily state, the order is not accepted. Instead, bit
perform the operation during the execution of 22 (incorrect state) of the general register des-
SIGNAL PROCESSOR. The order is effective ignated by the R field of the SIGNAL
only when the addressed CPU is in the stopped or PROCESSOR instruction is set to one, and
the operating state. condition code 1 is set.
Stop and Store Status: The addressed CPU The value to be placed in the prefix register of
performs the stop function, followed by the store- the addressed CPU is tested for the avail-
status operation (see “Store Status” on ability of the designated storage. The abso-
page 4-43). The CPU does not necessarily com- lute address of a 4K-byte area of storage is
plete the operation, or even enter the stopped formed by appending 12 zeros to the right of
state, during the execution of SIGNAL bits 1-19 of the parameter value. This
PROCESSOR. The order is effective only when address is treated as a 31-bit absolute
the addressed CPU is in the stopped or the oper- address regardless of whether the sending
ating state. and receiving CPUs are in the 24-bit or 31-bit
addressing mode. The 4K-byte block of
Initial CPU Reset: The addressed CPU performs storage at this address is accessed. The
initial CPU reset (see “Resets” on page 4-37). access is not subject to protection, and the
The execution of the reset does not affect other associated reference bit may or may not be
CPUs and does not cause I/O to be reset. The set to one. If the block is not available in the
reset operation is not necessarily completed configuration, the order is not accepted by the
during the execution of SIGNAL PROCESSOR.
When a calling linkage is to increase authority, the The BRANCH IN SUBSPACE GROUP instruction
calling linkage can be performed by PROGRAM is available when the subspace-group facility is
CALL and the return linkage by PROGRAM installed. The instruction allows linkage within a
TRANSFER. Alternatively, when the calling group of address spaces called a subspace group,
linkage is to decrease authority, the calling linkage where one address space in the group is called
can be performed by PROGRAM TRANSFER and the base space and the others are called sub-
the return linkage by PROGRAM CALL. spaces. It is intended that each subspace contain
a different subset of the storage in the base
The operation of PROGRAM CALL is controlled space, that the base space and each subspace
by means of an entry-table entry, which is located contain a subsystem control program, such as
as part of a table-lookup process during the exe- CICS, and application programs, and that each
cution of the instruction. The entry-table entry subspace contain the data for a single transaction
specifies either a basic (nonstacking) operation or being processed under the subsystem control
the stacking operation described in “Linkage-Stack program. The placement of the data for each
Introduction” on page 5-60. The instruction transaction in a different subspace prevents a
causes the primary address space to be changed program that is being executed to process one
only when the ASN in the entry-table entry is particular transaction from erroneously damaging
nonzero. When the primary address space is the data of other transactions. It is intended that
changed, the operation is called PROGRAM CALL the primary address space be the base space
with space switching (PC-ss). When the primary when the control program is being executed, and
address space is not changed, the operation is that it be the subspace for a transaction when an
called PROGRAM CALL to current primary application program is being executed to process
(PC-cp). that transaction. BRANCH IN SUBSPACE
GROUP changes not only the instruction address
PROGRAM TRANSFER specifies the new in the PSW but also the primary segment-table
addressing mode and the address space which is designation in control register 1. BRANCH IN
to become the new primary address space. When SUBSPACE GROUP does not change the primary
the primary address space is changed, the opera- ASN in control register 4 or the
tion is called PROGRAM TRANSFER with space primary-ASN-second-table-entry origin in control
switching (PT-ss). When the primary address register 5, and, therefore, the base space and the
space is not changed, the operation is called subspaces all are associated with the same ASN,
PROGRAM TRANSFER to current primary and the programs in those address spaces all are
(PT-cp). of equal authority.
The BRANCH AND SET AUTHORITY instruction Although a subspace is intended to be a subset of
is available when the branch-and-set-authority the base space as described above, the
facility is installed. BRANCH AND SET subspace-group facility does not require this, and
AUTHORITY can improve performance by the facility may be useful in ways other than as
replacing a PT-cp instruction used to perform a described above.
calling linkage in which PSW-key-mask authority is
reduced, and by replacing a PC-cp instruction BRANCH IN SUBSPACE GROUP uses an
used to perform the associated return linkage in access-list-entry token (ALET) in an access reg-
which PSW-key-mask authority is restored. ister as an identifier of the address space that is
BRANCH AND SET AUTHORITY also permits to receive control. The instruction saves the
changes between the supervisor and problem updated instruction address to permit a return
states, and it can replace SET PSW KEY FROM linkage, but it does not save an identifier of the
ADDRESS by changing the PSW key during the address space from which control was transferred.
linkage. The calling-linkage operation is called However, an ALET equal to 00000000 hex, called
BRANCH AND SET AUTHORITY in the base- ALET 0, can be used to return from a subspace to
authority state (BSA-ba), and the return-linkage the base space, and an ALET equal to 00000001
Programming Note: This section describes the PSW status is provided. The return from a routine
linkage instructions that were included in 370-XA called by SUPERVISOR CALL normally is accom-
and carried forward to ESA/370 and ESA/390. To plished by means of LOAD PSW, which is a privi-
give the reader a better understanding of the utility leged instruction.
and intended usage of these linkage instructions,
the following paragraphs in this note describe PROGRAM CALL is provided for fast communi-
various program linkages and conventions and the cation to a program operating in the supervisor
use of the linkage instructions in these situations. state or higher-authority problem state, or even to
a program with the same authority. PROGRAM
BRANCH RELATIVE AND SAVE and BRANCH CALL permits a program to call a program oper-
RELATIVE AND SAVE LONG, which are not men- ating in a different address space. This would
tioned in the remainder of this section, may be normally be used in the situation where the
used in place of BRANCH AND SAVE. authorization index associated with the called
address space had a higher level of authority than
The linkage instructions are provided to permit that of the calling address space. The advantage
System/370 programs to operate with no modifica- of PROGRAM CALL over SUPERVISOR CALL is
tion or only slight modification on ESA/390 in speed, since first-and second-level interruption-
systems and also to provide additional function for handler programs are avoided. It also provides a
those programs which are designed to take possible 2 different entry points. The authori-
advantage of the 31-bit addressing of ESA/390. zation key mask in the entry-table entry permits a
The instructions provide the capability for both old particular entry point to be available to a limited
and new programs to coexist in storage and to subset of the programs in the system. Thus,
communicate with each other. It is assumed that some or all of the authority checking which would
old, unmodified programs operate in the 24-bit otherwise have to be placed in the called program
addressing mode and call, or directly communi- can be eliminated. Return from a routine called
cate with, other programs operating in the 24-bit by PROGRAM CALL is normally accomplished by
addressing mode only. Modified programs means of the PROGRAM TRANSFER instruction;
normally operate in the 24-bit addressing mode however, LOAD PSW may be used if the called
but may call programs which operate in either the routine is in the supervisor state.
24-bit or 31-bit addressing mode. New programs
may be written to operate in either the 24-bit or PROGRAM TRANSFER is provided as the return
31-bit addressing mode, and, in some cases, a instruction for PROGRAM CALL. It is also useful
program may be written such that it can be for calling or transferring to programs with the
invoked in either mode. same authority in another address space.
Although PROGRAM TRANSFER does not save
SUPERVISOR CALL is provided for compatibility the current PASN, the instruction EXTRACT
purposes and also because it provides the sim- PRIMARY ASN may be used to provide the PASN
plest mechanism to call a program which operates for return purposes.
in the supervisor state. It has the advantage over
PROGRAM CALL that no general registers are BRANCH AND SAVE AND SET MODE (BASSM)
disturbed, that only two bytes in storage are is intended to be the principal calling instruction to
required in line, and that a complete change of subroutines outside of an assembler/linkage-editor
Trial Execution for Editing Instructions The instructions controlled by the authorization
and Translate Instruction mechanisms are listed in Figure 5-5 on
For the instructions EDIT, EDIT AND MARK, and page 5-25. The figure also shows additional
TRANSLATE, the portions of the operands that authorization mechanisms that do not control spe-
are actually used in the operation may be estab- cifically semiprivileged instructions; they control
lished in a trial execution for operand accessibility implicit access-register translation (access-register
that is performed before the execution of the translation as part of an instruction making a
instruction is started. This trial execution consists storage reference) and also access-register trans-
in an execution of the instruction in which results lation in the LOAD REAL ADDRESS, TEST
are not stored. If the first operand of TRANS- ACCESS, and TEST PROTECTION instructions
LATE or either operand of EDIT or EDIT AND | and a special form of access-register translation in
MARK is changed by another CPU or by a | the BRANCH IN SUBSPACE GROUP instruction.
channel program, after the initial trial execution but These additional mechanisms (the extended
before completion of execution, the contents of authorization index, ALE sequence number, and
any fields due to be changed by the instruction ASTE sequence number) are described in
are unpredictable. Furthermore, it is unpredictable “Access-Register-Specified Address Spaces” on
whether or not an interruption occurs for an page 5-34.
access exception that was not initially applicable.
Mode Requirements
Most of the semiprivileged instructions can be
Authorization Mechanisms executed only with DAT on. Basic PROGRAM
CALL, and PROGRAM TRANSFER, are valid only
The authorization mechanisms that are described
in the primary-space mode. (Basic PROGRAM
in this section permit the control program to estab-
CALL is the PROGRAM CALL operation when the
lish the degree of function provided to a particular
linkage stack is not used. When the linkage stack
semiprivileged program. The authorization mech-
is used, the PROGRAM CALL operation is called
anisms are intended for use by programs consid-
stacking PROGRAM CALL). MOVE TO
ered to be semiprivileged, that is, programs that
PRIMARY and MOVE TO SECONDARY are valid
are executed in the problem state but which may
only in the primary-space and secondary-space
be authorized to use additional capabilities. With
modes. BRANCH AND STACK, stacking
these authorization controls, a hierarchy of pro-
PROGRAM CALL, PROGRAM CALL FAST, and
grams may be established, with programs at a
PROGRAM RETURN are valid only in the
higher level having a greater degree of privilege or
primary-space and access-register modes.
authority than programs at a lower level. The
EXTRACT STACKED REGISTERS, EXTRACT
range of functions available at each level, and the
STACKED STATE, and MODIFY STACKED
ability to transfer control from a lower to a higher
STATE are valid only in the primary-space,
level, are specified in tables which are managed
access-register, and home-space modes. When a
by the control program. When the linkage stack is
semiprivileged instruction is executed in an invalid
used, a nonhierarchical transfer of control also can
translation mode, a special-operation exception is
be specified.
recognized.
A semiprivileged instruction is one which can be
PROGRAM TRANSFER specifies a new value for
executed in the problem state, but which is subject
the problem-state bit in the PSW. If a program in
to the control of one or more of the authorization
the problem state attempts to execute PROGRAM
mechanisms described in this section. There are
TRANSFER and set the supervisor state, a
26 semiprivileged instructions and also the privi-
privileged-operation exception is recognized. A
leged LOAD ADDRESS SPACE PARAMETERS
privileged-operation exception is also recognized
instruction that are controlled by the authorization
on an attempt to use RESUME PROGRAM, SET
mechanisms. All of these semiprivileged and priv-
ADDRESS SPACE CONTROL, or SET ADDRESS
SPACE CONTROL FAST to set the home-space
mode in the problem state.
The instruction SET SECONDARY ASN with BRANCH AND SET AUTHORITY
space switching, and the instruction PROGRAM BRANCH AND STACK
RETURN when the restored secondary ASN is not BRANCH IN SUBSPACE GROUP
equal to the restored primary ASN, use the EXTRACT STACKED REGISTERS
authorization index to test the secondary-authority EXTRACT STACKED STATE
bit in the authority-table entry to determine if the MODIFY STACKED STATE
address space can be established as a secondary PROGRAM CALL FAST
address space. The tested bit must be one; oth- PROGRAM RETURN
erwise, a secondary-authority exception is recog- TEST ACCESS
nized. Otherwise, a special-operation exception is recog-
nized. The ASF control is examined in both the
The instruction PROGRAM TRANSFER with problem and supervisor states and controls both
space switching uses the authorization index to the space-switching and current-primary forms of
test the primary-authority bit in the authority-table PROGRAM RETURN.
entry to determine if the address space can be
established as a primary address space. The Under certain circumstances when the ASF
tested bit must be one; otherwise, a primary- control is or has been zero, erroneous entries may
authority exception is recognized. exist in the ART-lookaside buffer (ALB), and this
can cause erroneous access-register translation.
The instruction PROGRAM CALL with space A description of the circumstances and of how to
switching causes a new authorization index to be remove the erroneous entries from the ALB
loaded from the ASN-second-table entry, and
Obtaining the Linkage-Table the primary-ASTE origin, bits 1-25 of control reg-
Designation ister 5, and adding 12. The addition cannot cause
When the address-space-function (ASF) control, a carry into bit position 0. All 31 bits of the
bit 15 of control register 0, is zero, the linkage- address are used, regardless of whether the
table designation is the contents of control register current PSW specifies the 24-bit or 31-bit
5. When the ASF control is one, the linkage-table addressing mode.
designation is obtained from bytes 12-15 of the
primary ASN-second-table entry, the starting When the ASF control is one, all four bytes of the
address of which is specified by the contents of linkage-table designation appear to be fetched
control register 5. concurrently from the primary ASTE as observed
by other CPUs. The fetch access is not subject to
When the ASF control is one, the 31-bit real protection. When the storage address which is
address of the linkage-table designation is generated for fetching the linkage-table desig-
obtained by appending six zeros on the right to nation designates a location which is not available
Bit 0 of the linkage-table entry specifies whether The use that is made of the information fetched
the entry table corresponding to the linkage index from the entry-table entry is described in the defi-
is available. This bit is inspected, and, if it is one, nition of the PROGRAM CALL instruction.
an LX-translation exception is recognized.
Recognition of Exceptions during
When no exceptions are recognized in the PC-Number Translation
process of linkage-table lookup, the entry fetched The exceptions which can be encountered during
from the linkage table designates the origin and the PC-number-translation process and their pri-
length of the corresponding entry table. ority are described in the definition of the
PROGRAM CALL instruction.
Programming Note: The linkage-table desig-
Access List
┌─────────────────┐
/ / ASTE for Space 36
├─────────────────┤ ┌─────────────────┐
4│ PBZ ├────│ │
├─────────────────┤ └─────────────────┘
/ / ASTE for Space 25
├─────────────────┤ ┌─────────────────┐
7│ PBO, ALEAX = 5 ├────│ │
├─────────────────┤ └─────────────────┘
/ / ASTE for Space 62
├─────────────────┤ ┌─────────────────┐
9│ PBO, ALEAX = 1 ├────│ │
├─────────────────┤ └─────────────────┘
/ / ASTE for Space 17 Authority Table
├─────────────────┤ ┌─────────────────┐ ┌─────────────────┐
12│ PBO, ALEAX = 5 ├────│ ├────│S bit selected by│
├─────────────────┤ └─────────────────┘ │EAX 1 is one. │
/ / └─────────────────┘
└─────────────────┘
Bit 0 is reserved for a possible future extension Fetch-Only Bit (FO): Bit 6 controls which types
and should be zero. of operand references are permitted to the
address space specified by the access-list entry.
Programming Note: The maximum number of
When bit 6 is zero, both fetch-type and store-type
access-list entries allowed by a format-0 or
references are permitted. When bit 6 is one, only
format-1 access-list designation is 1,024 or 4,096,
fetch-type references are permitted, and an
respectively. There are two access lists available
attempt to store causes a protection exception for
for use at any time. Therefore, if a model imple-
access-list-controlled protection to be recognized
ments the format-0 access-list designation, a
and the operation to be suppressed.
maximum of 2,048 2G-byte address spaces can
be addressable without control-program inter- Private Bit (P): Bit 7, when zero, specifies that
vention, which is a total of 4T bytes; and if a any program is authorized to use the access-list
model implements the format-1 access-list desig- entry in access-register translation. When bit 7 is
nation, a maximum of 8,192 2G-byte address one, authorization is determined as described for
spaces can be addressable without control- bits 16-31.
program intervention, which is a total of 16T bytes.
Access-List-Entry Sequence Number
Access-List Entries (ALESN): Bits 8-15 are compared against the
The effective access list is the dispatchable-unit ALESN in the ALET during access-register trans-
access list if bit 7 of the ALET being translated is lation. Inequality causes an ALE-sequence excep-
zero, or it is the primary-space access list if bit 7 tion to be recognized. It is intended that the
is one. The entry fetched from the effective control program change bits 8-15 each time it real-
access list is 16 bytes in length and has the fol- locates the access-list entry.
lowing format:
Access-List-Entry Authorization Index
┌─┬───┬─┬─┬────────┬────────────────┐ (ALEAX): Bits 16-31 may be used to determine
│ │ │F│ │ │ │
│I│ │O│P│ ALESN │ ALEAX │ whether the program for which access-register
└─┴───┴─┴─┴────────┴────────────────┘ translation is being performed is authorized to use
1 6 7 8 16 31 the access-list entry. The program is authorized if
any of the following conditions is met:
┌───────────────────────────────────┐ 1. Bit 7 is zero.
│ │
└───────────────────────────────────┘ 2. Bits 16-31 are equal to the extended authori-
32 63 zation index (EAX) in control register 8.
The access-list entry is checked for validity and for The principal features of access-register trans-
containing the correct access-list-entry sequence lation, including the effect of the ALB, are shown
number (ALESN). in Figure 5-9 on page 5-50.
Explanation:
┌─┐ Information, which may include the ALD-source origin, ALET, ALO, and EAX, is used to search
│2│ the ALB. This information, along with information from the ALE, ASTE, and ATE, may be
└─┘ placed in the ALB.
Locating the ASN-Second-Table Entry When the private bit is one and the ALEAX is not
The ASN-second-table-entry (ASTE) origin in the equal to the EAX, bits 30, 31, and 60-63 of the
access-list entry is used to locate the ASTE. Bits ASTE must be zeros; otherwise, an
65-89 of the access-list entry, with six zeros ASN-translation-specification exception may be
appended on the right, form the 31-bit real recognized, which would cause the operation to
address of the ASTE. be suppressed. A one value of bit 31 does not
cause an exception to be recognized if the
The 64-byte ASTE is fetched by using the real subspace-group facility is installed and the ASF
address. The fetch of the entry appears to be control is one.
word concurrent as observed by other CPUs, with
the leftmost word fetched first. The order in which When the private bit is one and the ALEAX is not
the remaining words are fetched is unpredictable. equal to the EAX, a process called the extended-
The fetch access is not subject to protection. authorization process is performed. Extended
When the storage address that is generated for authorization uses the EAX to select an entry in
fetching the ASTE refers to a location which is not the authority table designated by the ASTE, and it
available in the configuration, an addressing tests the secondary-authority bit in the selected
exception is recognized, and the operation is sup- entry for being one. The program is authorized if
pressed. the tested bit is one.
┌─┬────────────────────────────────────────┬──────┐ Entry Key Mask: Bits 96-111 are ORed into the
| │ │ ASTE Origin │ │ PSW-key mask in control register 3 when bit 132,
└─┴────────────────────────────────────────┴──────┘
16 186 191 the PSW-key-mask control, is zero, or replace the
PSW-key mask in control register 3 when bit 132
┌─────────────────────────────────────────────────┐ is one, as part of the stacking PROGRAM CALL
│ │ operation. Bits 96-111 are ORed into the
└─────────────────────────────────────────────────┘ PSW-key mask as part of the basic PROGRAM
192 223
CALL operation.
PC Number: In a program-call state entry, bit When the stacking process fetches or stores by
positions 12-31 of bytes 148-151 contain the PC using an address that designates, after translation,
number used by the stacking PROGRAM CALL a location that is not available in the configuration,
instruction that formed the entry. Stacking an addressing exception is recognized, and the
PROGRAM CALL places the PC number in bit operation is suppressed.
positions 12-31 of bytes 148-151, and it places
zeros in bit positions 0-11. Key-controlled protection does not apply to the
accesses made during the stacking process, but
Modifiable Area: Bytes 152-159 are the field page protection and low-address protection do
that is set by MODIFY STACKED STATE. apply. A protection exception causes the opera-
BRANCH AND STACK and stacking PROGRAM tion to be suppressed.
CALL place all zeros in bytes 152-159.
Locating Space for a New Entry
The contents placed in bytes 144-147 by The linkage-stack-entry address in control register
BRANCH AND STACK and stacking PROGRAM 15 is used to locate the current linkage-stack
CALL are unpredictable. Bytes 144-147 are entry. Bits 1-28 of control register 15, with three
reserved for possible future extensions. zeros appended on the right, form the 31-bit home
virtual address of the leftmost byte of the entry
Stacking Process descriptor of the current linkage-stack entry.
grams and is covered in the following sections in An instruction may be prefetched by using a
this chapter. virtual address only when the associated DAT
table entries are attached and valid or when
Instruction Fetching entries which qualify for substitution for the table
entries exist in the TLB. An instruction that has
Instruction fetching consists in fetching the one, been prefetched may be interpreted for execution
two, or three halfwords designated by the instruc- only for the same virtual address for which the
tion address in the current PSW. The immediate instruction was prefetched.
field of an instruction is accessed as part of an
No limit is established on the number of
instruction fetch. If, however, an instruction desig-
instructions which may be prefetched, and multiple
nates a storage operand at the location occupied
copies of the contents of a single storage location
by the instruction itself, the location is accessed
may be fetched. As a result, the instruction exe-
both as an instruction and as a storage operand.
cuted is not necessarily the most recently fetched
The fetch of the target instruction of EXECUTE is
copy. Storing caused by other CPUs and by
considered to be an instruction fetch.
channel programs does not necessarily change
The bytes of an instruction may be fetched piece- the copy of prefetched instructions. However, if a
meal and are not necessarily accessed in a left- non-vector-facility store that is conceptually earlier
to-right direction. The instruction may be fetched is made by the same CPU using the same effec-
multiple times for a single execution; for example, tive address as that by which the instruction is
it may be fetched for testing the addressability of subsequently fetched, and the CPU is in any of
operands or for inspection of PER events, and it the real, primary-space, and secondary-space
may be refetched for actual execution. modes when the the storing instruction is exe-
cuted and is in any of those modes when the sub-
Instructions are not necessarily fetched in the sequent instruction is executed, the updated infor-
sequence in which they are conceptually executed mation is obtained. If the store is caused by a
and are not necessarily fetched each time they vector-facility instruction, if the effective addresses
are executed. In particular, the fetching of an are different, or if the CPU is in the access-
instruction may precede the storage-operand ref- register mode or home-space mode during either
erences for an instruction that is conceptually the storing execution or the execution of the
earlier. The instruction fetch occurs prior to all instruction that is the destination of the store, the
storage-operand references for all instructions that updated information is not necessarily obtained.
are conceptually later. However, the updated information is obtained if
either execution is in the real mode since pre-
When an instruction has two storage operands Store accesses for interruption codes are not nec-
both of which cause fetch references, it is unpre- essarily single-access stores. The store accesses
dictable which operand is fetched first, or how for the external and supervisor-call-interruption
much of one operand is fetched before the other codes appear to occur between the conceptually
operand is fetched. When the two operands previous and conceptually subsequent operations.
overlap, the common locations may be fetched The store accesses for the program-interruption
independently for each operand. codes may precede the storage-operand refer-
ences associated with the instruction which results
When an instruction has two storage operands the in the program interruption.
first of which causes a store and the second a
fetch reference, it is unpredictable how much of | Relation between Storage-Key
the second operand is fetched before the results
| Accesses
are stored. In the case of destructively overlap-
ping operands, the portion of the second operand | As observed by other CPUs, storage-key fetches
which is common to the first is not necessarily | and stores due to instructions that explicitly manip-
fetched from storage. | ulate a storage key (INSERT STORAGE KEY
| EXTENDED, INSERT VIRTUAL STORAGE KEY,
When an instruction has two storage operands the
| RESET REFERENCE BIT EXTENDED, and SET
first of which causes an update reference and the
| STORAGE KEY EXTENDED) are ordered among
second a fetch reference, it is unpredictable which
| themselves and among storage-operand refer-
operand is fetched first, or how much of one
| ences as if the storage-key accesses were them-
operand is fetched before the other operand is
| selves storage-operand fetches and stores,
fetched. Similarly, it is unpredictable how much of
| respectively.
the result is processed before it is returned to
storage. In the case of destructively overlapping | Accesses of the access-control and fetch-
operands, the portion of the second operand | protection bits due to storage-operand references
which is common to the first is not necessarily | are concurrent with the references. Accesses of
fetched from storage. | the reference and change bits due to storage-
| operand references are in no particular order
The independent fetching of a single location for
| within the interval in which they are defined to
each of two operands may affect the program exe-
| occur. (See the description of when the change
cution in the following situation. When the same
| bit is set in “Storage-Key Accesses” on
storage location is designated by two operand
| page 5-84.) However, whether due to an instruc-
addresses of an instruction, and another CPU or a
| tion that explicitly manipulates a storage key or
channel program causes the contents of the
| due to a storage-operand reference, a storage-key
location to change during execution of the instruc-
CPU 1 CPU 2
The interruption mechanism permits the CPU to tion of the type of condition, interruption conditions
change its state as a result of conditions external are grouped into six classes: external,
to the configuration, within the configuration, or input/output, machine check, program, restart, and
within the CPU itself. To permit fast response to supervisor call.
conditions of high priority and immediate recogni-
┌───────────────────┬────────────────────────┬─────┬─────────┬───────┬─────────────┐
│ │ │ │Mask Bits│ │ │
│ │ │ │in Ctrl │ │Execution of │
│ │ │PSW- │Registers│ │Instruction │
│ Source │ Interruption │Mask │ │ ILC │Identified │
│ Identification │ Code │Bits │Reg, Bit│ Set │by Old PSW │
├───────────────────┼──────────────────┬─────┼─────┼─────────┼───────┼─────────────┤
│INPUT/OUTPUT │Locations 184-191 │ │ │ │ │
│ (old PSW 56, │ │ │ │ │ │
│ new PSW 12) │ │ │ │ │ │
│ │ │ │ │ │ │
│I/O-interruption │ │ 6 │ 6, -7$ │ u │unaffected │
│ subclass │ │ │ │ │ │
├───────────────────┼────────────────────────┼─────┼─────────┼───────┼─────────────┤
│RESTART │None │ │ │ │ │
│ (old PSW 8, │ │ │ │ │ │
│ new PSW ) │ │ │ │ │ │
│ │ │ │ │ │ │
│Restart key │ │ │ │ u │unaffected │
└───────────────────┴────────────────────────┴─────┴─────────┴───────┴─────────────┘
Figure 6-1 (Part 3 of 4). Interruption Action
For the ETR and service-signal interruptions, a The priorities for external-interruption requests in
32-bit parameter is associated with the interruption descending order are as follows:
and is stored at real locations 128-131. Bit 5 of
Interrupt key
The subclass-mask bit is in bit position 20 of The subclass-mask bit is in bit position 17 of
control register 0. This bit is initialized to zero. control register 0. This bit is initialized to zero.
An interruption request for an external call is gen- Facilities are provided for holding a separate
erated when the CPU accepts the external-call malfunction-alert request pending in the receiving
order specified by a SIGNAL PROCESSOR CPU for each of the other CPUs in the configura-
instruction addressing this CPU. The instruction tion. Removal of a CPU from the configuration
may have been executed by this CPU or by does not generate a malfunction-alert condition.
another CPU in the configuration. The request is
The subclass-mask bit is in bit position 16 of
preserved and remains pending in the receiving
control register 0. This bit is initialized to zero.
CPU until it is cleared. The pending request is
cleared when it causes an interruption and by
The malfunction-alert condition is indicated by an
CPU reset.
external-interruption code of 1200 hex. The
address of the CPU that generated the condition
Only one external-call request, along with the
is stored at real locations 132-133.
processor address, may be held pending in a CPU
at a time.
Service Signal
The subclass-mask bit is in bit position 18 of
control register 0. This bit is initialized to zero. An interruption request for a service signal is gen-
erated upon the completion of certain
The external-call condition is indicated by an configuration-control and maintenance functions,
external-interruption code of 1202 hex. The such as those initiated by means of the model-
address of the CPU that executed the SIGNAL dependent DIAGNOSE instruction. A 32-bit
PROCESSOR instruction is stored at real parameter is provided with the interruption to
locations 132-133. assist the program in determining the operation for
which the interruption is reported.
Interrupt Key
Service signal is a floating interruption condition
An interruption request for the interrupt key is gen- and is presented to the first CPU in the configura-
erated when the operator activates that key. The tion which can perform the interruption. The inter-
request is preserved and remains pending in the ruption condition is cleared when it causes an
CPU until it is cleared. The pending request is interruption in any one of the CPUs and also by
cleared when it causes an interruption and by subsystem reset.
CPU reset.
Programming Notes:
Program Interruption
1. When the new PSW for a program interruption
Program interruptions are used to report
has a PSW-format error or causes an excep-
exceptions and events which occur during exe-
tion to be recognized in the process of instruc-
cution of the program.
tion fetching, a string of program interruptions
may occur. See “Priority of Interruptions” on
A program interruption causes the old PSW to be
page 6-46 for a description of how such
stored at real locations 40-47 and a new PSW to
strings are terminated.
be fetched from real locations 104-111.
When an arithmetic exception is recognized during When both a specification exception and an
execution of an interruptible vector instruction, a AFP-register data exception apply, it is unpredict-
nonzero exception-extension code is stored in bits able which one is reported.
0-7 of the program-interruption code. This code is
set to a nonzero value only for arithmetic
exceptions occurring during the execution of DXC
vector instructions. For more details, see the pub- (Hex) Data Exception
lication IBM Enterprise Systems Architecture/390
00 Decimal operand
Vector Operations, SA22-7207.
01 AFP register
Data-Exception Code (DXC) 02 BFP instruction
When a data exception causes a program inter- 08 IEEE inexact and truncated
ruption and the basic-floating-point-extensions 0C IEEE inexact and incremented
facility is installed, a data-exception code (DXC) is
10 IEEE underflow, exact
stored at location 147, and zeros are stored at
locations 144-146. The DXC distinguishes 18 IEEE underflow, inexact and truncated
between the various types of data-exception con-
1C IEEE underflow, inexact and incremented
ditions. When the AFP-register (additional
floating-point register) control bit, bit 13 of control 20 IEEE overflow, exact
register 0, is one, the DXC is also placed in the 28 IEEE overflow, inexact and truncated
DXC field of the floating-point-control (FPC) reg-
ister. The DXC field in the FPC register remains 2C IEEE overflow, inexact and incremented
unchanged when any other program exception is 40 IEEE division by zero
reported. The DXC is an 8-bit code indicating the
specific cause of a data exception. The data- 80 IEEE invalid operation
exception codes and data exceptions are shown in
Figure 6-2 and Figure 6-3 on page 6-16. Figure 6-2. Data-Exception Codes (DXC)
For the operands of MOVE PAGE, a page- The unit of operation is nullified, except that when
translation exception is recognized when any of the exception is caused by an expanded-storage
the following is true: data error occurring when MOVE PAGE moves
1. The page-table entry indicated by the page- data between main storage and expanded
index portion of a virtual address is outside storage, the contents of the first-operand location
the page table. are unpredictable.
2. The page-invalid bit is one, and the operand is When the exception occurs during fetching of an
also invalid in expanded storage. If this is instruction, it is unpredictable whether the ILC is 1,
true for both operands, the exception is recog- 2, or 3. When the exception occurs during a ref-
erence to the target of EXECUTE, the ILC is 2.
The instruction-length code is 0, 1, 2, or 3. Code 4. In the problem state, the key value specified
0 is set only if a specification exception is indi- by the rightmost byte of the register desig-
cated concurrently. nated by the R field of the MOVE WITH KEY
instruction corresponds to a zero
The PER event is indicated by setting bit 8 of the PSW-key-mask bit in control register 3.
program-interruption code to one. 5. In the problem state, the key value specified
by the rightmost byte of the register desig-
nated by the R field for the instruction MOVE
TO PRIMARY, MOVE TO SECONDARY, or
For a protected operand location, the instruction- When an interruption occurs, information about the
length code (ILC) is 1, 2, or 3, indicating the virtual address causing the exception is stored at
length of the instruction that caused the reference. real locations 144-147 and conditionally at real
location 160. See “Assigned Storage Locations”
The protection exception is indicated by a on page 3-43 for a detailed description of this
program-interruption code of 0004 hex (or 0084 information.
hex if a concurrent PER event is indicated).
The unit of operation is nullified.
Secondary-Authority Exception
A secondary-authority exception is recognized When the exception occurs during fetching of an
during ASN authorization in SET SECONDARY instruction, it is unpredictable whether the ILC is 1,
ASN with space switching, or during ASN authori- 2, or 3. When the exception occurs during the
zation in PROGRAM RETURN when the restored fetching of the target of EXECUTE, the ILC is 2.
SASN does not equal the restored PASN, when
either: When the exception occurs during a reference to
an operand location, the instruction-length code
1. The authority-table entry indicated by the (ILC) is 1, 2, or 3 and indicates the length of the
authorization index in control register 4 is instruction causing the exception.
beyond the end of the authority table used.
The authority table is the one designated by The segment-translation exception is indicated by
the ASN-second-table entry for the ASN used. a program-interruption code of 0010 hex (or 0090
For PROGRAM RETURN, the ASN is the hex if a concurrent PER event is indicated).
SASN being restored from the linkage-stack
state entry used. Space-Switch Event
2. The secondary-authority bit indicated by the A space-switch event is recognized at the com-
authorization index is zero. pletion of the operation in each of the following
cases:
The ASN used is stored at real locations 146-147,
and real locations 144-145 are set to zeros. 1. The space-switching form of PROGRAM
CALL, PROGRAM CALL FAST, PROGRAM
The operation is nullified. RETURN, or PROGRAM TRANSFER is exe-
cuted and any of the following is true:
The instruction-length code is 1 or 2.
a. The primary space-switch-event-control
bit, bit 0 of control register 1, is one before
The secondary-authority exception is indicated by
the operation.
a program-interruption code of 0025 hex (or 00A5
hex if a concurrent PER event is indicated). b. The primary space-switch-event-control bit
is one after the operation.
Segment-Translation Exception c. A PER event is indicated.
A segment-translation exception is recognized
when either: 2. RESUME PROGRAM, SET ADDRESS
SPACE CONTROL, or SET ADDRESS
1. The segment-table entry indicated by the SPACE CONTROL FAST is executed, the
segment-index portion of a virtual address is CPU is in the home-space mode either before
outside the segment table. or after the operation, but not both before and
2. The segment-invalid bit is one. after the operation, and any of the following is
true:
The exception is recognized as part of the exe-
cution of an instruction that needs the segment- a. The primary space-switch-event-control
table entry in the translation of an instruction or bit, bit 0 of control register 1, is one.
Any access exception is recognized as part of the An access exception due to fetching an instruction
execution of the instruction with which the excep- is indicated when the first instruction halfword
tion is associated. An access exception is not cannot be fetched without encountering the excep-
recognized when the CPU attempts to prefetch tion. When the first halfword of the instruction has
from an unavailable location or detects some other no access exceptions, access exceptions may be
access-exception condition, but a branch instruc- indicated for additional halfwords according to the
tion or an interruption changes the instruction instruction length specified by the first two bits of
sequence such that the instruction is not exe- the instruction; however, when the operation can
cuted. be performed without accessing the second or
third halfwords of the instruction, it is unpredict-
Every instruction can cause an access exception able whether the access exception is indicated for
to be recognized because of instruction fetch. the unused part. Since the indication of access
Additionally, access exceptions associated with exceptions for instruction fetch is common to all
instruction execution may occur because of an instructions, it is not covered in the individual
access to an operand in storage. instruction definitions.
┌──────────────────────────────────────────────────────────────────────────────────┐
│ 1. Specification exception due to any PSW error of the type that causes an │
│ immediate interruption. │
│ │
│ 2. Specification exception due to an odd instruction address in the PSW. │
│ │
│ 3. Access exceptions for first halfword of EXECUTE. │
│ │
│ 4. Access exceptions for second halfword of EXECUTE. │
│ │
│ 5. Specification exception due to target instruction of EXECUTE not being │
│ specified on halfword boundary. │
│ │
│ 6. Access exceptions for first instruction halfword. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B Access exceptions for third instruction halfword. │
│ │
│ 7.C.1 Vector-operation exception. │
│ │
│ 7.C.2 Operation exception. │
│ │
│ 7.C.3 Privileged-operation exception for privileged instructions. │
│ │
│ 7.C.4 Execute exception. │
│ │
│ 7.C.5 Special-operation exception. │
│ │
│ 8.A Specification exception due to conditions other than those included in │
│ 1, 2, and 5 above. │
│ │
│ 8.B Access exceptions for an access to an operand in storage. │
│ │
│ 8.C Access exceptions for any other access to an operand in storage. │
│ │
│ 8.D Data exception. │
│ │
│ 8.E Decimal-divide exception.$ │
│ │
│ 8.F Trace exceptions. │
│ │
│ 9. Events other than PER events, exceptions which result in completion, │
│ and the following exceptions: fixed-point divide, HFP divide, operand, │
│ HFP square root, and unnormalized operand. Either these exceptions and │
│ events are mutually exclusive or their priority is specified in the │
│ corresponding definitions. │
└──────────────────────────────────────────────────────────────────────────────────┘
Figure 6-6 (Part 1 of 2). Priority of Program-Interruption Conditions
This chapter includes all the unprivileged MOVE and TRANSLATE, one operand is replaced
instructions described in this publication other than by new data, and the execution of the operation
the decimal and floating-point instructions. may be affected by the amount of overlap and the
manner in which data is fetched or stored. For
purposes of evaluating the effect of overlapped
Data Format operands, data is considered to be handled one
eight-bit byte at a time. Special rules apply to the
The general instructions treat data as being of four
operands of MOVE LONG and MOVE INVERSE.
types: signed binary integers, unsigned binary
See “Interlocks within a Single Instruction” on
integers, unstructured logical data, and decimal
page 5-80 for how overlap is detected in the
data. Data is treated as decimal by the conver-
access-register mode.
sion, packing, and unpacking instructions.
Decimal data is described in Chapter 8, “Decimal
Instructions.”
Binary-Integer Representation
The general instructions manipulate data which Binary integers are treated as signed or unsigned.
resides in general registers or in storage or is
introduced from the instruction stream. Some In an unsigned binary integer, all bits are used to
general instructions operate on data which resides express the absolute value of the number. When
in the PSW or the TOD clock. two unsigned binary integers of different lengths
are added, the shorter number is considered to be
In a storage-and-storage operation the operand extended on the left with zeros.
fields may be defined in such a way that they
overlap. The effect of this overlap depends upon In some operations, the result is achieved by the
the operation. When the operands remain use of the one's complement of the number. The
unchanged, as in COMPARE or TRANSLATE one's complement of a number is obtained by
AND TEST, overlapping does not affect the exe- inverting each bit of the number, including the
cution of the operation. For instructions such as sign.
For signed binary integers, the leftmost bit repres- number, and a fixed-point-overflow exception is
ents the sign, which is followed by the numeric recognized. An overflow does not result, however,
field. Positive numbers are represented in true when the maximum negative number is comple-
binary notation with the sign bit set to zero. When mented as an intermediate result but the final
the value is zero, all bits are zeros, including the result is within the representable range. An
sign bit. Negative numbers are represented in example of this case is a subtraction of the
two's-complement binary notation with a one in maximum negative number from -1. The product
the sign-bit position. of two maximum negative numbers of a given
length is representable as a positive number of
Specifically, a negative number is represented by double that length.
the two's complement of the positive number of
the same absolute value. The two's complement In discussions of signed binary integers in this
of a number is obtained by forming the one's com- publication, a signed binary integer includes the
plement of the number, adding a value of one in sign bit. Thus, the expression “32-bit signed
the rightmost bit position, allowing a carry into the binary integer” denotes an integer with 31 numeric
sign position, and ignoring any carry out of the bits and a sign bit, and the expression “64-bit
sign position. signed binary integer” denotes an integer with 63
numeric bits and a sign bit.
This number representation can be considered the
rightmost portion of an infinitely long represen- In an arithmetic operation, a carry out of the
tation of the number. When the number is posi- numeric field of a signed binary integer is carried
tive, all bits to the left of the most significant bit of into the sign bit. However, in algebraic left-
the number are zeros. When the number is nega- shifting, the sign bit does not change even if sig-
tive, these bits are ones. Therefore, when a nificant numeric bits are shifted out.
signed operand must be extended with bits on the
left, the extension is achieved by setting these bits Programming Notes:
equal to the sign bit of the operand. 1. An alternate way of forming the two's comple-
ment of a signed binary integer is to invert all
The notation for signed binary integers does not
bits to the left of the rightmost one bit, leaving
include a negative zero. It has a number range in
the rightmost one bit and all zero bits to the
which, for a given length, the set of negative
right of it unchanged.
nonzero numbers is one larger than the set of
positive nonzero numbers. The maximum positive 2. The numeric bits of a signed binary integer
number consists of a sign bit of zero followed by may be considered to represent a positive
all ones, whereas the maximum negative number value, with the sign representing a value of
(the negative number with the greatest absolute either zero or the maximum negative number.
value) consists of a sign bit of one followed by all
zeros.
Binary Arithmetic
A signed binary integer of either sign, except for
zero and the maximum negative number, can be
changed to a number of the same magnitude but
Signed Binary Arithmetic
opposite sign by forming its two's complement.
Forming the two's complement of a number is
Addition and Subtraction
Addition of signed binary integers is performed by
equivalent to subtracting the number from zero.
adding all bits of each operand, including the sign
The two's complement of zero is zero.
bits. When one of the operands is shorter, the
The two's complement of the maximum negative shorter operand is considered to be extended on
number cannot be represented in the same the left to the length of the longer operand by
number of bits. When an operation, such as propagating the sign-bit value.
LOAD COMPLEMENT, attempts to produce the
Subtraction is performed by adding the one's com-
two's complement of the maximum negative
plement of the second operand and a value of one
number, the result is the maximum negative
to the first operand.
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│ADD │AR │RR C │ │ IF │ R │ │1A │
│ADD │A │RX C │ A │ IF │ R │ B│5A │
│ADD HALFWORD │AH │RX C │ A │ IF │ R │ B│4A │
│ADD HALFWORD IMMEDIATE │AHI │RI C IR│ │ IF │ R │ │A7A │
│ADD LOGICAL │ALR │RR C │ │ │ R │ │1E │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│ADD LOGICAL │AL │RX C │ A │ │ R │ B│5E │
| │ADD LOGICAL WITH CARRY │ALCR │RRE C N3│ │ │ R │ │B998│
| │ADD LOGICAL WITH CARRY │ALC │RXE C N3│ A │ │ R │ B│E398│
│AND │NR │RR C │ │ │ R │ │14 │
│AND │N │RX C │ A │ │ R │ B│54 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│AND (character) │NC │SS C │ A │ │ ST│B B│D4 │
│AND (immediate) │NI │SI C │ A │ │ ST│B │94 │
│BRANCH AND LINK │BALR │RR │ │ T │B R │ │5 │
│BRANCH AND LINK │BAL │RX │ │ │B R │ │45 │
│BRANCH AND SAVE │BASR │RR │ │ T │B R │ │D │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│BRANCH AND SAVE │BAS │RX │ │ │B R │ │4D │
│BRANCH AND SAVE AND SET MODE │BASSM│RR │ │ T │B R │ │C │
│BRANCH AND SET MODE │BSM │RR │ │ │B R │ │B │
│BRANCH ON CONDITION │BCR │RR │ │ ¢ │B │ │7 │
│BRANCH ON CONDITION │BC │RX │ │ │B │ │47 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│BRANCH ON COUNT │BCTR │RR │ │ │B R │ │6 │
│BRANCH ON COUNT │BCT │RX │ │ │B R │ │46 │
│BRANCH ON INDEX HIGH │BXH │RS │ │ │B R │ │86 │
│BRANCH ON INDEX LOW OR EQUAL │BXLE │RS │ │ │B R │ │87 │
│BRANCH RELATIVE AND SAVE │BRAS │RI IR│ │ │B R │ │A75 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│BRANCH RELATIVE AND SAVE LONG │BRASL│RIL N3│ │ │B R │ │C5 │
│BRANCH RELATIVE ON CONDITION │BRC │RI IR│ │ │B │ │A74 │
│BRANCH RELATIVE ON CONDITION LONG │BRCL │RIL N3│ │ │B │ │C4 │
│BRANCH RELATIVE ON COUNT │BRCT │RI IR│ │ │B R │ │A76 │
│BRANCH RELATIVE ON INDEX HIGH │BRXH │RSI IR│ │ │B R │ │84 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│BRANCH RELATIVE ON INDEX LOW OR EQ. │BRXLE│RSI IR│ │ │B R │ │85 │
│CHECKSUM │CKSM │RRE C CK│ A SP│ │ R │ R│B241│
| │CIPHER MESSAGE │KM │RRE C MS│ A SP│ GM I1 │ ST│R R│B92E│
| │CIPHER MESSAGE WITH CHAINING │KMC │RRE C MS│ A SP│ GM I1 │ ST│R R│B92F│
│COMPARE │CR │RR C │ │ │ │ │19 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│COMPARE │C │RX C │ A │ │ │ B│59 │
│COMPARE AND FORM CODEWORD │CFC │S C │ A SP│II GM │ R │I1 │B21A│
│COMPARE AND SWAP │CS │RS C │ A SP│ $ │ R ST│ B│BA │
│COMPARE DOUBLE AND SWAP │CDS │RS C │ A SP│ $ │ R ST│ B│BB │
│COMPARE HALFWORD │CH │RX C │ A │ │ │ B│49 │
└────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┘
Figure 7-1 (Part 1 of 7). Summary of General Instructions
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│COMPARE HALFWORD IMMEDIATE │CHI │RI C IR│ │ │ │ │A7E │
│COMPARE LOGICAL │CLR │RR C │ │ │ │ │15 │
│COMPARE LOGICAL │CL │RX C │ A │ │ │ B│55 │
│COMPARE LOGICAL (character) │CLC │SS C │ A │ │ │B B│D5 │
│COMPARE LOGICAL (immediate) │CLI │SI C │ A │ │ │B │95 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│COMPARE LOGICAL CHARS. UNDER MASK │CLM │RS C │ A │ │ │ B│BD │
│COMPARE LOGICAL LONG │CLCL │RR C │ A SP│II │ R │R R│F │
│COMPARE LOGICAL LONG EXTENDED │CLCLE│RS C CM│ A SP│ │ R │R R│A9 │
│COMPARE LOGICAL LONG UNICODE │CLCLU│RSE C E2│ A SP│ │ R │R R│EB8F│
│COMPARE LOGICAL STRING │CLST │RRE C SR│ A SP│ G │ R │R R│B25D│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│COMPARE UNTIL SUBSTRING EQUAL │CUSE │RRE C │ A SP│II GM │ │R R│B257│
| │COMPUTE INTERMEDIATE MESSAGE DIGEST │KIMD │RRE C MS│ A SP│ GM I1 │ ST│ R│B93E│
| │COMPUTE LAST MESSAGE DIGEST │KLMD │RRE C MS│ A SP│ GM I1 │ ST│ R│B93F│
| │COMPUTE MESSAGE AUTHENTICATION CODE │KMAC │RRE C MS│ A SP│ GM I1 │ ST│ R│B91E│
│CONVERT TO BINARY │CVB │RX │ A │Dd IK │ R │ B│4F │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│CONVERT TO DECIMAL │CVD │RX │ A │ │ ST│ B│4E │
│CONVERT UNICODE TO UTF-8 │CUUTF│RRE C ET│ A SP│ │ R ST│R R│B2A6│
│CONVERT UTF-8 TO UNICODE │CUTFU│RRE C ET│ A SP│ │ R ST│R R│B2A7│
│COPY ACCESS │CPYA │RRE │ │ │ │U U│B24D│
│DIVIDE │DR │RR │ SP│ IK │ R │ │1D │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│DIVIDE │D │RX │ A SP│ IK │ R │ B│5D │
│DIVIDE LOGICAL │DLR │RRE N3│ SP│ IK │ R │ │B997│
│DIVIDE LOGICAL │DL │RXE N3│ A SP│ IK │ R │ B│E397│
│EXCLUSIVE OR │XR │RR C │ │ │ R │ │17 │
│EXCLUSIVE OR │X │RX C │ A │ │ R │ B│57 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│EXCLUSIVE OR (character) │XC │SS C │ A │ │ ST│B B│D7 │
│EXCLUSIVE OR (immediate) │XI │SI C │ A │ │ ST│B │97 │
│EXECUTE │EX │RX │ AI SP│ EX │ │ │44 │
│EXTRACT ACCESS │EAR │RRE │ │ │ R │ U│B24F│
│EXTRACT PSW │EPSW │RRE N3│ │ │ R │ │B98D│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│INSERT CHARACTER │IC │RX │ A │ │ R │ B│43 │
│INSERT CHARACTERS UNDER MASK │ICM │RS C │ A │ │ R │ B│BF │
│INSERT PROGRAM MASK │IPM │RRE │ │ │ R │ │B222│
│LOAD │LR │RR │ │ │ R │ │18 │
│LOAD │L │RX │ A │ │ R │ B│58 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│LOAD ACCESS MULTIPLE │LAM │RS │ A SP│ │ │ UB│9A │
│LOAD ADDRESS │LA │RX │ │ │ R │ │41 │
│LOAD ADDRESS EXTENDED │LAE │RX │ │ │ R │U BP│51 │
│LOAD ADDRESS RELATIVE LONG │LARL │RIL N3│ │ │ R │ │C │
│LOAD AND TEST │LTR │RR C │ │ │ R │ │12 │
└────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┘
Figure 7-1 (Part 2 of 7). Summary of General Instructions
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│LOAD COMPLEMENT │LCR │RR C │ │ IF │ R │ │13 │
│LOAD HALFWORD │LH │RX │ A │ │ R │ B│48 │
│LOAD HALFWORD IMMEDIATE │LHI │RI IR│ │ │ R │ │A78 │
│LOAD MULTIPLE │LM │RS │ A │ │ R │ B│98 │
│LOAD NEGATIVE │LNR │RR C │ │ │ R │ │11 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│LOAD POSITIVE │LPR │RR C │ │ IF │ R │ │1 │
│LOAD REVERSED │LRVR │RRE N3│ │ │ R │ │B91F│
│LOAD REVERSED │LRVH │RXE N3│ A │ │ R │ B│E31F│
│LOAD REVERSED │LRV │RXE N3│ A │ │ R │ B│E31E│
│MONITOR CALL │MC │SI │ SP│ MO │ │ │AF │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│MOVE (character) │MVC │SS │ A │ │ ST│B B│D2 │
│MOVE (immediate) │MVI │SI │ A │ │ ST│B │92 │
│MOVE INVERSE │MVCIN│SS │ A │ │ ST│B B│E8 │
│MOVE LONG │MVCL │RR C │ A SP│II │ R ST│R R│E │
│MOVE LONG EXTENDED │MVCLE│RS C CM│ A SP│ │ R ST│R R│A8 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│MOVE LONG UNICODE │MVCLU│RSE C E2│ A SP│ │ R ST│R R│EB8E│
│MOVE NUMERICS │MVN │SS │ A │ │ ST│B B│D1 │
│MOVE PAGE (facility 1) │MVPG │RRE C M1│ A SP│ G │ ST│R R│B254│
│MOVE STRING │MVST │RRE C SR│ A SP│ G │ R ST│R R│B255│
│MOVE WITH OFFSET │MVO │SS │ A │ │ ST│B B│F1 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│MOVE ZONES │MVZ │SS │ A │ │ ST│B B│D3 │
│MULTIPLY │MR │RR │ SP│ │ R │ │1C │
│MULTIPLY │M │RX │ A SP│ │ R │ B│5C │
│MULTIPLY HALFWORD │MH │RX │ A │ │ R │ B│4C │
│MULTIPLY HALFWORD IMMEDIATE │MHI │RI IR│ │ │ R │ │A7C │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│MULTIPLY LOGICAL │MLR │RRE N3│ SP│ │ R │ │B996│
│MULTIPLY LOGICAL │ML │RXE N3│ A SP│ │ R │ B│E396│
│MULTIPLY SINGLE │MSR │RRE IR│ │ │ R │ │B252│
│MULTIPLY SINGLE │MS │RX IR│ A │ │ R │ B│71 │
│OR │OR │RR C │ │ │ R │ │16 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│OR │O │RX C │ A │ │ R │ B│56 │
│OR (character) │OC │SS C │ A │ │ ST│B B│D6 │
│OR (immediate) │OI │SI C │ A │ │ ST│B │96 │
│PACK │PACK │SS │ A │ │ ST│B B│F2 │
│PACK ASCII │PKA │SS E2│ A SP│ │ ST│B B│E9 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│PACK UNICODE │PKU │SS E2│ A SP│ │ ST│B B│E1 │
│PERFORM LOCKED OPERATION │PLO │SS C PL│ A SP│ $ GM │ R ST│ FC│EE │
│ROTATE LEFT SINGLE LOGICAL │RLL │RSE N3│ │ │ R │ │EB1D│
│SEARCH STRING │SRST │RRE C SR│ A SP│ G │ R │ R│B25E│
│SET PROGRAM MASK │SPM │RR L │ │ │ │ │4 │
└────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┘
Figure 7-1 (Part 3 of 7). Summary of General Instructions
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│SHIFT LEFT DOUBLE │SLDA │RS C │ SP│ IF │ R │ │8F │
│SHIFT LEFT DOUBLE LOGICAL │SLDL │RS │ SP│ │ R │ │8D │
│SET ACCESS │SAR │RRE │ │ │ │U │B24E│
│SET ADDRESSING MODE │SAM24│E N3│ SP│ T │ │ │1C│
│SET ADDRESSING MODE │SAM31│E N3│ SP│ T │ │ │1D│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│SHIFT LEFT SINGLE │SLA │RS C │ │ IF │ R │ │8B │
│SHIFT LEFT SINGLE LOGICAL │SLL │RS │ │ │ R │ │89 │
│SHIFT RIGHT DOUBLE │SRDA │RS C │ SP│ │ R │ │8E │
│SHIFT RIGHT DOUBLE LOGICAL │SRDL │RS │ SP│ │ R │ │8C │
│SHIFT RIGHT SINGLE │SRA │RS C │ │ │ R │ │8A │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│SHIFT RIGHT SINGLE LOGICAL │SRL │RS │ │ │ R │ │88 │
│STORE │ST │RX │ A │ │ ST│ B│5 │
│STORE ACCESS MULTIPLE │STAM │RS │ A SP│ │ ST│ UB│9B │
│STORE CHARACTER │STC │RX │ A │ │ ST│ B│42 │
│STORE CHARACTERS UNDER MASK │STCM │RS │ A │ │ ST│ B│BE │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│STORE CLOCK │STCK │S C │ A │ $ │ ST│ B│B25│
│STORE CLOCK EXTENDED │STCKE│S C EK│ A │ $ │ ST│ B│B278│
│STORE HALFWORD │STH │RX │ A │ │ ST│ B│4 │
│STORE MULTIPLE │STM │RS │ A │ │ ST│ B│9 │
│STORE REVERSED │STRVH│RXE N3│ A │ │ ST│ B│E33F│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│STORE REVERSED │STRV │RXE N3│ A │ │ ST│ B│E33E│
│SUBTRACT │SR │RR C │ │ IF │ R │ │1B │
│SUBTRACT │S │RX C │ A │ IF │ R │ B│5B │
│SUBTRACT HALFWORD │SH │RX C │ A │ IF │ R │ B│4B │
│SUBTRACT LOGICAL │SLR │RR C │ │ │ R │ │1F │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│SUBTRACT LOGICAL │SL │RX C │ A │ │ R │ B│5F │
│SUBTRACT LOGICAL WITH BORROW │SLBR │RRE C N3│ │ │ R │ │B999│
│SUBTRACT LOGICAL WITH BORROW │SLB │RXE C N3│ A │ │ R │ B│E399│
│SUPERVISOR CALL │SVC │RR │ │ ¢ │ │ │A │
│TEST ADDRESSING MODE │TAM │E C N3│ │ │ │ │1B│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│TEST AND SET │TS │S C │ A │ $ │ ST│ B│93 │
│TEST UNDER MASK │TM │SI C │ A │ │ │B │91 │
│TEST UNDER MASK HIGH │TMH │RI C IR│ │ │ │ │A7 │
│TEST UNDER MASK LOW │TML │RI C IR│ │ │ │ │A71 │
│TRANSLATE │TR │SS │ A │ │ ST│B B│DC │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│TRANSLATE AND TEST │TRT │SS C │ A │ GM │ R │B B│DD │
│TRANSLATE EXTENDED │TRE │RRE C ET│ A SP│ │ R ST│R R│B2A5│
│TRANSLATE ONE TO ONE │TROO │RRE C E2│ A SP│ GM │ R ST│RM R│B993│
│TRANSLATE ONE TO TWO │TROT │RRE C E2│ A SP│ GM │ R ST│RM R│B992│
│TRANSLATE TWO TO ONE │TRTO │RRE C E2│ A SP│ GM │ R ST│RM R│B991│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│TRANSLATE TWO TO TWO │TRTT │RRE C E2│ A SP│ GM │ R ST│RM R│B99│
│UNPACK │UNPK │SS │ A │ │ ST│B B│F3 │
│UNPACK ASCII │UNPKA│SS C E2│ A SP│ │ ST│B B│EA │
│UNPACK UNICODE │UNPKU│SS C E2│ A SP│ │ ST│B B│E2 │
│UPDATE TREE │UPT │E C │ A SP│II GM │ R ST│I4 │12│
└────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┘
Figure 7-1 (Part 4 of 7). Summary of General Instructions
┌────────────────────────────────────────────────────────────────────────────────────────────────┐
│Explanation: │
│ │
│ ¢ Causes serialization and checkpoint synchronization. │
│ ¢ Causes serialization and checkpoint synchronization when the M and R fields contain all │
│ ones and all zeros, respectively. │
│ $ Causes serialization. │
│ A Access exceptions for logical addresses. │
│ A Access exceptions; not all access exceptions may occur; see instruction description for │
│ details. │
│ AI Access exceptions for instruction address. │
│ B PER branch event. │
│ B B field designates an access register in the access-register mode. │
│ B B field designates an access register in the access-register mode. │
│ BP B field designates an access register when PSW bits 16 and 17 have the value 1. │
│ C Condition code is set. │
│ CK Checksum facility. │
│ CM Compare-and-move-extended facility. │
│ Dd Decimal-operand data exception. │
│ E E instruction format. │
│ E2 Extended-translation facility 2. │
│ EK Extended-TOD-clock facility. │
│ ET Extended-translation facility 1. │
│ EX Execute exception. │
│ FC Designation of access registers depends on the function code of the instruction. │
│ G Instruction execution includes the implied use of general register . │
│ GM Instruction execution includes the implied use of multiple general registers: │
│ General registers and 1 for TRANSLATE ONE TO ONE, TRANSLATE ONE TO TWO, TRANSLATE │
│ TWO TO ONE, and TRANSLATE TWO TO TWO. │
│ General registers 1 and 2 for TRANSLATE AND TEST. │
│ General registers 1, 2, and 3 for COMPARE AND FORM CODEWORD. │
│ General registers and 1 for COMPARE UNTIL SUBSTRING EQUAL and PERFORM LOCKED │
│ OPERATION. │
│ General registers -5 for UPDATE TREE. │
│ IF Fixed-point-overflow exception. │
│ II Interruptible instruction. │
│ IK Fixed-point-divide exception. │
│ IR Immediate-and-relative-instruction facility. │
│ I1 Access register 1 is implicitly designated in the access-register mode. │
│ I4 Access register 4 is implicitly designated in the access-register mode. │
│ L New condition code is loaded. │
│ MO Monitor event. │
| │ MS Message-security assist. │
│ M1 Move-page facility 1, which is a subset of move-page facility 2. │
│ N3 Instruction is added to ESA/39 from z/Architecture. │
│ PL Perform-locked-operation facility. │
│ R PER general-register-alteration event. │
│ R R field designates an access register in the access-register mode. │
│ R R field designates an access register in the access-register mode. │
└────────────────────────────────────────────────────────────────────────────────────────────────┘
Figure 7-1 (Part 6 of 7). Summary of General Instructions
┌────────────────────────────────────────────────────────────────────────────────────────────────┐
│Explanation (Continued): │
│ │
│ R R field designates an access register in the access-register mode. │
│ RI RI instruction format. │
│ RM R field designates an access register in the access-register mode, and access-register 1 │
│ also is used in the access-register mode. │
│ RR RR instruction format. │
│ RRE RRE instruction format. │
│ RS RS instruction format. │
│ RSE RSE instruction format. │
│ RSI RSI instruction format. │
│ RX RX instruction format. │
│ S S instruction format. │
│ SI SI instruction format. │
│ SP Specification exception. │
│ SR String-instruction facility. │
│ SS SS instruction format. │
│ ST PER storage-alteration event. │
│ T Trace exceptions (includes trace table, addressing, and low-address protection). │
│ U R field designates an access register unconditionally. │
│ U R field designates an access register unconditionally. │
│ UB R and R fields designate access registers unconditionally, and B field designates an │
│ access register in the access-register mode. │
└────────────────────────────────────────────────────────────────────────────────────────────────┘
Figure 7-1 (Part 7 of 7). Summary of General Instructions
When there is an overflow, the result is obtained ADD LOGICAL WITH CARRY
by allowing any carry into the sign-bit position and
ignoring any carry out of the sign-bit position, and ALCR R,R [RRE]
condition code 3 is set. If the fixed-point-overflow
┌────────────────┬────────┬────┬────┐
mask is one, a program interruption for fixed-point │ 'B998' │////////│ R │ R │
overflow occurs. └────────────────┴────────┴────┴────┘
16 24 28 31
Resulting Condition Code:
ALC R,D(X,B) [RXE]
0 Result zero; no overflow
1 Result less than zero; no overflow ┌────────┬────┬────┬────┬─/──┬────────┬────────┐
2 Result greater than zero; no overflow │ 'E3' │ R │ X │ B │ D │////////│ '98' │
3 Overflow └────────┴────┴────┴────┴─/──┴────────┴────────┘
8 12 16 2 32 4 47
Program Exceptions:
The second operand and the carry are added to
Access (fetch, operand 2 of AH only)
the first operand, and the sum is placed at the
Fixed-point overflow
first-operand location. The operands, the carry,
Operation (AHI if the immediate-
and the sum are treated as 32-bit unsigned binary
and-relative-instruction facility is not installed)
integers.
Programming Note: An example of the use of
the ADD HALFWORD instruction is given in Resulting Condition Code:
Appendix A, “Number Representation and 0 Result zero; no carry
Instruction-Use Examples.” 1 Result not zero; no carry
2 Result zero; carry
ADD LOGICAL 3 Result not zero; carry
The link information in the 31-bit addressing mode BRANCH AND SAVE
consists of the right half of the PSW, that is, the
addressing-mode bit (always a one) and a 31-bit BASR R,R [RR]
updated instruction address, arranged in the fol-
┌────────┬────┬────┐
lowing format: │ 'D' │ R │ R │
┌─┬───────────────────────────────┐ └────────┴────┴────┘
│1│ Instruction Address │ 8 12 15
└─┴───────────────────────────────┘
1 31 BAS R,D(X,B) [RX]
In the 24-bit addressing mode, the link information Bit 32 of the current PSW, the addressing mode,
consists of a 24-bit instruction address with eight is inserted into the first operand. Subsequently,
zeros appended on the left. In the 31-bit the addressing mode and instruction address in
addressing mode, the link information consists of the current PSW are replaced from the second
a 31-bit address with a one appended on the left. operand. The action associated with an operand
is not performed if the associated R field is zero.
The contents of general register R specify the
new addressing mode and designate the branch The value of bit 32 of the PSW is placed in bit
address; however, when the R field is zero, the position 0 of general register R, and bits 1-31 of
operation is performed without branching and the register remain unchanged; however, when
without setting the addressing mode. the R field is zero, the bit is not inserted, and the
contents of general register 0 are not changed.
When the contents of general register R are
used, bit 0 of the register specifies the new The contents of general register R specify the
addressing mode and replaces bit 32 of the new addressing mode and designate the branch
current PSW, and the branch address is gener- address; however, when the R field is zero, the
ated from the contents of the register under the operation is performed without branching and
control of the new addressing mode. The new without setting the addressing mode.
value for the PSW is computed before general
register R is changed. When the contents of general register R are
used, bit 0 of the register specifies the new
Condition Code: The code remains unchanged. addressing mode and replaces bit 32 of the
current PSW, and the branch address is gener-
Program Exceptions: ated from the contents of the register under the
control of the new addressing mode. The new
Trace (R field nonzero)
value for the PSW is computed before general
register R is changed.
the same as in operand-address specification. ered as either signed or unsigned binary inte-
For branch instructions in the RX format, the gers since the result of a binary subtraction is
branch address is the address specified by the same in both cases.
X, B, and D; in the RR format, the branch
3. An initial count of one results in zero, and no
address is contained in the register desig-
branching takes place; an initial count of zero
nated by R. For operands, the address
results in -1 and causes branching to be per-
specified by X, B, and D is the operand
formed; an initial count of -1 results in -2 and
address, but the register designated by R
causes branching to be performed; and so on.
contains the operand, not the operand
In a loop, branching takes place each time the
address.
instruction is executed until the result is again
zero. Note that, because of the number
BRANCH ON COUNT range, an initial count of -2 results in a posi-
tive value of 2 - 1.
BCTR R,R [RR]
4. Counting is performed without branching when
┌────────┬────┬────┐ the R field in the RR format contains zero.
│ '6' │ R │ R │
└────────┴────┴────┘
8 12 15
BRANCH ON INDEX HIGH
BCT R,D(X,B) [RX] BXH R,R,D(B) [RS]
┌────────┬────┬────┬────┬────────────┐ ┌────────┬────┬────┬────┬────────────┐
│ '46' │ R │ X │ B │ D │ │ '86' │ R │ R │ B │ D │
└────────┴────┴────┴────┴────────────┘ └────────┴────┴────┴────┴────────────┘
8 12 16 2 31 8 12 16 2 31
In the RX format, the second-operand address is An increment is added to the first operand, and
used as the branch address. In the RR format, the sum is compared with a compare value. The
the contents of general register R are used to result of the comparison determines whether
generate the branch address; however, when the branching occurs. Subsequently, the sum is
R field is zero, the operation is performed without placed at the first-operand location. The second-
branching. The branch address is computed operand address is used as a branch address.
before general register R is changed. The R field designates registers containing the
increment and the compare value.
Condition Code: The code remains unchanged.
For BRANCH ON INDEX HIGH, when the sum is
Program Exceptions: None. high, the instruction address in the current PSW is
replaced by the branch address. When the sum is
Programming Notes: low or equal, normal instruction sequencing pro-
ceeds with the updated instruction address.
1. An example of the use of the BRANCH ON
COUNT instruction is given in Appendix A, For BRANCH ON INDEX LOW OR EQUAL, when
“Number Representation and Instruction-Use the sum is low or equal, the instruction address in
Examples.” the current PSW is replaced by the branch
2. The first operand and result can be consid- address. When the sum is high, normal instruc-
tion sequencing proceeds with the updated cannot be represented in that format, but -2.
instruction address. The instruction does not provide an indication
of such overflow. Consequently, some
When the R field is even, it designates a pair of common looping techniques based on the use
registers; the contents of the even and odd regis- of these instructions do not work when a data
ters of the pair are used as the increment and the area ends at address 2 - 1. This problem is
compare value, respectively. When the R field is illustrated in a BRANCH ON INDEX LOW OR
odd, it designates a single register, the contents of EQUAL example in Appendix A, “Number
which are used as both the increment and the Representation and Instruction-Use
compare value. Examples.”
┌────────┬────┬────┬──────────/──────────┐
Condition Code: The code remains unchanged. │ 'C' │ R │'5' │ I │
└────────┴────┴────┴──────────/──────────┘
Program Exceptions: None. 8 12 16 47
Programming Notes:
Bits 32-63 of the current PSW, including the
1. Several examples of the use of the BRANCH updated instruction address, are saved as link
ON INDEX HIGH and BRANCH ON INDEX information at the first-operand location. Subse-
LOW OR EQUAL instructions are given in quently, the instruction address is replaced by the
Appendix A, “Number Representation and branch address.
Instruction-Use Examples.”
In the 24-bit addressing mode, the link information
2. The word “index” in the names of these
consists of a 24-bit instruction address with eight
instructions indicates that one of the major
zeros appended on the left. In the 31-bit
purposes is the incrementing and testing of an
addressing mode, the link information consists of
index value. The increment, being a signed
a 31-bit address with a one appended on the left.
binary integer, may be used to increase or
decrease the value in general register R by The contents of the I field are a signed binary
an arbitrary amount. integer specifying the number of halfwords that is
3. Care must be taken in the 31-bit addressing added to the address of the instruction to generate
mode when a data area in storage is at the the branch address.
rightmost end of an address space and a
BRANCH ON INDEX HIGH or BRANCH ON Condition Code: The code remains unchanged.
INDEX LOW OR EQUAL instruction is used to
step upward through the data. Since the addi- Program Exceptions:
tion and comparison operations performed Operation (if the immediate-
during the execution of these instructions treat and-relative-instruction facility is not installed,
the operands as 32-bit signed binary integers, BRAS only; if z/Architecture is not installed,
the value following 2 - 1 is not 2, which BRASL only)
3. An initial count of one results in zero, and no For BRANCH RELATIVE ON INDEX LOW OR
branching takes place; an initial count of zero EQUAL, when the sum is low or equal, the
results in -1 and causes branching to be exe- instruction address in the current PSW is replaced
cuted; an initial count of -1 results in -2 and by the branch address. When the sum is high,
causes branching to be executed; and so on. normal instruction sequencing proceeds with the
In a loop, branching takes place each time the updated instruction address.
instruction is executed until the result is again
zero. Note that, because of the number When the R field is even, it designates a pair of
range, an initial count of -2 results in a posi- registers; the contents of the even and odd regis-
tive value of 2 - 1. ters of the pair are used as the increment and the
compare value, respectively. When the R field is instruction does not provide an indication of
odd, it designates a single register, the contents of such overflow. Consequently, some common
which are used as both the increment and the looping techniques based on the use of these
compare value. instructions do not work when a data area
ends at address 2 - 1. This problem is illus-
For purposes of the addition and comparison, all trated in a BRANCH ON INDEX LOW OR
operands and results are treated as 32-bit signed EQUAL example in Appendix A.
binary integers. Overflow caused by the addition
4. When the instruction is the target of
is ignored.
EXECUTE, the branch is relative to the target
The original contents of the compare-value reg- address; see “Branch-Address Generation” on
ister are used as the compare value even when page 5-9.
that register is also specified to be the first-
operand location. CHECKSUM
The sum is placed at the first-operand location, CKSM R,R [RRE]
regardless of whether the branch is taken. ┌────────────────┬────────┬────┬────┐
│ 'B241' │////////│ R │ R │
Condition Code: The code remains unchanged. └────────────────┴────────┴────┴────┘
16 24 28 31
Program Exceptions:
Operation (if the immediate- Successive four-byte elements of the second
and-relative-instruction facility is not installed) operand are added to the first operand in general
register R to form a 32-bit checksum in the reg-
Programming Notes: ister. The first operand and the four-byte ele-
ments are treated as 32-bit unsigned binary inte-
1. The operations are the same as those of the gers. After each addition of an element, a carry
BRANCH ON INDEX HIGH and BRANCH ON out of bit position 0 of the first operand is added to
INDEX LOW OR EQUAL instructions except bit position 31 of the first operand. If the second
for the means of specifying the branch operand is not a multiple of four bytes, its last
address. Several examples of the use of one, two, or three bytes are treated as appended
BRANCH ON INDEX HIGH and BRANCH ON on the right with the number of all-zeros bytes
INDEX LOW OR EQUAL are given in needed to form a four-byte element. The four-
Appendix A. byte elements are added to the first operand until
2. The word “index” in the names of these either the entire second operand or a
instructions indicates that one of the major CPU-determined amount of the second operand
purposes is the incrementing and testing of an has been processed. The result is indicated in the
index value. The increment, being a signed condition code.
binary integer, may be used to increase or
decrease the value in general register R by The R field designates an even-odd pair of
an arbitrary amount. general registers and must designate an even-
numbered register; otherwise, a specification
3. Care must be taken in the 31-bit addressing exception is recognized.
mode when a data area in storage is at the
rightmost end of an address space and a The location of the leftmost byte of the second
BRANCH RELATIVE ON INDEX HIGH or operand is specified by the contents of the R
BRANCH RELATIVE ON INDEX LOW OR general register. The number of bytes in the
EQUAL instruction is used to step upward second-operand location is specified by the 32-bit
through the data. Since the addition and com- unsigned binary integer in the R + 1 general
parison operations performed during the exe- register.
cution of these instructions treat the operands
as 32-bit signed binary integers, the value fol- The handling of the address in general register R
lowing 2 - 1 is not 2, which cannot be is dependent on the addressing mode. In the
represented in that format, but -2. The 24-bit addressing mode, the contents of bit posi-
tions 8-31 of general register R constitute the is four bytes or the number of bytes specified in
address, and the contents of bit positions 0-7 are the R + 1 general register, whichever is smaller.
ignored. In the 31-bit addressing mode, the con-
tents of bit positions 1-31 of general register R At the completion of the operation, the leftmost
constitute the address, and the contents of bit bits which are not part of the address in general
position 0 are ignored. register R may be set to zeros or may remain
unchanged, even when the initial length in register
The addition of second-operand four-byte ele- R + 1 is zero.
ments to the first operand proceeds left to right,
four-byte element by four-byte element, and ends When the R register is the same register as the
as soon as (1) the entire second operand has R or R + 1 register, the results are unpredict-
been processed or (2) a lesser CPU-determined able.
amount of the second operand has been proc-
essed. In either case, the result in general reg- Access exceptions for the portion of the second
ister R is a 32-bit checksum for the part of the operand to the right of the last byte processed
second operand that has been processed. When may or may not be recognized. For a second
the second operand is not a multiple of four bytes, operand longer than 4K bytes, access exceptions
the final second-operand bytes in excess of a mul- are not recognized for locations more than 4K
tiple of four are conceptually appended on the bytes beyond the last byte processed.
right with an appropriate number of all-zeros bytes
to form the final four-byte element. Access exceptions are not recognized if the R
field is odd. When the length of the second
If the operation ends because the entire second operand is zero, no access exceptions are recog-
operand has been processed, the condition code nized.
is set to 0. If the operation ends because a lesser
CPU-determined amount of the second operand Resulting Condition Code:
has been processed, the condition code is set to 0 Entire second operand processed
3. When the operation is to end with a setting of 1 --
condition code 3, any carry out of bit position 0 of 2 --
the first operand is added to bit position 31 of the 3 CPU-determined amount of second operand
first operand before the operation ends. processed
instruction. The contents of the R register | hash collisions, and (b) a value that is not too
are represented as A,B, meaning the value A | close to a power of two. Following the
in bit positions 0-15 and the value B in bit | DIVIDE (D) instruction, the remainder in reg-
positions 16-31. The value C is a carry from | ister 0 represents the resulting hash value.
A + B. Note that register R + 1 is known to
contain all zeros when CHECKSUM has set | SR 1,1 Zero accumulator
| LA 2,KEY Point to string
condition code 0.
| LA 3,L'KEY Load string length
| LOOP CKSM 1,2 Compute checksum
Contents Contents | BNZ LOOP Repeat if not done
Program of R2 of R2+1 | SR , Zero for divide
| D ,SIZE Compute hash value
LR R2,R1 A,B , | ...
SRDL R2,16 ,A B, | KEY DS CL64 String to be hashed
ALR R2,R2+1 B,A B, | SIZE DS F Size of hash table
ALR R2,R1 A+B+C,A+B B,
SRL R2,16 ,A+B+C B,
4. In the access-register mode, access register 0
| 3. The CHECKSUM instruction may be used in designates the primary address space regard-
| computing hash values as illustrated in the fol- less of the contents of access register 0.
| lowing programming example. The variable 5. The storage-operand references of
| KEY contains a string to be mapped into a CHECKSUM may be multiple-access refer-
| slot in a hash table. The variable SIZE is a ences. (See “Storage-Operand Consistency”
| prime number designating the size of the hash on page 5-87.)
| table. The value of SIZE is determined by
6. Figure 7-2 on page 7-25 contains a summary
| (a) the number of strings to be hashed into
of the operation.
| the table divided by the acceptable number of
┌───────────────────────────────────────────────┐
│Contents of R1 ── CHECKSUM │
│ │
│Address in R2 ── ADR, contents of R2+1 ── LEN│
└─────────────────┬─────────────────────────────┘
│
┌───────────────────│ Note: All addends are unsigned binary integers
│
│ ┌────────┐ No ┌─────────────────────────────────┐
│ │LEN >= 4├─────────────────────│LEN ── INC │
│ └────┬───┘ │ │
│ │ Yes │INC bytes at ADR followed by │
│ │4-INC all-zeros bytes ── ELEMENT│
│ ┌──────────────────────────┐ └────────────────┬────────────────┘
│ │4 ── INC │ │
│ │ │ │
│ │4 bytes at ADR ── ELEMENT│ │
│ └────────────┬─────────────┘ │
│ │ │
│ │──────────────────────────────────────────┘
│
│ ┌───────────────────────────────┐
│ │CHECKSUM + ELEMENT ── CHECKSUM│
│ └──────────────┬────────────────┘
│ │
│
│ ┌───────────────────┐ Yes ┌─────────────────────────┐
│ │Carry from addition├────│CHECKSUM + 1 ── CHECKSUM│
│ └─────────┬─────────┘ └────────────┬────────────┘
│ │ No │
│ │───────────────────────────┘
│
│ ┌─────────────────────────────────────┐
│ │ADR + INC ── ADR, LEN - INC ── LEN │
│ └──────────────┬──────────────────────┘
│ │
│
│ ┌─────────────────────────┐
│ │LEN = or CPU-determined│
│ │reason to end operation │
│ └────┬───────┬────────────┘
│ │ No │ Yes
└────────────┘ │
┌────────────────────────┐
│CHECKSUM ── R1 │
│ │
│ADR ── R2, LEN ── R2+1│
└───────────┬────────────┘
│
┌───────┐ No
│LEN = ├───────────────────────┐
└───┬───┘ │
│ Yes │
┌────────────────────┐ ┌────────────────────┐
│Set condition code │ │Set condition code 3│
└─────────┬──────────┘ └─────────┬──────────┘
│ │
End operation End operation
Figure 7-2. Execution of CHECKSUM
| CIPHER MESSAGE (KM) | Figure 7-3. Function Codes for CIPHER MESSAGE
| The R field designates a general register and | ands, respectively, and the contents of bit posi-
| must designate an even-numbered register; other- | tions 0-7 are ignored; bits 8-31 of the updated
| wise, a specification exception is recognized. | addresses replace the corresponding bits in
| general registers R and R, carries out of bit
| The R field designates an even-odd pair of | position 8 of the updated address are ignored, and
| general registers and must designate an even- | the contents of bit positions 0-7 of general regis-
| numbered register; otherwise, a specification | ters R and R are set to zeros. In the 31-bit
| exception is recognized. | addressing mode, the contents of bit positions
| 1-31 of general registers R and R constitute the
| The location of the leftmost byte of the first and | addresses of the first and second operands,
| second operands is specified by the contents of | respectively, and the content of bit position 0 is
| the R and R general registers, respectively. | ignored; bits 1-31 of the updated addresses
| The number of bytes in the second-operand | replace the corresponding bits in general registers
| location is specified in general register R + 1. | R and R, carries out of bit position 1 of the
| The first operand is the same length as the | updated address are ignored, and the content of
| second operand. | bit position 0 of general registers R and R is set
| to zero.
| As part of the operation, the addresses in general
| registers R and R are incremented by the | In both the 24-bit and the 31-bit addressing
| number of bytes processed, and the length in | modes, the contents of bit positions 0-31 of
| general register R + 1 is decremented by the | general register R + 1 form a 32-bit unsigned
| same number. The formation and updating of the | binary integer which specifies the number of bytes
| addresses and length is dependent on the | in the first and second operands; and the updated
| addressing mode. | value replaces the contents of bit positions 0-31 of
| general register R + 1.
| In the 24-bit addressing mode, the contents of bit
| positions 8-31 of general registers R and R con- | Figure 7-5 shows the contents of the general reg-
| stitute the addresses of the first and second oper- | isters just described.
| ┌────────────────────────┬─┬───────┐ ┌────────────────────────┬─┬───────┐
| GR │////////////////////////│M│ FC │ │////////////////////////│M│ FC │
| └────────────────────────┴─┴───────┘ └────────────────────────┴─┴───────┘
| 24 31 24 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| GR1 │////////│ Parameter-Block Address │ │/│ Parameter-Block Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| R │////////│ First-Operand Address │ │/│ First-Operand Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| R │////////│ Second-Operand Address │ │/│ Second-Operand Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌──────────────────────────────────┐ ┌──────────────────────────────────┐
| R + 1 │ Second-Operand Length │ │ Second-Operand Length │
| └──────────────────────────────────┘ └──────────────────────────────────┘
| 31 31
| In the access-register mode, access registers 1, | are not accessed, general registers R, R, and
| R, and R specify the address spaces containing | R + 1 are not changed, and condition code 0 is
| the parameter block, first, and second operands, | set.
| respectively.
| When the contents of the R and R fields are the
| The result is obtained as if processing starts at the | same, the contents of the designated registers are
| left end of both the first and second operands and | incremented only by the number of bytes proc-
| proceeds to the right, block by block. The opera- | essed, not by twice the number of bytes proc-
| tion is ended when the number of bytes in the | essed.
| second operand as specified in general register
| R + 1 have been processed and placed at the | As observed by other CPUs and channel pro-
| first-operand location (called normal completion) or | grams, references to the parameter block and
| when a CPU-determined number of blocks that is | storage operands may be multiple-access refer-
| less than the length of the second operand have | ences, accesses to these storage locations are
| been processed (called partial completion). The | not necessarily block-concurrent, and the
| CPU-determined number of blocks depends on | sequence of these accesses or references is
| the model, and may be a different number each | undefined.
| time the instruction is executed. The
| CPU-determined number of blocks is usually | In certain unusual situations, instruction execution
| nonzero. In certain unusual situations, this | may complete by setting condition code 3 without
| number may be zero, and condition code 3 may | updating the registers and chaining value to reflect
| be set with no progress. However, the CPU pro- | the last unit of the first and second operands proc-
| tects against endless reoccurrence of this no- | essed. The size of the unit processed in this case
| progress case. | depends on the situation and the model, but is
| limited such that the portion of the first and
| The results in the first-operand location and the | second operands which have been processed and
| chaining-value field are unpredictable if any of the | not reported do not overlap in storage. In all
| following situations occur: | cases, change bits are set and PER storage-
| alteration events are reported, when applicable,
| 1. The cryptographic-key field overlaps any
| for all first-operand locations processed.
| portion of the first operand.
| 2. The chaining-value field overlaps any portion | Access exceptions may be reported for a larger
| of the first operand or the second operand. | portion of an operand than is processed in a
| single execution of the instruction; however,
| 3. The first and second operands overlap
| access exceptions are not recognized for locations
| destructively. Operands are said to overlap
| beyond the length of an operand nor for locations
| destructively when the first-operand location
| more than 4K bytes beyond the current location
| would be used as a source after data would
| being processed.
| have been moved into it, assuming processing
| to be performed from left to right and one byte | Symbols Used in Function Descriptions
| at a time.
| The following symbols are used in the subsequent
| When the operation ends due to normal com- | description of the CIPHER MESSAGE and
| pletion, condition code 0 is set and the resulting | CIPHER MESSAGE WITH CHAINING functions.
| value in R + 1 is zero. When the operation | For data-encryption-algorithm (DEA) functions, the
| ends due to partial completion, condition code 3 is | DEA-key-parity bit in each byte of the DEA key is
| set and the resulting value in R + 1 is nonzero. | ignored, and the operation proceeds normally,
| regardless of the DEA-key parity of the key.
| When a storage-alteration PER event is recog-
| Further description of the data-encryption algo-
| nized, fewer than 4K additional bytes are stored
| rithm may be found in Data Encryption Algorithm,
| into the first-operand locations before the event is
| ANSI-X3.92.1981, American National Standard for
| reported.
| Information Systems.
| When the second-operand length is initially zero,
| the parameter block, first, and second operands
| C = A XOR B | The parameter block used for the function has the
| following format:
| Figure 7-6. Symbol For Bit-Wise Exclusive Or
| ┌────────────────────────┐
| │ Cryptographic Key (K) │
| K <8> P <8> K <8> C <8> | └────────────────────────┘
| │ │ | 63
| │ ┌───┐ │ ┌───┐
| └─────│DEA│ └─────│DEA│ | Figure 7-9. Parameter Block for KM-DEA
| │ e │ │ d │
| └─┬─┘ └─┬─┘
| | When the modifier bit in general register 0 is zero,
| C <8> P <8> | an encipher operation is performed. The 8-byte
| Symbol for DEA Symbol for DEA | plaintext blocks (P1, P2, ..., Pn) in operand 2 are
| Encryption Decryption | enciphered using the DEA algorithm with the
| 64-bit cryptographic key in the parameter block.
| Symbol Explanation
| <n> Length of item in bytes | Each plaintext block is independently enciphered;
| C Ciphertext | that is, the encipher operation is performed
| K Key value
| P Plaintext | without chaining. The ciphertext blocks (C1, C2,
| ..., Cn) are stored in operand 1. The operation is
| Figure 7-7. Symbols for DEA Encryption and | shown in the following figure:
| Decryption
| Parameter
| KM-Query (KM Function Code 0) | Block ┌─────────────┐
| in | K <8> │
| Storage └──────┬──────┘
|
| The locations of the operands and addresses | K
| used by the instruction are as shown in Figure 7-5
| Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐
| on page 7-27. | in │ P1 <8> │ P2 <8> │ P3 <8> │ │ Pn <8> │
| Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘
|
| The parameter block used for the function has the | ┌───┐ ┌───┐ ┌───┐ ┌───┐
| K ─│DEA│ K ─│DEA│ K ─│DEA│ K ─│DEA│
| following format: | │ e │ │ e │ │ e │ │ e │
| └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘
|
| Op 1 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐
| ┌────────────────────────┐ | in │ C1 <8> │ C2 <8> │ C3 <8> │ │ Cn <8> │
| │ │ | Storage └─────────────┴─────────────┴─────────────┴/┴─────────────┘
| ├ Status Word ┤
| 8 │ │ | Figure 7-10. KM-DEA Encipher Operation
| └────────────────────────┘
| 63 | When the modifier bit in general register 0 is one,
| Figure 7-8. Parameter Block for KM-Query | a decipher operation is performed. The 8-byte
| ciphertext blocks (C1, C2, ..., Cn) in operand 2 are
| A 128-bit status word is stored in the parameter | deciphered using the DEA algorithm with the
| block. Bits 0-127 of this field correspond to func- | 64-bit cryptographic key in the parameter block.
| tion codes 0-127, respectively, of the CIPHER | Each ciphertext block is independently deciphered;
| MESSAGE instruction. When a bit is one, the cor- | that is, the decipher operation is performed
| responding function is installed; otherwise, the | without chaining. The plaintext blocks (P1, P2, ...,
| function is not installed. | Pn) are stored in operand 1. The operation is
| shown in the following figure:
| Condition code 0 is set when execution of the
| KM-Query function completes; condition code 3 is
| not applicable to this function.
| Parameter | Parameter
| Block ┌─────────────┐ | Block ┌─────────────┬─────────────┐
| in | K <8> │ | in | K1 <8> │ K2 <8> │
| Storage └──────┬──────┘ | Storage └──────┬──────┴──────┬──────┘
| |
| K | K1 K2
| Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐ | Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐
| in │ C1 <8> │ C2 <8> │ C3 <8> │ │ Cn <8> │ | in │ P1 <8> │ P2 <8> │ P3 <8> │ │ Pn <8> │
| Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘ | Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘
| |
| ┌───┐ ┌───┐ ┌───┐ ┌───┐ | ┌───┐ ┌───┐ ┌───┐ ┌───┐
| K ─│DEA│ K ─│DEA│ K ─│DEA│ K ─│DEA│ | K1 ─│DEA│ K1 ─│DEA│ K1 ─│DEA│ K1 ─│DEA│
| │ d │ │ d │ │ d │ │ d │ | │ e │ │ e │ │ e │ │ e │
| └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘ | └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘
| |
| Op 1 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐ | ┌───┐ ┌───┐ ┌───┐ ┌───┐
| in │ P1 <8> │ P2 <8> │ P3 <8> │ │ Pn <8> │ | K2 ─│DEA│ K2 ─│DEA│ K2 ─│DEA│ K2 ─│DEA│
| Storage └─────────────┴─────────────┴─────────────┴/┴─────────────┘ | │ d │ │ d │ │ d │ │ d │
| └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘
|
| Figure 7-11. KM-DEA Decipher Operation | ┌───┐ ┌───┐ ┌───┐ ┌───┐
| K1 ─│DEA│ K1 ─│DEA│ K1 ─│DEA│ K1 ─│DEA│
| │ e │ │ e │ │ e │ │ e │
| └─┬─┘ └─┬─┘ └─┬─┘ └─┬─┘
| KM-TDEA-128 (KM Function Code 2) |
| Op 1 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐
| in │ C1 <8> │ C2 <8> │ C3 <8> │ │ Cn <8> │
| Storage └─────────────┴─────────────┴─────────────┴/┴─────────────┘
| The locations of the operands and addresses
| used by the instruction are as shown in Figure 7-5 | Figure 7-13. KM-TDEA-128 Encipher Operation
| on page 7-27.
| When the modifier bit in general register 0 is one,
| The parameter block used for the function has the | a decipher operation is performed. The 8-byte
| following format: | ciphertext blocks (C1, C2, ..., Cn) in operand 2 are
| deciphered using the TDEA algorithm with the two
| ┌────────────────────────┐
| │Cryptographic Key 1 (K1)│ | 64-bit cryptographic keys in the parameter block.
| ├────────────────────────┤ | Each ciphertext block is independently deciphered;
| 8 │Cryptographic Key 2 (K2)│ | that is, the decipher operation is performed
| └────────────────────────┘ | without chaining. The plaintext blocks (P1, P2, ...,
| 63 | Pn) are stored in operand 1. The operation is
| Figure 7-12. Parameter Block for KM-TDEA-128 | shown in the following figure:
| When the modifier bit in general register 0 is one, | Condition code 0 is set when execution of the
| a decipher operation is performed. The 8-byte | KMC-Query function completes; condition code 3
| ciphertext blocks (C1, C2, ..., Cn) in operand 2 are | is not applicable to this function.
| deciphered using the TDEA algorithm with the
| three 64-bit cryptographic keys in the parameter | KMC-DEA (KMC Function Code 1)
| block. Each ciphertext block is independently
| deciphered; that is, the decipher operation is per- | The locations of the operands and addresses
| formed without chaining. The plaintext blocks (P1, | used by the instruction are as shown in Figure 7-5
| P2, ..., Pn) are stored in operand 1. The opera- | on page 7-27.
| tion is shown in the following figure:
| The parameter block used for the function has the
| following format:
| Figure 7-20. KMC-DEA Encipher Operation | When the modifier bit in general register 0 is zero,
| an encipher operation is performed. The 8-byte
| When the modifier bit in general register 0 is one,
| plaintext blocks (P1, P2, ..., Pn) in operand 2 are
| a decipher operation is performed. The 8-byte
| enciphered using the TDEA algorithm with the two
| ciphertext blocks (C1, C2, ..., Cn) in operand 2 are
| 64-bit cryptographic keys and the 64-bit chaining
| deciphered using the DEA algorithm with the
| value in the parameter block.
| 64-bit cryptographic key and the 64-bit chaining
| value in the parameter block. | The chaining value, called the initial chaining
| value (ICV), for deriving the first ciphertext block is
| The chaining value, called the initial chaining
| the chaining value in the parameter block; the
| value (ICV), for deriving the first plaintext block is
| chaining value for deriving each subsequent
| in the parameter block; the chaining value for
| ciphertext block is the corresponding previous
| deriving each subsequent plaintext block is the
| Program Exceptions:
| Access (fetch, operand 2 and cryptographic
| key; store, operand 1; fetch and store,
| chaining value)
| Operation (if the message-security assist is
| not installed)
| Specification
| ┌───────────────────────────────────────────────────────────────────────┐
| │ 1.-6. Exceptions with the same priority as the priority of program- │
| │ interruption conditions for the general case. │
| │ │
| │ 7.A Access exceptions for second instruction halfword. │
| │ │
| │ 7.B Operation exception. │
| │ │
| │ 8. Specification exception due to invalid function code │
| │ or invalid register number. │
| │ │
| │ 9. Specification exception due to invalid operand length. │
| │ │
| │ 1. Condition code due to second-operand length originally zero. │
| │ │
| │ 11. Access exceptions for an access to the parameter block, first, │
| │ or second operand. │
| │ │
| │ 12. Condition code due to normal completion (second-operand │
| │ length originally nonzero, but stepped to zero). │
| │ │
| │ 13. Condition code 3 due to partial completion (second-operand │
| │ length still nonzero). │
| └───────────────────────────────────────────────────────────────────────┘
| Figure 7-28. Priority of Execution: KM and KMC
┌────────────────┬────┬────────────┐
If the index is less than or equal to the index limit,
│ 'B21A' │ B │ D │ the index is applied to the first-operand and third-
└────────────────┴────┴────────────┘ operand base addresses to locate the current pair
16 2 31 of halfwords to be compared. The index, with 16
leftmost zeros appended, and the contents of
General register 2 contains an index, which is general register 1 are added to form a 32-bit inter-
used along with the contents of general registers 1 mediate value. A carry out of bit position 0, if any,
and 3 to designate the starting addresses of two is ignored. The address of the current first-
fields in storage, called the first and third oper- operand halfword is generated from the interme-
ands. The first and third operands are logically diate value by following the normal rules for
compared, and a codeword is formed for use in operand address generation. The address of the
sort/merge algorithms. current third-operand halfword is formed in the
same manner by adding the contents of general
The second-operand address is not used to register 3 and the index.
address data. Bits 17-30 of the second-operand
address, with one rightmost and one leftmost zero The current first-operand and third-operand
appended, are used as a 16-bit index limit. Bit 31 halfwords are logically compared. If they are
of the second-operand address is the operand- equal, the contents of general register 2 are incre-
control bit. When bit 31 is zero, the codeword is mented by 2, and a unit of operation ends.
formed from the high operand; when bit 31 is one,
the codeword is formed from the low operand. If the compare values are unequal, the contents of
The remainder of the second-operand address is general register 2 are incremented by 2 and then
ignored. shifted left logically by 16 bit positions. If the
operand-control bit is zero, (1) the one's comple-
General registers 1 and 3 contain the base ment of the higher halfword is placed in the right
addresses of the first and third operands. Bits half of general register 2, and (2) if operand 1 was
16-31 of general register 2 are used as an index higher, the contents of general registers 1 and 3
for addressing both the first and third operands. are interchanged. If the operand-control bit is
General registers 1, 2, and 3 must all initially one, (1) the lower halfword is placed in the right
contain even values; otherwise, a specification half of general register 2, and (2) if operand 1 was
exception is recognized. lower, the contents of general registers 1 and 3
are interchanged.
In the access-register mode, access register 1
specifies the address space containing the first For the purpose of recognizing access exceptions,
and third operands. operand 1 and operand 3 are both considered to
have a length equal to 2 more than the value of
The operation consists in comparing the first and the index limit minus the index. When the index is
third operands halfword by halfword and incre- initially larger than the index limit, access
menting the index until an unequal pair of exceptions are not recognized for the storage
halfwords is found or the index exceeds the index operands. For operands longer than 4K bytes,
limit. This proceeds in units of operation, between access exceptions are not recognized more than
which interruptions may occur. The condition 4K bytes beyond the byte being processed.
Access exceptions are not recognized when a
specification-exception condition exists.
If the B field designates general register 2, it is tion, bit positions 0-15 of general register 2
unpredictable whether or not the index limit is will contain the offset at which another
recomputed; thus, in this case the operand length COMPARE AND FORM CODEWORD should
is unpredictable. However, in no case can the resume comparison for breaking codeword
operands exceed 2 bytes in length. ties. Operand-control-bit values of zero or
one are used for sorting operands in
Resulting Condition Code: ascending or descending order, respectively.
0 Operands equal Refer to “Sorting Instructions” on page A-51
1 Operand-control bit zero and operand 1 low, for a discussion of the use of codewords in
or operand-control bit one and operand 3 low sorting.
2 Operand-control bit zero and operand 1 high, 3. The condition code indicates the results of
or operand-control bit one and operand 3 high comparing operands up to 32,768 bytes long.
3 -- Equal operands result in a negative codeword
in general register 2. A negative codeword
Program Exceptions: also results when the index limit is 32,766 and
Access (fetch, operands 1 and 3) the operands that are compared differ in only
Specification their last two bytes. If this latter codeword is
used by UPDATE TREE, an incorrect result
Programming Notes: may be indicated in general registers 0 and 1.
Therefore, the index limit should not exceed
1. An example of the use of COMPARE AND
32,764 when the resulting codeword is to be
FORM CODEWORD is given in “Sorting
used by UPDATE TREE.
Instructions” in Appendix A, “Number Repre-
sentation and Instruction-Use Examples.” 4. Special precautions should be taken if
COMPARE AND FORM CODEWORD is
2. The offset of the halfword of the first and third
made the target of EXECUTE. See the pro-
operands at which comparison is to begin
gramming note concerning interruptible
should be placed in bit positions 16-31 of
instructions under EXECUTE.
general register 2 before executing
COMPARE AND FORM CODEWORD. The 5. Further programming notes concerning inter-
index limit derived from the second-operand ruptible instructions are included in “Interrup-
address should be the offset of the last tible Instructions” in Chapter 5, “Program
halfword of the first and third operands for Execution.”
which comparison can be made. When the 6. The storage-operand references of
operands do not compare equal, the left half COMPARE AND FORM CODEWORD may be
of the codeword formed in general register 2 multiple-access references. (See “Storage-
by the execution of COMPARE AND FORM Operand Consistency” on page 5-87.)
CODEWORD gives the offset of the first
halfword not compared. If the codewords 7. Figure 7-29 on page 7-38 and Figure 7-30 on
compare equal in an UPDATE TREE opera- page 7-39 contain summaries of the opera-
tion.
┌────────┬─────────┬─────────┬─────────┬────────┬────────┐
│Operand-│ │Resulting│ │ │ │
│Control │ │Condition│ Result │ Result │ Result │
│ Bit │Relation │ Code │ in GR2 │ in GR1 │ in GR3 │
├────────┼─────────┼─────────┼─────────┼────────┼────────┤
│ │op1 = op3│ │ OGR3b1 │ - │ - │
│ │op1 < op3│ 1 │ X, nop3 │ - │ - │
│ │op1 > op3│ 2 │ X, nop1 │ OGR3 │ OGR1 │
│ 1 │op1 = op3│ │ OGR3b1 │ - │ - │
│ 1 │op1 < op3│ 2 │ X, top1 │ OGR3 │ OGR1 │
│ 1 │op1 > op3│ 1 │ X, top3 │ - │ - │
├────────┴─────────┴─────────┴─────────┴────────┴────────┤
│Explanation: │
│ │
│ - The contents of the register remain unchanged. │
│ │
│ OGR1 The original contents of GR1. │
│ │
│ OGR3 The original contents of GR3. │
│ │
│ OGR3b1 The original contents of GR3 with bit set to │
│ one. │
│ │
│ X Bits -15 of GR2 are 2 more than the index of │
│ the first unequal halfword. │
│ │
│ nop1 Bits 16-31 of GR2 are the one's complement of │
│ the first unequal halfword in operand 1. │
│ │
│ nop3 Bits 16-31 of GR2 are the one's complement of │
│ the first unequal halfword in operand 3. │
│ │
│ top1 Bits 16-31 of GR2 are the first unequal halfword│
│ in operand 1. │
│ │
│ top3 Bits 16-31 of GR2 are the first unequal halfword│
│ in operand 3. │
└────────────────────────────────────────────────────────┘
Figure 7-29. Operation of COMPARE AND FORM CODEWORD
┌─────────────────────────────────────────────────────┐
│2 x bits 17-3 of 2nd-operand address ── index limit│
│ │
│Bit 31 of 2nd-operand address ── operand-control bit│
└──────────────────────────┬──────────────────────────┘
│
┌──────────────────────────────────────┐ No
│Bit 31 of GR1, GR2, and GR3 all zeros├───────────── Specification
└──────────────────┬───────────────────┘ exception
│ Yes
┌───────────────────────│
│
│ ┌───────────────────────────────┐ Yes
│ │Bits 16-31 of GR2 > index limit├───────────────────┐
│ └───────────────┬───────────────┘ │
│ │ No │
│
┌────┴────┐ ┌──────────────────────────────┐ ┌──────────────────┐
│Unit-of- │ │GR1 + bits 16-31 of GR2 │ │GR3 ── GR2 │
│operation│ │── 1st-operand address │ │ │
│boundary │ │ │ │1 ── bit of GR2│
└─────────┘ │GR3 + bits 16-31 of GR2 │ │ │
│── 3rd-operand address │ │ ── Cond code │
│ │ │ └────────┬─────────┘
│ │Fetch halfwords from current │ │
│ │1st- and 3rd-operand locations│
│ │ │ End operation
│ │GR2 + 2 ── GR2 │
│ └──────────────┬───────────────┘
│ │
│
│ Equal ┌─────────────────────────┐ 1st op high
└───────────┤Compare halfwords fetched├───────────────────────────┐
└────────────┬────────────┘ │
│ 1st op low │
Zero ┌────────────────────────┐ Zero ┌────────────────────────┐
┌─────────┤Test operand-control bit│ ┌──────┤Test operand-control bit│
│ └───────────┬────────────┘ │ └────────────┬───────────┘
│ One │ One
┌────────────────┐ ┌────────────────┐
│One's complement│ ┌───────────────┐ │One's complement│ ┌──────────┐
│of 3rd-op HW │ │1st-op HW │ │of 1st-op HW │ │3rd-op HW │
│── TEMPHW │ │── TEMPHW │ │── TEMPHW │ │── TEMPHW│
└───────┬────────┘ │ │ │ │ └────┬─────┘
│ │Exchange │ │Exchange │ │
│GR1 and GR3 │ │GR1 and GR3 │
┌────────────────┐ │ │ │ │ ┌───────────────┐
│1 ── Cond code │ │2 ── Cond code│ │2 ── Cond code │ │1 ── Cond code│
└───────┬────────┘ └───────┬───────┘ └───────┬────────┘ └───────┬───────┘
│ │ │ │
│ │
└─────────────────────────────────────────────────────────┘
│
┌────────────────────────────┐
│Shift GR2 left 16 positions │
│ │
│TEMPHW ── bits 16-31 of GR2│
└─────────────┬──────────────┘
│
End operation
Figure 7-30. Execution of COMPARE AND FORM CODEWORD
successful, condition code 0 is set. If the on continuing, cannot easily detect that the list
storage location no longer contains the is changed. By increasing the size of the
original value, the update has not been control word to a doubleword containing both
successful, the general register desig- the first message address and a word with a
nated by the R field of the COMPARE change number that is incremented for each
AND SWAP instruction contains the new modification of the list, and by using
current value of the storage location, and COMPARE DOUBLE AND SWAP to update
condition code 1 is set. When condition both fields together, the possibility of the list
code 1 is set, the CPU program can being incorrectly updated is reduced to a neg-
repeat the procedure using the new ligible level. That is, an incorrect update can
current value. occur only if the first CPU program is delayed
while changes exactly equal in number to a
b. COMPARE AND SWAP can be used for
multiple of 2 take place and only if the last
controlled sharing of a common storage
change places the original message address
area, including the capability of leaving a
in the control word.
message (in a chained list of messages)
when the common area is in use. To 4. COMPARE AND SWAP and COMPARE
accomplish this, a word in storage can be DOUBLE AND SWAP do not interlock against
used as a control word, with a zero value storage accesses by channel programs.
in the word indicating that the common Therefore, the instructions should not be used
area is not in use and that no messages to update a location at which a channel
exist, a negative value indicating that the program may store, since the channel-
area is in use and that no messages exist, program data may be lost.
and a nonzero positive value indicating
5. To ensure successful updating of a common
that the common area is in use and that
storage field by two or more CPUs, all
the value is the address of the most
updates must be done by means of an
recent message added to the list. Thus,
interlocked-update reference. COMPARE
any number of CPU programs desiring to
AND SWAP, COMPARE AND SWAP AND
seize the area can use COMPARE AND
PURGE, COMPARE DOUBLE AND SWAP,
SWAP to update the control word to indi-
and TEST AND SET are the only instructions
cate that the area is in use or to add mes-
that perform an interlocked-update reference.
sages to the list. The single CPU
For example, if one CPU executes OR IMME-
program which has seized the area can
DIATE and another CPU executes COMPARE
also safely use COMPARE AND SWAP to
AND SWAP to update the same byte, the
remove messages from the list.
fetch by OR IMMEDIATE may occur either
3. COMPARE DOUBLE AND SWAP can be before the fetch by COMPARE AND SWAP or
used in a manner similar to that described for between the fetch and the store by
COMPARE AND SWAP. In addition, it has COMPARE AND SWAP, and then the store
another use. Consider a chained list, with a by OR IMMEDIATE may occur after the store
control word used to address the first by COMPARE AND SWAP, in which case the
message in the list, as described in program- change made by COMPARE AND SWAP is
ming note 2b above. If multiple CPU pro- lost.
grams are to be permitted to delete messages
6. For the case of a condition-code setting of 1,
by using COMPARE AND SWAP (and not just
COMPARE AND SWAP and COMPARE
the single CPU program which has seized the
DOUBLE AND SWAP may or may not,
common area), there is a possibility the list
depending on the model, cause any of the fol-
will be incorrectly updated. This would occur
lowing to occur for the second-operand
if, for example, after one CPU program has
location: a PER storage-alteration event may
fetched the address of the most recent
be recognized; a protection exception for
message in order to remove the message,
storing may be recognized; and, provided no
another CPU program removes the first two
access exception exists, the change bit may
messages and then adds the first message
be set to one. Because the contents of
back into the chain. The first CPU program,
storage remain unchanged, the change bit
The contents of the M field are used as a mask. The R and R fields each designate an even-odd
These four bits, left to right, correspond one for pair of general registers and must designate an
one with the four bytes, left to right, of general even-numbered register; otherwise, a specification
register R. The byte positions corresponding to exception is recognized.
ones in the mask are considered as a contiguous
field and are compared with the second operand. The location of the leftmost byte of the first
The second operand is a contiguous field in operand and second operand is designated by the
storage, starting at the second-operand address contents of general registers R and R, respec-
and equal in length to the number of ones in the tively. The number of bytes in the first-operand
mask. The bytes in the general register corre- and second-operand locations is specified by
sponding to zeros in the mask do not participate in unsigned binary integers in bit positions 8-31 of
the operation. general registers R + 1 and R + 1, respec-
tively. Bit positions 0-7 of general register R + 1
The comparison proceeds left to right, byte by contain the padding byte. The contents of bit
byte, and ends as soon as an inequality is found positions 0-7 of general register R + 1 are
or the end of the fields is reached. ignored.
When the mask is not zero, exceptions associated The handling of the addresses in general registers
with storage-operand access are recognized for R and R is dependent on the addressing mode.
no more than the number of bytes specified by the
mask. Access exceptions may or may not be In the 24-bit addressing mode, the contents of bit
recognized for the portion of a storage operand to positions 8-31 of general registers R and R con-
the right of the first unequal byte. When the mask stitute the address, and the contents of bit posi-
is zero, access exceptions are recognized for one tions 0-7 are ignored. In the 31-bit addressing
byte at the second-operand address. mode, the contents of bit positions 1-31 of general
registers R and R constitute the address, and
Resulting Condition Code: the contents of bit position 0 are ignored.
0 Operands equal, or mask bits all zeros The contents of the registers just described are
1 First operand low shown in Figure 7-31 on page 7-44.
2 First operand high
3 --
Program Exceptions:
Access (fetch, operand 2)
Programming Note: An example of the use of
the COMPARE LOGICAL CHARACTERS UNDER
MASK instruction is given in Appendix A, “Number
Representation and Instruction-Use Examples.”
┌──────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬───────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴───────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌────────┬────────────────────────┐ │
│ R + 1 │////////│ First-Operand Length │ │////////│ First-Operand Length │ │
│ └────────┴───────────────────────┘ └────────┴────────────────────────┘ │
│ 8 31 8 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬───────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴───────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌────────┬────────────────────────┐ │
│ R + 1 │ Pad │ Second-Operand Length │ │ Pad │ Second-Operand Length │ │
│ └────────┴───────────────────────┘ └────────┴────────────────────────┘ │
│ 8 31 8 31 │
│ │
└──────────────────────────────────────────────────────────────────────────────────┘
Figure 7-31. Register Contents for COMPARE LOGICAL LONG
The comparison proceeds left to right, byte by If the operation ends because of an inequality, the
byte, and ends as soon as an inequality is found address fields in general registers R and R at
or the end of the longer operand is reached. If completion identify the first unequal byte in each
the operands are not of the same length, the operand. The lengths in bit positions 8-31 of
shorter operand is considered to be extended on general registers R + 1 and R + 1 are decre-
the right with the appropriate number of padding mented by the number of bytes that were equal,
bytes. unless the inequality occurred with the padding
byte, in which case the length field for the shorter
If both operands are of zero length, the operands operand is set to zero. The addresses in general
are considered to be equal. registers R and R are incremented by the
amounts by which the corresponding length fields
The execution of the instruction is interruptible. were reduced.
When an interruption occurs, other than one that
| follows termination, the contents of general regis- If the two operands, including the padding byte, if
ters R + 1 and R + 1 are decremented by the necessary, are equal, both length fields are made
number of bytes compared, and the contents of zero at completion, and the addresses are incre-
general registers R and R are incremented by mented by the corresponding operand-length
the same number, so that the instruction, when values.
reexecuted, resumes at the point of interruption.
The leftmost bits which are not part of the address At the completion of the operation, the leftmost
in general registers R and R are set to zeros; bits which are not part of the address in general
the contents of bit positions 0-7 of general regis- registers R and R are set to zeros, even when
ters R + 1 and R + 1 remain unchanged; and one or both of the initial length values are zero.
the condition code is unpredictable. If the opera- The contents of bit positions 0-7 of general regis-
tion is interrupted after the shorter operand has ters R + 1 and R + 1 remain unchanged.
been exhausted, the length field pertaining to the
shorter operand is zero, and its address is Access exceptions for the portion of a storage
updated accordingly. operand to the right of the first unequal byte may
or may not be recognized. For operands longer
than 2K bytes, access exceptions are not recog-
nized more than 2K bytes beyond the byte being 5. In the access-register mode, access register 0
processed. Access exceptions are not indicated designates the primary address space regard-
for locations more than 2K bytes beyond the first less of the contents of access register 0.
unequal byte.
┌───────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Third-Operand Address │ │/│ Third-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Third-Operand Length │ │ Third-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌───────────────────────┬────────┐ ┌───────────────────────┬────────┐ │
│ 2nd Op. │///////////////////////│ Pad │ │///////////////////////│ Pad │ │
│ Address └───────────────────────┴────────┘ └───────────────────────┴────────┘ │
│ 24 31 24 31 │
│ │
└───────────────────────────────────────────────────────────────────────────────────┘
Figure 7-32. Register Contents and Second-Operand Address for COMPARE LOGICAL LONG EXTENDED
The comparison proceeds left to right, byte by sponding length fields were decremented. Condi-
byte, and ends as soon as an inequality is found, tion code 1 is set if the first operand is low, or
the end of the longer operand is reached, or a condition code 2 is set if the first operand is high.
CPU-determined number of bytes have been com-
pared, whichever occurs first. If the operands are If the two operands, including the padding byte, if
not of the same length, the shorter operand is necessary, are equal, both length fields are made
considered to be extended on the right with the zero at completion, and the addresses are incre-
appropriate number of padding bytes. mented by the corresponding operand-length
values. Condition code 0 is set.
If both operands are of zero length, the operands
are considered to be equal. If the operation is completed because a
CPU-determined number of bytes have been com-
If the operation ends because of an inequality, the pared without finding an inequality or reaching the
address fields in general registers R and R at end of the longer operand, the lengths in general
completion identify the first unequal byte in each registers R + 1 and R + 1 are decremented by
operand. The lengths in general registers R + 1 the number of bytes compared, and the addresses
and R + 1 are decremented by the number of in general registers R and R are incremented by
bytes that were equal, unless the inequality the same number, so that the instruction, when
occurred with the padding byte, in which case the reexecuted, resumes at the next bytes to be com-
length field for the shorter operand is set to zero. pared. If the operation is completed after the
The addresses in general registers R and R are shorter operand has been exhausted, the length
incremented by the amounts by which the corre- field pertaining to the shorter operand is zero, and
is reached, or a CPU-determined number of char- with the appropriate number of two-byte padding
acters have been compared, whichever occurs characters.
first. The shorter operand is considered to be
extended on the right with two-byte padding char- If both operands are of zero length, the operands
acters. The result is indicated in the condition are considered to be equal.
code.
If the operation ends because of an inequality, the
The R and R fields each designate an even-odd address fields in general registers R and R at
pair of general registers and must designate an completion identify the first unequal two-byte char-
even-numbered register; otherwise, a specification acter in each operand. The lengths in bit posi-
exception is recognized. tions 0-31 of general registers R + 1 and
R + 1 are decremented by 2 times the number
The location of the leftmost character of the first of characters that were equal, unless the ine-
operand and third operand is designated by the quality occurred with the two-byte padding char-
contents of general registers R and R, respec- acter, in which case the length field for the shorter
tively. The number of bytes in the first-operand operand is set to zero. The addresses in general
and third-operand locations is specified by the registers R and R are incremented by the
contents of bit positions 0-31 of general registers amounts by which the corresponding length fields
R + 1 and R + 1, respectively, and those con- were decremented. Condition code 1 is set if the
tents are treated as 32-bit unsigned binary inte- first operand is low, or condition code 2 is set if
gers. the first operand is high.
The contents of general registers R + 1 and If the two operands, including the two-byte
R + 1 must specify an even number of bytes; padding character, if necessary, are equal, both
otherwise, a specification exception is recognized. length fields are made zero at completion, and the
addresses are incremented by the corresponding
The handling of the addresses in general registers operand-length values. Condition code 0 is set.
R and R is dependent on the addressing mode.
If the operation is completed because a
In the 24-bit addressing mode, the contents of bit CPU-determined number of characters have been
positions 8-31 of general registers R and R con- compared without finding an inequality or reaching
stitute the address, and the contents of bit posi- the end of the longer operand, the lengths in
tions 0-7 are ignored. In the 31-bit addressing general registers R + 1 and R + 1 are decre-
mode, the contents of bit positions 1-31 of the reg- mented by 2 times the number of characters com-
isters constitute the address, and the contents of pared, and the addresses in general registers R
bit position 0 are ignored. and R are incremented by the same number, so
that the instruction, when reexecuted, resumes at
The second-operand address is not used to the next characters to be compared. If the opera-
address data; instead, the rightmost 16 bits of the tion is completed after the shorter operand has
second-operand address, bits 16-31, are the two- been exhausted, the length field pertaining to the
byte padding character. Bits 0-15 of the second- shorter operand is zero, and the operand address
operand address are ignored. is updated accordingly. Condition code 3 is set.
The contents of the registers and address just The two-byte padding character may be formed
described are shown in Figure 7-33 on from D(B) multiple times during the execution of
page 7-49. the instruction, and the registers designated by R
and R may be updated multiple times. There-
The comparison proceeds left to right, character fore, if B equals R, R + 1, R, or R + 1 and
by character, and ends as soon as an inequality is is subject to change during the execution of the
found, the end of the longer operand is reached, instruction, the results are unpredictable.
or a CPU-determined number of characters have
been compared, whichever occurs first. If the The amount of processing that results in the
operands are not of the same length, the shorter setting of condition code 3 is determined by the
operand is considered to be extended on the right CPU on the basis of improving system perform-
┌───────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Third-Operand Address │ │/│ Third-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Third-Operand Length │ │ Third-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌───────────────┬────────────────┐ ┌───────────────┬────────────────┐ │
│ 2nd Op. │///////////////│ Pad │ │///////////////│ Pad │ │
│ Address └───────────────┴────────────────┘ └───────────────┴────────────────┘ │
│ 24 31 24 31 │
│ │
└───────────────────────────────────────────────────────────────────────────────────┘
Figure 7-33. Register Contents and Second-Operand Address for COMPARE LOGICAL LONG UNICODE
ance, and it may be a different amount each time Resulting Condition Code:
the instruction is executed.
0 All characters compared; operands equal, or
both zero length
At the completion of the operation, the leftmost
1 First operand low
bits which are not part of the address in general
2 First operand high
registers R and R may be set to zeros or may
3 CPU-determined number of characters com-
remain unchanged from their original values,
pared without finding an inequality
including the case when one or both of the initial
length values are zero.
Program Exceptions:
Access exceptions for the portion of a storage Access (fetch, operands 1 and 3)
operand to the right of the first unequal character Operation (if the extended-translation facility 2
may or may not be recognized. For operands is not installed)
longer than 4K bytes, access exceptions are not Specification
recognized more than 4K bytes beyond the char-
acter being processed. Access exceptions are not Programming Notes:
indicated for locations more than 4K bytes beyond 1. COMPARE LOGICAL LONG UNICODE is
the first unequal character. intended for use in place of COMPARE
LOGICAL LONG or COMPARE LOGICAL
When the length of an operand is zero, no access
LONG EXTENDED when two-byte characters
exceptions are recognized for that operand.
are to be compared. The characters may be
Access exceptions are not recognized for an
Unicode characters or any other double-byte
operand if the R field or length associated with
characters. COMPARE LOGICAL LONG
that operand is odd.
UNICODE sets condition code 3 in cases in
which COMPARE LOGICAL LONG would be
interrupted.
2. When condition code 3 is set, the program contents of general registers R and R, respec-
can simply branch back to the instruction to tively.
continue the comparison. The program need
not determine the number of characters that The handling of the addresses in general registers
were compared. R and R is dependent on the addressing mode.
In the 24-bit addressing mode, the contents of bit
3. When the R and R fields are the same, the
positions 8-31 of general registers R and R con-
operation proceeds in the same way as when
stitute the address, and the contents of bit posi-
two distinct pairs of registers having the same
tions 0-7 are ignored. In the 31-bit addressing
contents are specified, except that the con-
mode, the contents of bit positions 1-31 of general
tents of the designated registers are incre-
registers R and R constitute the address, and
mented or decremented only by 2 times the
the contents of bit position 0 are ignored.
number of characters compared, not by 4
times the number of characters compared. In The first and second operands may be of the
the absence of dynamic modification of the same or different lengths. The end of an operand
operand area by another CPU or by a channel is indicated by an ending character in the last byte
program, the condition code is finally set to 0 position of the operand. The ending character to
after possible settings to 3. However, it is be used to determine the end of an operand is
unpredictable whether access exceptions are specified in bit positions 24-31 of general register
recognized for the operand since the opera- 0. Bit positions 0-23 of general register 0 are
tion can be completed without storage being reserved for possible future extensions and must
accessed. If storage is not accessed, condi- contain all zeros; otherwise, a specification excep-
tion code 3 may or may not be set regardless tion is recognized.
of the operand length.
4. In the access-register mode, access register 0 The operation proceeds left to right, byte by byte,
designates the primary address space regard- and ends as soon as the ending character is
less of the contents of access register 0. encountered in either or both operands, unequal
bytes which do not include an ending character
5. If padding with a Unicode space character is are compared, or a CPU-determined number of
required (or any character whose represen- bytes have been compared, whichever occurs
tation is less than or equal to FFF hex), the first. The CPU-determined number is at least 256.
character may be represented in the displace- When the ending character is encountered simul-
ment field of the instruction, for example: taneously in both operands, even when it is in the
CLCLU 6,8,X'2' first byte position of the operands, the operands
are of the same length and are considered to be
COMPARE LOGICAL STRING equal, and condition code 0 is set. When the
ending character is encountered in only one
CLST R,R [RRE] operand, that operand, which is the shorter
operand, is considered to be low, and condition
┌────────────────┬────────┬────┬────┐
│ 'B25D' │////////│ R │ R │ code 1 or 2 is set. Condition code 1 is set if the
└────────────────┴────────┴────┴────┘ first operand is low, or condition code 2 is set if
16 24 28 31 the second operand is low. Similarly, when
unequal bytes which do not include an ending
The first operand is compared with the second character are compared, condition code 1 is set if
operand until unequal bytes are compared, the the lower byte is in the first operand, or condition
end of either operand is reached, or a code 2 is set if the lower byte is in the second
CPU-determined number of bytes have been com- operand. When a CPU-determined number of
pared, whichever occurs first. The bytes have been compared, condition code 3 is
CPU-determined number is at least 256. The set.
result is indicated in the condition code.
When condition code 1 or 2 is set, the address of
The location of the leftmost byte of the first the last byte processed in the first and second
operand and second operand is designated by the operands is placed in general registers R and
R, respectively. That is, when condition code 1
┌─────────────────────────────────────────────────────────────────────────────────┐
│ │
│ ┌───────────────────────┬────────┐ ┌───────────────────────┬────────┐ │
│ GR │///////////////////////│ SS Len.│ GR1 │///////////////////////│ Pad │ │
│ └───────────────────────┴────────┘ └───────────────────────┴────────┘ │
│ 24 31 24 31 │
│ │
├─────────────────────────────────────────────────────────────────────────────────┤
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Second-Operand Length │ │ Second-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
└─────────────────────────────────────────────────────────────────────────────────┘
Figure 7-34. Register Contents for COMPARE UNTIL SUBSTRING EQUAL
registers R + 1 and R + 1, respectively. When The result is obtained as if the operands were
an operand length is negative, it is treated as processed from left to right. However, multiple
zero, and it remains unchanged upon completion accesses may be made to all or some of the bytes
of the instruction. of each operand.
Bits 24-31 of general register 0 specify the The comparison proceeds left to right, byte by
unsigned substring length, a value of 0-255, in byte, and ends as soon as (1) equal substrings of
bytes. Bits 24-31 of general register 1 are the the specified length are found, (2) the end of the
padding byte. Bits 0-23 of general registers 0 and longer operand is reached without finding equal
1 are ignored. substrings of the specified length, or (3) the last
bytes compared are unequal, and a
The handling of the addresses in general registers CPU-determined number of bytes have been com-
R and R is dependent on the addressing mode. pared. The CPU-determined number is at least
In the 24-bit addressing mode, the contents of bit 256. If the operands are not of the same length,
positions 8-31 of general registers R and R con- the shorter operand is considered to be extended
stitute the address, and the contents of bit posi- on the right with the appropriate number of
tions 0-7 are ignored. In the 31-bit addressing padding bytes.
mode, the contents of bit positions 1-31 of general
registers R and R constitute the address, and If the operation ends because equal substrings of
the contents of bit position 0 are ignored. the specified length were found, the condition
code is set to 0. If the operation ends because
The contents of the registers just described are the end of the longer operand was reached
shown in Figure 7-34. without finding equal substrings of the specified
length, the condition code is set to 1 if equal bytes
were the last bytes compared, or it is set to 2 if
unequal bytes were the last bytes compared. If have been decremented by the number of bytes
the operation ends because unequal bytes were compared, except that a length field is not decre-
compared when a CPU-determined number of mented below zero.
bytes had been compared, the condition code is
set to 3. When the contents of the R and R fields are the
same, the first and second operands may be com-
If the specified substring length is zero, it is con- pared, or the condition code may be set to 0 or 1
sidered that equal substrings of the specified without comparing the operands.
length were found, and condition code 0 is set.
The substring length and padding byte may be
If both operands are of zero length but the speci- fetched from general registers 0 and 1 multiple
fied substring length is not zero, it is considered times during the execution of the instruction, and
that the end of the longer operand was reached the registers designated by R and R may be
when unequal bytes were the last bytes com- updated multiple times. Therefore, if R or R is
pared, and condition code 2 is set. zero, the results are unpredictable.
If equal bytes have been compared but then When condition code 3 is set, the general regis-
unequal bytes are compared, it is considered that ters used by the instruction have been set so that
all bytes so far compared are unequal. the remainder of the operands can be processed
by simply branching back and reexecuting the
At the completion of the operation, the operand- instruction.
length fields in the R + 1 and R + 1 registers
are decremented by the number of unequal bytes The amount of processing that results in the
compared (including equal bytes before unequal setting of condition code 3 is determined by the
bytes compared), and the addresses in the R CPU on the basis of improving system perform-
and R registers are incremented by the same ance, and it may be a different amount each time
number. However, in the case when a byte of the the instruction is executed.
longer operand is compared against the padding
byte, the length field for the shorter operand is not The execution of the instruction is interruptible
decremented below zero, and the corresponding when the last bytes compared are unequal; it is
address is not incremented above the address of not interruptible when the last bytes compared are
the first byte after the shorter operand. The left- equal. When an interruption occurs, other than
most bits which are not part of the addresses in | one that follows termination, the contents of the
registers R and R are set to zeros, even if the registers designated by the R and R fields are
substring length is zero or both operand lengths updated the same as upon normal completion of
are initially zero. the instruction, so that the instruction, when reexe-
cuted, resumes at the point of interruption. The
Thus, when condition code 0 or 1 is set, the condition code is unpredictable.
resulting addresses in the R and R registers
designate the first bytes of equal substrings in the Access exceptions for the portion of a storage
two operands, and the lengths in the R + 1 and operand to the right of the last byte processed
R + 1 registers have been decremented by the may or may not be recognized. For operands
number of bytes preceding the equal substrings, longer than 4K bytes, access exceptions are not
except when the equal substring in the shorter recognized for locations more than 4K bytes
operand begins with the padding byte, in which beyond the last byte processed.
case the length field for the shorter operand is
zero, and the corresponding address field has When the length of an operand is zero, no access
been incremented by the operand length. When exceptions are recognized for that operand.
condition code 2 is set, each address field desig- Access exceptions are not recognized for an
nates the first byte after the corresponding operand if the R field associated with that operand
operand, and both length fields are zero. When is odd. Although the operand address and length
condition code 3 is set, each address field desig- fields remain unchanged when a zero substring
nates the first byte after the last compared byte of length is specified, the recognition of access
the corresponding operand, and both length fields exceptions is not necessarily prevented.
| ┌────────────────┬────────┬────┬────┐
| The function codes for COMPUTE LAST
| │ 'B93F' │////////│ R │ R │ | MESSAGE DIGEST are as follows.
| └────────────────┴────────┴────┴────┘
| 16 24 28 31
| Figure 7-36. Function Codes for COMPUTE LAST
| MESSAGE DIGEST
| A function specified by the function code in
| Parm. Data
| general register 0 is performed.
| Block Block
| Bits 16-23 of the instruction and the R field are | Size Size
| ignored. | Code Function (bytes) (bytes)
| 0 KLMD-Query 16 —
| Bit positions 25-31 of general register 0 contain
| the function code. Figures 7-35 and 7-36 show | 1 KLMD-SHA-1 28 64
| the assigned function codes for COMPUTE | Explanation:
| INTERMEDIATE MESSAGE DIGEST and
| — Not applicable
| COMPUTE LAST MESSAGE DIGEST, respec-
| tively. All other function codes are unassigned.
| Bit 24 of general register 0 must be zero; other- | All other function codes are unassigned.
| wise, a specification exception is recognized. All
| other bits of general register 0 are ignored. | The query function provides the means of indi-
| cating the availability of the other functions. The
| General register 1 contains the logical address of | contents of general registers R and R + 1 are
| the leftmost byte of the parameter block in | ignored for the query function.
| storage. In the 24-bit addressing mode, the con-
| tents of bit positions 8-31 of general register 1 | For all other functions, the second operand is
| constitute the address, and the contents of bit | processed as specified by the function code using
| positions 0-7 are ignored. In the 31-bit addressing | an initial chaining value in the parameter block,
| mode, the contents of bit positions 1-31 of general | and the result replaces the chaining value. For
| register 1 constitute the address, and the content | COMPUTE LAST MESSAGE DIGEST, the opera-
| of bit position 0 is ignored. | tion also uses a message bit length in the param-
| eter block. The operation proceeds until the end
| The function codes for COMPUTE INTERME- | of the second-operand location is reached or a
| DIATE MESSAGE DIGEST are as follows. | CPU-determined number of bytes have been proc-
| essed, whichever occurs first. The result is indi-
| cated in the condition code.
| The location of the leftmost byte of the second | of bit positions 0-7 of general register R are set
| operand is specified by the contents of the R | to zeros. In the 31-bit addressing mode, the con-
| general register. The number of bytes in the | tents of bit positions 1-31 of general register R
| second-operand location is specified in general | constitute the address of second operand, and the
| register R + 1. | content of bit position 0 is ignored; bits 1-31 of the
| updated address replace the corresponding bits in
| As part of the operation, the address in general | general register R, carries out of bit position 1 of
| register R is incremented by the number of bytes | the updated address are ignored, and bit 0 of
| processed from the second operand, and the | general register R is set to zero.
| length in general register R + 1 is decremented
| by the same number. The formation and updating | In both the 24-bit and the 31-bit addressing
| of the address and length is dependent on the | modes, the contents of bit positions 0-31 of
| addressing mode. | general register R + 1 form a 32-bit unsigned
| binary integer which specifies the number of bytes
| In the 24-bit addressing mode, the contents of bit | in the second operand; and the updated value
| positions 8-31 of general register R constitute the | replaces the contents of bit positions 0-31 of
| address of second operand, and the contents of | general register R + 1.
| bit positions 0-7 are ignored; bits 8-31 of the
| updated address replace the corresponding bits in | Figure 7-37 shows the contents of the general
| general register R, carries out of bit position 8 of | registers just described.
| the updated address are ignored, and the contents
| ┌────────────────────────┬─┬───────┐ ┌────────────────────────┬─┬───────┐
| GR │////////////////////////││ FC │ │////////////////////////││ FC │
| └────────────────────────┴─┴───────┘ └────────────────────────┴─┴───────┘
| 24 31 24 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| GR1 │////////│ Parameter-Block Address │ │/│ Parameter-Block Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| R │////////│ Second-Operand Address │ │/│ Second-Operand Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌──────────────────────────────────┐ ┌──────────────────────────────────┐
| R + 1 │ Second-Operand Length │ │ Second-Operand Length │
| └──────────────────────────────────┘ └──────────────────────────────────┘
| 31 31
| In the access-register mode, access registers 1 | less than the length of the second operand have
| and R specify the address spaces containing the | been processed (called partial completion). The
| parameter block and second operand, respec- | CPU-determined number of blocks depends on
| tively. | the model, and may be a different number each
| time the instruction is executed. The
| The result is obtained as if processing starts at the | CPU-determined number of blocks is usually
| left end of the second operand and proceeds to | nonzero. In certain unusual situations, this
| the right, block by block. The operation is ended | number may be zero, and condition code 3 may
| when all source bytes in the second operand have | be set with no progress. However, the CPU pro-
| been processed (called normal completion), or | tects against endless reoccurrence of this no-
| when a CPU-determined number of blocks that is | progress case.
| When the chaining-value field overlaps any portion | Secure Hash Standard, Federal Information Proc-
| of the second operand, the result in the chaining- | essing Standards publication 180-1, National Insti-
| value field is unpredictable. | tute of Standards and Technology, Washington
| DC, April 17, 1995.
| For COMPUTE INTERMEDIATE MESSAGE
| DIGEST, normal completion occurs when the
| number of bytes in the second operand as speci- | ICV <2> M <64>
| │
| fied in general register R + 1 have been proc-
| │ ┌─────┐
| essed. For COMPUTE LAST MESSAGE | └────────│SHA-1│
| DIGEST, after all bytes in the second operand as | │ bda │
| specified in general register R + 1 have been | └──┬──┘
| processed, the padding operation is performed, |
| and then normal completion occurs. | OCV <2>
| The following symbols are used in the subsequent | KIMD-SHA-1 (KIMD Function Code 1)
| description of the COMPUTE INTERMEDIATE
| MESSAGE DIGEST and COMPUTE LAST | The locations of the operands and addresses
| MESSAGE DIGEST functions. Further description | used by the instruction are as shown in
| of the secure hash algorithm may be found in | Figure 7-37 on page 7-56.
| The parameter block used for the function has the | A 128-bit status word is stored in the parameter
| following format: | block. Bits 0-127 of this field correspond to func-
| tion codes 0-127, respectively, of the COMPUTE
| ┌────────────┐ | LAST MESSAGE DIGEST instruction. When a bit
| │ H │
| is one, the corresponding function is installed; oth-
| ├────────────┤
| 4 │ H1 │ | erwise, the function is not installed.
| ├────────────┤
| 8 │ H2 │ | Condition code 0 is set when execution of the
| ├────────────┤ | KLMD-Query function completes; condition code 3
| 12 │ H3 │ | is not applicable to this function.
| ├────────────┤
| 16 │ H4 │
| └────────────┘ | KLMD-SHA-1 (KLMD Function Code 1)
| 31
| The locations of the operands and addresses
| Figure 7-40. Parameter Block for KIMD-SHA-1 | used by the instruction are as shown in
| Figure 7-37 on page 7-56.
| A 20-byte intermediate message digest is gener-
| ated for the the 64-byte message blocks in | The parameter block used for the function has the
| operand 2 using the SHA-1 block digest algorithm | following format:
| with the 20-byte chaining value in the parameter
| block. The generated intermediate message | ┌────────────┐
| digest, also called the output chaining value | │ H │
| (OCV), is stored in the chaining-value field of the | ├────────────┤
| 4 │ H1 │
| parameter block. The operation is shown in the
| ├────────────┤
| following figure: | 8 │ H2 │
| ├────────────┤
| OCV <2>
| 12 │ H3 │
| Parameter | ├────────────┤
| Block ┌──────────────────────────────────┐
| in │ H H1 H2 H3 H4 │ | 16 │ H4 │
| Storage └────────────────┬─────────────────┘ | ├────────────┤
|
| ICV <2> | 2 │ Message │
| │ Bit Length │
| Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐ | 24 │ (mbl) │
| in │ M1 <64> │ M2 <64> │ M3 <64> │ │ Mn <64> │
| Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘ | └────────────┘
|
| ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐ | 31
| ICV ─│SHA-1│ ┌────│SHA-1│ ┌────│SHA-1│ ┌─/────│SHA-1│
| │ bda │ │ │ bda │ │ │ bda │ │ │ bda │ | Figure 7-43. Parameter Block for KLMD-SHA-1
| └──┬──┘ │ └──┬──┘ │ └──┬──┘ │ └──┬──┘
| │ │ │ │ │ │
| └────┘ └────┘ └────┘ OCV <2>
| The message digest for the message (M) in
| Figure 7-41. KIMD-SHA-1 | operand 2 is generated using the SHA-1 algorithm
| with the chaining value and message-bit-length
| KLMD-Query (KLMD Function Code 0) | information in the parameter block.
| The locations of the operands and addresses | If the length of the message in operand 2 is equal
| used by the instruction are as shown in | to or greater than 64 bytes, an intermediate
| Figure 7-37 on page 7-56. | message digest is generated for each 64-byte
| message block using the SHA-1 block digest algo-
| The parameter block used for the function has the | rithm with the 20-byte chaining value in the
| following format: | parameter block, and the generated intermediate
| message digest, also called the output chaining
| ┌────────────────────────┐ | value (OCV), is stored into the chaining-value field
| │ │ | of the parameter block. This operation is shown in
| ├ Status Word ┤
| 8 │ │ | Figure 7-44 on page 7-59 and repeats until the
| └────────────────────────┘ | remaining message is less than 64 bytes.
| 63
| Figure 7-42. Parameter Block for KLMD-Query
| ┌───────────────────────────────────────────────────────────────────────┐
| │ 1.-6. Exceptions with the same priority as the priority of program- │
| │ interruption conditions for the general case. │
| │ │
| │ 7.A Access exceptions for second instruction halfword. │
| │ │
| │ 7.B Operation exception. │
| │ │
| │ 8. Specification exception due to invalid function code or │
| │ invalid register number. │
| │ │
| │ 9. Specification exception due to invalid operand length. │
| │ │
| │ 1. Condition code due to second-operand length originally zero. │
| │ │
| │ 11. Access exceptions for an access to the parameter block or │
| │ second operand. │
| │ │
| │ 12. Condition code due to normal completion (second-operand │
| │ length originally nonzero, but stepped to zero). │
| │ │
| │ 13. Condition code 3 due to partial completion (second-operand │
| │ length still nonzero). │
| └───────────────────────────────────────────────────────────────────────┘
| Figure 7-48. Priority of Execution: KIMD and KLMD
| constitute the address, and the contents of bit | numbered register; otherwise, a specification
| positions 0-7 are ignored. In the 31-bit addressing | exception is recognized.
| mode, the contents of bit positions 1-31 of general
| register 1 constitute the address, and the content | The location of the leftmost byte of the second
| of bit position 0 is ignored. | operand is specified by the contents of the R
| general register. The number of bytes in the
| The function codes for COMPUTE MESSAGE | second-operand location is specified in general
| AUTHENTICATION CODE are as follows. | register R + 1.
| Figure 7-49. Function Codes for COMPUTE | As part of the operation, the address in general
| MESSAGE AUTHENTICATION CODE | register R is incremented by the number of bytes
| processed from the second operand, and the
| Parm. Data | length in general register R + 1 is decremented
| Block Block | by the same number. The formation and updating
| Size Size | of the address and length is dependent on the
| Code Function (bytes) (bytes) | addressing mode.
| 0 KMAC-Query 16 —
| In the 24-bit addressing mode, the contents of bit
| 1 KMAC-DEA 16 8 | positions 8-31 of general register R constitute the
| 2 KMAC-TDEA-128 24 8 | address of second operand, and the contents of
| bit positions 0-7 are ignored; bits 8-31 of the
| 3 KMAC-TDEA-192 32 8 | updated address replace the corresponding bits in
| Explanation: | general register R, carries out of bit position 8 of
| the updated address are ignored, and the contents
| — Not applicable
| of bit positions 0-7 of general register R are set
| to zeros. In the 31-bit addressing mode, the con-
| All other function codes are unassigned. | tents of bit positions 1-31 of general register R
| constitute the address of second operand, and the
| The query function provides the means of indi- | content of bit position 0 is ignored; bits 1-31 of the
| cating the availability of the other functions. The | updated address replace the corresponding bits in
| contents of general registers R and R + 1 are | general register R, carries out of bit position 1 of
| ignored. | the updated address are ignored, and the content
| of bit position 0 of general register R is set to
| For all other functions, the second operand is | zero.
| processed as specified by the function code using
| an initial chaining value in the parameter block | In both the 24-bit and the 31-bit addressing
| and the result replaces the chaining value. The | modes, the contents of bit positions 0-31 of
| operation also uses a cryptographic key in the | general register R + 1 form a 32-bit unsigned
| parameter block. The operation proceeds until the | binary integer which specifies the number of bytes
| end of the second-operand location is reached or | in the second operand; and the updated value
| a CPU-determined number of bytes have been | replaces the contents of bit positions 0-31 of
| processed, whichever occurs first. The result is | general register R + 1.
| indicated in the condition code.
| Figure 7-50 on page 7-63 shows the contents of
| The R field designates an even-odd pair of | the general registers just described.
| general registers and must designate an even-
| ┌────────────────────────┬─┬───────┐ ┌────────────────────────┬─┬───────┐
| GR │////////////////////////││ FC │ │////////////////////////││ FC │
| └────────────────────────┴─┴───────┘ └────────────────────────┴─┴───────┘
| 24 31 24 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| GR1 │////////│ Parameter-Block Address │ │/│ Parameter-Block Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌────────┬─────────────────────────┐ ┌─┬────────────────────────────────┐
| R │////////│ Second-Operand Address │ │/│ Second-Operand Address │
| └────────┴─────────────────────────┘ └─┴────────────────────────────────┘
| 8 31 1 31
| ┌──────────────────────────────────┐ ┌──────────────────────────────────┐
| R + 1 │ Second-Operand Length │ │ Second-Operand Length │
| └──────────────────────────────────┘ └──────────────────────────────────┘
| 31 31
| In the access-register mode, access registers 1 | value in R + 1 is zero. When the operation
| and R specify the address spaces containing the | ends due to partial completion, condition code 3 is
| parameter block and second operand, respec- | set and the resulting value in R + 1 is nonzero.
| tively.
| When the second-operand length is initially zero,
| The result is obtained as if processing starts at the | the second operand and the parameter block are
| left end of the second operand and proceeds to | not accessed, general registers R and R + 1
| the right, block by block. The operation is ended | are not changed, and condition code 0 is set.
| when all source bytes in the second operand have
| been processed (called normal completion), or | As observed by other CPUs and channel pro-
| when a CPU-determined number of blocks that is | grams, references to the parameter block and
| less than the length of the second operand have | storage operands may be multiple-access refer-
| been processed (called partial completion). The | ences, accesses to these storage locations are
| CPU-determined number of blocks depends on | not necessarily block-concurrent, and the
| the model, and may be a different number each | sequence of these accesses or references is
| time the instruction is executed. The | undefined.
| CPU-determined number of blocks is usually
| nonzero. In certain unusual situations, this | Access exceptions may be reported for a larger
| number may be zero, and condition code 3 may | portion of the second operand than is processed
| be set with no progress. However, the CPU pro- | in a single execution of the instruction; however,
| tects against endless reoccurrence of this no- | access exceptions are not recognized for locations
| progress case. | beyond the length of the second operand nor for
| locations more than 4K bytes beyond the current
| When the chaining-value field overlaps any portion | location being processed.
| of the second operand, the result in the chaining-
| value field is unpredictable. | Symbols Used in Function Descriptions
| Normal completion occurs when the number of | The following symbols are used in the subsequent
| bytes in the second operand as specified in | description of the COMPUTE MESSAGE
| general register R + 1 have been processed. | AUTHENTICATION CODE functions. For data-
| encryption-algorithm (DEA) functions, the
| When the operation ends due to normal com- | DEA-key-parity bit in each byte of the DEA key is
| pletion, condition code 0 is set and the resulting | ignored, and the operation proceeds normally,
| regardless of the DEA-key parity of the key. | function is installed; otherwise, the function is not
| Further description of the data-encryption algo- | installed.
| rithm may be found in Data Encryption Algorithm,
| ANSI-X3.92.1981, American National Standard for | Condition code 0 is set when execution of the
| Information Systems. | KMAC-Query function completes; condition code 3
| is not applicable to this function.
| A | KMAC-DEA (Function Code 1)
|
| ┌───┐
| B ─│xor│ | The locations of the operands and addresses
| └─┬─┘
| | used by the instruction are as shown in
| C | Figure 7-50 on page 7-63.
| C = A XOR B
| The parameter block used for the function has the
| Figure 7-51. Symbol For Bit-Wise Exclusive Or | following format:
| ┌────────────────────────┐
| K <8> P <8> K <8> C <8> | │ Chaining Value (CV) │
| │ │ | ├────────────────────────┤
| │ ┌───┐ │ ┌───┐
| └─────│DEA│ └─────│DEA│
| 8 │ Cryptographic Key (K) │
| │ e │ │ d │ | └────────────────────────┘
| └─┬─┘ └─┬─┘ | 63
|
| C <8> P <8> | Figure 7-54. Parameter Block for KMAC-DEA
| Symbol for DEA Symbol for DEA
| Encryption Decryption | The message authentication code for the 8-byte
| message blocks (M1, M2, ..., Mn) in operand 2 is
| Symbol Explanation | computed using the DEA algorithm with the 64-bit
| <n> Length of item in bytes
| C Ciphertext | cryptographic key and the 64-bit chaining value in
| K Key value | the parameter block.
| P Plaintext
| The parameter block used for the function has the | ┌────────────────────────┐
| following format: | │ Chaining Value (CV) │
| ├────────────────────────┤
| ┌────────────────────────┐ | 8 │Cryptographic Key 1 (K1)│
| │ Chaining Value (CV) │ | ├────────────────────────┤
| ├────────────────────────┤ | 16 │Cryptographic Key 2 (K2)│
| 8 │Cryptographic Key 1 (K1)│ | ├────────────────────────┤
| ├────────────────────────┤ | 24 │Cryptographic Key 3 (K3)│
| 16 │Cryptographic Key 2 (K2)│ | └────────────────────────┘
| └────────────────────────┘ | 63
| 63 | Figure 7-58. Parameter Block for KMAC-TDEA-192
| Figure 7-56. Parameter Block for KMAC-TDEA-128
| The message authentication code for the 8-byte
| The message authentication code for the 8-byte | message blocks (M1, M2, ..., Mn) in operand 2 is
| message blocks (M1, M2, ..., Mn) in operand 2 is | computed using the TDEA algorithm with the three
| computed using the TDEA algorithm with the two | 64-bit cryptographic keys and the 64-bit chaining
| 64-bit cryptographic keys and the 64-bit chaining | value in the parameter block.
| value in the parameter block.
| The message authentication code, also called the
| The message authentication code, also called the | output chaining value (OCV), is stored in the
| output chaining value (OCV), is stored in the | chaining-value field of the parameter block. The
| chaining-value field of the parameter block. The | operation is shown in the following figure:
| operation is shown in the following figure:
| OCV
| Parameter
| OCV | Block ┌─────────────┬─────────────┬─────────────┬─────────────┐
| Parameter | in │ CV <8> │ K1 <8> │ K2 <8> │ K3 <8> │
| Block ┌─────────────┬─────────────┬─────────────┐ | Storage └──────┬──────┴──────┬──────┴──────┬──────┴──────┬──────┘
| in │ CV <8> │ K1 <8> │ K2 <8> │ |
| Storage └──────┬──────┴──────┬──────┴──────┬──────┘ | ICV K1 K2 K3
|
| ICV K1 K2
| Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐
| in │ M1 <8> │ M2 <8> │ M3 <8> │ │ Mn <8> │
| Op 2 ┌─────────────┬─────────────┬─────────────┬/┬─────────────┐ | Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘
| in │ M1 <8> │ M2 <8> │ M3 <8> │ │ Mn <8> │ |
| Storage └──────┬──────┴──────┬──────┴──────┬──────┴/┴──────┬──────┘ | ┌───┐ ┌───┐ ┌───┐ ┌───┐
| | ICV ─│xor│ ┌─────│xor│ ┌─────│xor│ ┌──/────│xor│
| ┌───┐ ┌───┐ ┌───┐ ┌───┐ | └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘
| ICV ─│xor│ ┌─────│xor│ ┌─────│xor│ ┌──/────│xor│ | │ │ │
| └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘ | ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐
| │ │ │ | K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│
| ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐ | │ e │ │ │ e │ │ │ e │ │ │ e │
| K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│ | └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘
| │ e │ │ │ e │ │ │ e │ │ │ e │ | │ │ │
| └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘ | ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐
| │ │ │ | K2 ─│DEA│ │ K2 ─│DEA│ │ K2 ─│DEA│ │ K2 ─│DEA│
| ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐ | │ d │ │ │ d │ │ │ d │ │ │ d │
| K2 ─│DEA│ │ K2 ─│DEA│ │ K2 ─│DEA│ │ K2 ─│DEA│ | └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘
| │ d │ │ │ d │ │ │ d │ │ │ d │ | │ │ │
| └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘ | ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐
| │ │ │ | K3 ─│DEA│ │ K3 ─│DEA│ │ K3 ─│DEA│ │ K3 ─│DEA│
| ┌───┐ │ ┌───┐ │ ┌───┐ │ ┌───┐ | │ e │ │ │ e │ │ │ e │ │ │ e │
| K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│ │ K1 ─│DEA│ | └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘
| │ e │ │ │ e │ │ │ e │ │ │ e │ | │ │ │ │ │ │
| └─┬─┘ │ └─┬─┘ │ └─┬─┘ │ └─┬─┘ | └────┘ └────┘ └────┘ OCV
| │ │ │ │ │ │
| └────┘ └────┘ └────┘ OCV
| Figure 7-59. KMAC-TDEA-192
| Figure 7-57. KMAC-TDEA-128
| Special Conditions for KMAC
| KMAC-TDEA-192 (Function Code 3)
| A specification exception is recognized and no
| The locations of the operands and addresses | other action is taken if any of the following occurs:
| used by the instruction are as shown in | 1. Bit 24 of general register 0 is not zero.
| Figure 7-50 on page 7-63.
| 2. Bits 25-31 of general register 0 specify an
| The parameter block used for the function has the | unassigned or uninstalled function code.
| following format: | 3. The R field designates an odd-numbered
| register or general register 0.
| ┌───────────────────────────────────────────────────────────────────────┐
| │ 1.-6. Exceptions with the same priority as the priority of program- │
| │ interruption conditions for the general case. │
| │ │
| │ 7.A Access exceptions for second instruction halfword. │
| │ │
| │ 7.B Operation exception. │
| │ │
| │ 8. Specification exception due to invalid function code or │
| │ invalid register number. │
| │ │
| │ 9. Specification exception due to invalid operand length. │
| │ │
| │ 1. Condition code due to second-operand length originally zero. │
| │ │
| │ 11. Access exceptions for an access to the parameter block or │
| │ second operand. │
| │ │
| │ 12. Condition code due to normal completion (second-operand │
| │ length originally nonzero, but stepped to zero). │
| │ │
| │ 13. Condition code 3 due to partial completion (second-operand │
| │ length still nonzero). │
| └───────────────────────────────────────────────────────────────────────┘
| Figure 7-60. Priority of Execution: KMAC
The second operand occupies eight bytes in The result occupies eight bytes in storage and is
storage and has the format of packed decimal in the format for packed decimal data, as
data, as described in Chapter 8, “Decimal described in Chapter 8, “Decimal Instructions.”
Instructions.” It is checked for valid sign and digit The rightmost four bits of the result represent the
codes, and a decimal-operand data exception is sign. A positive sign is encoded as 1100; a nega-
recognized when an invalid code is detected. tive sign is encoded as 1101.
The result of the conversion is a 32-bit signed Condition Code: The code remains unchanged.
binary integer, which is placed in general register
R. The maximum positive number that can be Program Exceptions:
converted and still be contained in a 32-bit register Access (store, operand 2)
is 2,147,483,647; the maximum negative number
(the negative number with the greatest absolute Programming Notes:
value) that can be converted is −2,147,483,648.
For any decimal number outside this range, the 1. An example of the use of the CONVERT TO
operation is completed by placing the 32 rightmost DECIMAL instruction is given in Appendix A,
bits of the binary result in the register, and a fixed- “Number Representation and Instruction-Use
point-divide exception is recognized. Examples.”
2. The number to be converted is a 32-bit signed
Condition Code: The code remains unchanged. binary integer obtained from a general reg-
ister. Since 15 decimal digits are available for
Program Exceptions: the result, and the decimal equivalent of 31
Access (fetch, operand 2) bits requires at most 10 decimal digits, an
Data overflow cannot occur.
Fixed-point divide 3. The storage-operand references for
CONVERT TO DECIMAL may be multiple-
Programming Notes:
access references. (See “Storage-Operand
1. An example of the use of the CONVERT TO Consistency” on page 5-87.)
BINARY instruction is given in Appendix A,
“Number Representation and Instruction-Use CONVERT UNICODE TO UTF-8
Examples.”
CUUTF R,R [RRE]
2. When the second operand is negative, the
result is in two's-complement notation. ┌────────────────┬────────┬────┬────┐
│ 'B2A6' │////////│ R │ R │
3. The storage-operand references for └────────────────┴────────┴────┴────┘
CONVERT TO BINARY may be multiple- 16 24 28 31
access references. (See “Storage-Operand
Consistency” on page 5-87.) The two-byte Unicode characters of the second
operand are converted to UTF-8 characters and
CONVERT TO DECIMAL placed at the first-operand location. The UTF-8
characters are one, two, three, or four bytes,
CVD R,D(X,B) [RX] depending on the Unicode characters that are
┌────────┬────┬────┬────┬────────────┐ converted. The operation proceeds until the end
│ '4E' │ R │ X │ B │ D │ of the first or second operand is reached or a
└────────┴────┴────┴────┴────────────┘ CPU-determined number of characters have been
8 12 16 2 31
converted, whichever occurs first. The result is
indicated in the condition code.
The first operand is changed from binary to
decimal, and the result is stored at the second- The R and R fields each designate an even-odd
operand location. The first operand is treated as pair of general registers and must designate an
a 32-bit signed binary integer. even-numbered register; otherwise, a specification
exception is recognized.
The location of the leftmost byte of the first Unicode High Surrogate 111111
operand and the second operand is designated by Bit Numbers 1234567 8912345
the contents of general registers R and R,
Identifying Bit Letters 1111ab cdefghij
respectively. The number of bytes in the first-
operand and second-operand locations is speci-
fied by bits 0-31 of general registers R + 1 and Unicode Low Surrogate 11112222 22222233
R + 1, respectively. The contents of general Bit Numbers 6789123 4567891
registers R + 1 and R + 1 are treated as 32-bit
Identifying Bit Letters 11111kl mnopqrst
unsigned binary integers.
Any Unicode character in the range 0000 to 007F
The handling of the addresses in general registers hex is converted to a one-byte UTF-8 character as
R and R is dependent on the addressing mode. follows:
Unicode jklmnop
In the 24-bit addressing mode, the contents of bit Character
positions 8-31 of general registers R and R con-
stitute the address, and the contents of bit posi- UTF-8 jklmnop
tions 0-7 are ignored. In the 31-bit addressing Character
mode, the contents of bit positions 1-31 of the reg- Any Unicode character in the range 0080 to 07FF
isters constitute the address, and the contents of hex is converted to a two-byte UTF-8 character as
bit position 0 are ignored. follows:
The contents of the registers just described are Unicode fgh ijklmnop
Character
shown in Figure 7-61 on page 7-69.
UTF-8 11fghij 1klmnop
The characters of the second operand are Character
selected one by one for conversion, proceeding
left to right. The bytes resulting from a conversion Any Unicode character in the range 0800 to D7FF
are placed at the first-operand location, pro- and DC00 to FFFF hex is converted to a three-
ceeding left to right. The operation proceeds until byte UTF-8 character as follows:
the first-operand or second-operand location is Unicode abcdefgh ijklmnop
exhausted or a CPU-determined number of Character
second-operand characters have been converted.
UTF-8 111abcd 1efghij 1klmnop
Character
To show the method of converting a Unicode
character to a UTF-8 character, the bits of a Any Unicode surrogate pair starting with a high
Unicode character are identified by letters as surrogate in the range D800 to DBFF hex is con-
follows: verted to a four-byte UTF-8 character as follows:
Unicode Character 111111 Unicode 1111ab cdefghij 11111kl mnopqrst
Bit Numbers 1234567 8912345 Characters
┌─────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Second-Operand Length │ │ Second-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
└─────────────────────────────────────────────────────────────────────────────────┘
Figure 7-61. Register Contents for CONVERT UNICODE TO UTF-8
conversion of the next second-operand character CPU on the basis of improving system perform-
or surrogate pair. ance, and it may be a different amount each time
the instruction is executed.
When the second-operand location is exhausted,
condition code 0 is set. When the first-operand When the R register is the same register as the
location is exhausted, condition code 1 is set, R register, the results are unpredictable.
except that condition code 0 is set if the second-
operand location also is exhausted. When a When the second operand overlaps the first
CPU-determined number of characters have been operand, the results are unpredictable.
converted, condition code 3 is set.
Access exceptions for the portions of the oper-
When the operation is completed, the contents of ands to the right of the last byte processed may or
general register R + 1 are decremented by the may not be recognized. For an operand longer
number of bytes converted, and the contents of than 4K bytes, access exceptions are not recog-
general register R are incremented by the same nized for locations more than 4K bytes beyond the
number. Also, the contents of general register last byte processed.
R + 1 are decremented by the number of bytes
placed at the first-operand location, and the con- When the length of an operand is zero, no access
tents of general register R are incremented by exceptions are recognized for that operand.
the same number. When general registers R Access exceptions are not recognized for an
and R are updated, the bits in them that are not operand if the R field associated with that operand
part of the address may be set to zeros or may is odd.
remain unchanged.
Resulting Condition Code:
When condition code 3 is set, the registers have 0 Entire second operand processed
been updated so that the instruction, when reexe- 1 End of first operand reached
cuted, resumes at the next byte locations to be 2 --
processed. 3 CPU-determined number of characters con-
verted
The amount of processing that results in the
setting of condition code 3 is determined by the
1. When condition code 3 is set, the program The contents of the registers just described are
can simply branch back to the instruction to shown in Figure 7-62 on page 7-71.
continue the conversion. The program need
not determine the number of first-operand or The characters of the second operand are
second-operand bytes that were processed. selected one by one for conversion, proceeding
left to right. The bytes resulting from a conversion
2. The storage-operand references of CONVERT
are placed at the first-operand location, pro-
UNICODE TO UTF-8 may be multiple-access
ceeding left to right. The operation proceeds until
references. (See “Storage-Operand
the first-operand or second-operand location is
Consistency” on page 5-87.)
exhausted, a CPU-determined number of second-
operand characters have been converted, or an
CONVERT UTF-8 TO UNICODE invalid UTF-8 character is encountered in the
second operand.
CUTFU R,R [RRE]
┌─────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Second-Operand Length │ │ Second-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
└─────────────────────────────────────────────────────────────────────────────────┘
Figure 7-62. Register Contents for CONVERT UTF-8 TO UNICODE
When the contents of the first byte of a UTF-8 UTF-8 1111uvw 1xyefgh 1ijklmn 1opqrst
Character
character are in the range C0 to DF hex, the char-
acter is a two-byte character, and it is converted Unicode 1111ab cdefghij 11111kl mnopqrst
to a two-byte Unicode character as follows: Characters
UTF-8 11fghij 1klmnop where zabcd = uvwxy -1
Character
The first two bits in the second, third, and fourth
Unicode fgh ijklmnop bytes of the UTF-8 character are ignored. The
Character high order bit (z) produced by the subtract opera-
The first two bits in the second byte of the UTF-8 tion should be zero but is ignored.
character are ignored.
The second-operand location is considered
When the contents of the first byte of a UTF-8 exhausted when it does not contain at least one
character are in the range E0 to EF hex, the char- remaining byte or when it does not contain at least
acter is a three-byte character, and it is converted the two, three, or four remaining bytes required to
to a two-byte Unicode character as follows: contain the two-, three-, or four-byte UTF-8 char-
acter indicated by the contents of the first
UTF-8 111abcd 1efghij 1klmnop
remaining byte. The first-operand location is con-
Character
sidered exhausted when it does not contain at
Unicode abcdefgh ijklmnop least two remaining bytes or at least four
Character remaining bytes in the case when a four-byte
The first two bits in the second and third bytes of UTF-8 character is to be converted.
the UTF-8 character are ignored.
When the second-operand location is exhausted,
When the contents of the first byte of a UTF-8 condition code 0 is set. When the first-operand
character are in the range F0 to F7 hex, the char- location is exhausted, condition code 1 is set,
acter is a four-byte character, and it is converted except that condition code 0 is set if the second-
to two two-byte Unicode characters (a surrogate operand location also is exhausted. When a
pair) as follows: CPU-determined number of characters have been
processed, condition code 3 is set.
When the contents of the first byte of the next Access exceptions are not recognized for an
UTF-8 character are in the range 80 to BF hex or operand if the R field associated with that operand
F8 to FF hex, the character is invalid, and condi- is odd.
tion code 2 is set.
Resulting Condition Code:
When the conditions for setting condition codes 1
0 Entire second operand processed
and 2 are both met, condition code 2 is set.
1 End of first operand reached
2 Invalid UTF-8 character
When the operation is completed, the contents of
3 CPU-determined number of characters proc-
general register R + 1 are decremented by the
essed
number of bytes converted, and the contents of
general register R are incremented by the same
Program Exceptions:
number. Also, the contents of general register
R + 1 are decremented by the number of bytes Access (fetch, operand 2; store, operand 1)
placed at the first-operand location, and the con- Operation (if the extended-translation facility 1
tents of general register R are incremented by is not installed)
the same number. When general registers R Specification
and R are updated, the bits in them that are not
part of the address may be set to zeros or may Programming Notes:
remain unchanged. 1. When condition code 3 is set, the program
can simply branch back to the instruction to
When condition code 3 is set, the registers have continue the conversion. The program need
been updated so that the instruction, when reexe- not determine the number of first-operand or
cuted, resumes at the next byte locations to be second-operand bytes that were processed.
processed.
2. Bits 0 and 1 of the continuation bytes of
When condition code 2 is set, general register R multiple-byte UTF-8 characters are not
contains the address of the invalid UTF-8 char- checked in order to speed up the conversion.
acter. Thus, invalid continuation bytes are not
detected.
The amount of processing that results in the
3. The storage-operand references of CONVERT
setting of condition code 3 is determined by the
UTF-8 TO UNICODE may be multiple-access
CPU on the basis of improving system perform-
references. (See “Storage-Operand
ance, and it may be a different amount each time
Consistency” on page 5-87.)
the instruction is executed.
┌────────┬────┬────┐ ┌────────────────┬────────┬────┬────┐
│ '1D' │ R │ R │ │ 'B997' │////////│ R │ R │
└────────┴────┴────┘ └────────────────┴────────┴────┴────┘
8 12 15 16 24 28 31
┌────────┬────┬────┬────┬────────────┐ ┌────────┬────┬────┬────┬─/──┬────────┬────────┐
│ '5D' │ R │ X │ B │ D │ │ 'E3' │ R │ X │ B │ D │////////│ '97' │
└────────┴────┴────┴────┴────────────┘ └────────┴────┴────┴────┴─/──┴────────┴────────┘
8 12 16 2 31 8 12 16 2 32 4 47
The 64-bit first operand (the dividend) is divided The 64-bit first operand (the dividend) is divided
by the 32-bit second operand (the divisor), and the by the 32-bit second operand (the divisor), and the
32-bit remainder and quotient are placed at the 32-bit remainder and quotient are placed at the
first-operand location. first-operand location.
The R field designates an even-odd pair of The R field designates an even-odd pair of
general registers and must designate an even- general registers and must designate an even-
numbered register; otherwise, a specification numbered register; otherwise, a specification
exception is recognized. exception is recognized.
The dividend is treated as a 64-bit signed binary The dividend is treated as a 64-bit unsigned
integer. The leftmost 32 bits of the dividend are in binary integer. The leftmost 32 bits of the divi-
general register R, and the rightmost 32 bits are dend are in general register R, and the rightmost
in general register R + 1. The divisor, 32 bits are in general register R + 1.
remainder, and quotient are treated as 32-bit
| signed binary integers. The remainder is placed The divisor, remainder, and quotient are treated
| in general register R, and the quotient is placed as 32-bit unsigned binary integers. The remainder
| in general register R + 1. is placed in general register R, and the quotient
is placed in general register R + 1.
The sign of the quotient is determined by the rules
of algebra, and the remainder has the same sign When the divisor is zero, or when the magnitudes
as the dividend, except that a zero quotient or a of the dividend and divisor are such that the quo-
zero remainder is always positive. tient cannot be expressed as a 32-bit unsigned
binary, a fixed-point-divide exception is recog-
When the divisor is zero, or when the magnitudes nized. This includes the case of division of zero
of the dividend and divisor are such that the quo- by zero.
tient cannot be expressed by a 32-bit signed
binary integer, a fixed-point-divide exception is Condition Code: The code remains unchanged.
recognized. This includes the case of division of
zero by zero. Program Exceptions:
Access (fetch, operand 2 of DL only)
Condition Code: The code remains unchanged. Fixed-point divide
Operation (if z/Architecture is not installed)
Program Exceptions:
Specification
Access (fetch, operand 2 of D only)
Fixed-point divide
Specification
┌────────┬────┬────┬────┬────────────┐
For EXCLUSIVE OR (XI), the first operand is one │ '44' │ R │ X │ B │ D │
byte in length, and only one byte is stored. └────────┴────┴────┴────┴────────────┘
8 12 16 2 31
Resulting Condition Code:
0 Result zero The single instruction at the second-operand
1 Result not zero address is modified by the contents of general
2 -- register R, and the resulting instruction, called
3 -- the target instruction, is executed.
ister R. The ORing does not change either the Programming Notes:
contents of general register R or the instruction in
1. An example of the use of the EXECUTE
storage, and it is effective only for the interpreta-
instruction is given in Appendix A, “Number
tion of the instruction to be executed. When the
Representation and Instruction-Use
R field is zero, no ORing takes place.
Examples.”
The target instruction may be two, four, or six 2. The ORing of eight bits from the general reg-
bytes in length. The execution and exception han- ister with the designated instruction permits
dling of the target instruction are exactly as if the the indirect specification of the length, index,
target instruction were obtained in normal sequen- mask, immediate-data, register, or extended-
tial operation, except for the instruction address op-code field.
and the instruction-length code.
3. The fetching of the target instruction is consid-
ered to be an instruction fetch for purposes of
The instruction address in the current PSW is
program-event recording and for purposes of
increased by the length of EXECUTE. This
reporting access exceptions.
updated address and the instruction-length code
of EXECUTE are used, for example, as part of the 4. An access or specification exception may be
link information when the target instruction is caused by EXECUTE or by the target instruc-
BRANCH AND LINK. When the target instruction tion.
is a successful branching instruction, the instruc-
5. When an interruptible instruction is made the
tion address in the current PSW is replaced by the
target of EXECUTE, the program normally
branch address specified by the target instruction.
should not designate any register updated by
the interruptible instruction as the R, X, or
When the target instruction is in turn EXECUTE,
B register for EXECUTE. Otherwise, on
an execute exception is recognized.
resumption of execution after an interruption,
The effective address of EXECUTE must be even; or if the instruction is refetched without an
otherwise, a specification exception is recognized. interruption, the updated values of these regis-
When the target instruction is two or three ters will be used in the execution of
halfwords in length but can be executed without EXECUTE. Similarly, the program should
fetching its second or third halfword, it is unpre- normally not let the destination field in storage
dictable whether access exceptions are recog- of an interruptible instruction include the
nized for the unused halfwords. Access location of EXECUTE, since the new contents
exceptions are not recognized for the second- of the location may be interpreted when
operand address when the address is odd. resuming execution.
┌────────┬────┬────┬────┬────────────┐
INSERT PROGRAM MASK │ '9A' │ R │ R │ B │ D │
└────────┴────┴────┴────┴────────────┘
IPM R [RRE] 8 12 16 2 31
┌────────────────┬────────┬────┬────┐
│ 'B222' │////////│ R │////│ The set of access registers starting with access
└────────────────┴────────┴────┴────┘ register R and ending with access register R is
16 24 28 31 loaded from the locations designated by the
second-operand address.
The condition code and program mask from the
current PSW are inserted into bit positions 2 and 3 The storage area from which the contents of the
and 4-7, respectively, of general register R. Bits access registers are obtained starts at the location
0 and 1 of the register are set to zeros; bits 8-31 designated by the second-operand address and
are left unchanged. continues through as many storage words as the
number of access registers specified. The access
Condition Code: The code remains unchanged. registers are loaded in ascending order of their
register numbers, starting with access register R
Program Exceptions: None. and continuing up to and including access register
R, with access register 0 following access reg-
LOAD ister 15.
Program Exceptions:
Access (fetch, operand 2)
Specification
example, the two bytes of interest are in bit 24-bit addressing mode, bits 0-7 are set to zeros;
positions 16-31 of the R1 register. in the 31-bit addressing mode, bit 0 is set to zero.
For MOVE (MVC), each operand is processed left When the operands overlap by more than one
to right. When the operands overlap, the result is byte, the contents of the overlapped portion of the
obtained as if the operands were processed one result field are unpredictable.
byte at a time and each result byte were stored
immediately after fetching the necessary operand Condition Code: The code remains unchanged.
byte.
Program Exceptions:
For MOVE (MVI), the first operand is one byte in Access (fetch, operand 2; store, operand 1)
length, and only one byte is stored.
Programming Notes:
Condition Code: The code remains unchanged.
1. An example of the use of the MOVE
Program Exceptions: INVERSE instruction is given in Appendix A,
“Number Representation and Instruction-Use
Access (fetch, operand 2 of MVC; store, Examples.”
operand 1, MVI and MVC)
2. The contents of each byte moved remain
Programming Notes: unchanged.
1. Examples of the use of the MOVE instruction 3. MOVE INVERSE is the only SS-format
are given in Appendix A, “Number Represen- instruction for which the second-operand
tation and Instruction-Use Examples.” address designates the rightmost, instead of
the leftmost, byte of the second operand.
2. It is possible to propagate one byte through
an entire field by having the first operand start 4. The storage-operand references for MOVE
one byte to the right of the second operand. INVERSE may be multiple-access references.
(See “Storage-Operand Consistency” on
page 5-87.)
MOVE INVERSE
MVCIN D(L,B),D(B) [SS] MOVE LONG
┌────────┬────────┬────┬─/──┬────┬─/──┐ MVCL R,R [RR]
│ 'E8' │ L │ B │ D │ B │ D │
└────────┴────────┴────┴─/──┴────┴─/──┘ ┌────────┬────┬────┐
8 16 2 32 36 47 │ 'E' │ R │ R │
└────────┴────┴────┘
8 12 15
The second operand is placed at the first-operand
location with the left-to-right sequence of the bytes
inverted. The second operand is placed at the first-operand
location, provided overlapping of operand
locations would not affect the final contents of the overlap destructively, no movement takes place,
first-operand location. The remaining rightmost and condition code 3 is set.
byte positions, if any, of the first-operand location
are filled with padding bytes. Operands do not overlap destructively, and move-
ment is performed, if the leftmost byte of the first
The R and R fields each designate an even-odd operand does not coincide with any of the second-
pair of general registers and must designate an operand bytes participating in the operation other
even-numbered register; otherwise, a specification than the leftmost byte of the second operand.
exception is recognized. When an operand wraps around from location
2 - 1 (or 2 - 1) to location 0, operand bytes
The location of the leftmost byte of the first in locations up to and including 2 - 1 (or
operand and second operand is designated by the 2 - 1) are considered to be to the left of bytes
contents of general registers R and R, respec- in locations from 0 up.
tively. The number of bytes in the first-operand
and second-operand locations is specified by In the 24-bit addressing mode, wraparound is from
unsigned binary integers in bit positions 8-31 of location 2 - 1 to location 0; in the 31-bit
general registers R + 1 and R + 1, respec- addressing mode, wraparound is from location
tively. Bit positions 0-7 of register R + 1 contain 2 - 1 to location 0.
the padding byte. The contents of bit positions
0-7 of register R + 1 are ignored. In the access-register mode, the contents of
access register R and access register R are
The handling of the addresses in general registers compared. If the R or R field is zero, 32 zeros
R and R is dependent on the addressing mode. are used rather than the contents of access reg-
In the 24-bit addressing mode, the contents of bit ister 0. If all 32 bits of the compared values are
positions 8-31 of registers R and R constitute equal, then the destructive overlap test is made.
the address, and the contents of bit positions 0-7 If all 32 bits of the compared values are not equal,
are ignored. In the 31-bit addressing mode, the destructive overlap is declared not to exist. If, for
contents of bit positions 1-31 of registers R and this case, the operands actually overlap in real
R constitute the address, and the contents of bit storage, it is unpredictable whether the result
position 0 are ignored. reflects the overlap condition.
The contents of the registers just described are When the length specified by bit positions 8-31 of
shown in Figure 7-63 on page 7-85. general register R + 1 is zero, no movement
takes place, and condition code 0 or 1 is set to
The result is obtained as if the movement starts at indicate the relative values of the lengths.
the left end of both fields and proceeds to the
right, byte by byte. The operation is ended when The execution of the instruction is interruptible.
the number of bytes specified by bits 8-31 of When an interruption occurs other than one that
general register R + 1 have been moved into the | follows termination, the contents of general regis-
first-operand location. If the second operand is ters R + 1 and R + 1 are decremented by the
shorter than the first operand, the remaining right- number of bytes moved, and the contents of
most bytes of the first-operand location are filled general registers R and R are incremented by
with the padding byte. the same number, so that the instruction, when
reexecuted, resumes at the point of interruption.
As part of the execution of the instruction, the The leftmost bits which are not part of the address
values of the two length fields are compared for in general registers R and R are set to zeros;
the setting of the condition code, and a check is the contents of bit positions 0-7 of general regis-
made for destructive overlap of the operands. ters R + 1 and R + 1 remain unchanged; and
Operands are said to overlap destructively when the condition code is unpredictable. If the opera-
the first-operand location is used as a source after tion is interrupted during padding, the length field
data has been moved into it, assuming the in general register R + 1 is 0, the address in
inspection for overlap is performed by the use of general register R is incremented by the original
logical operand addresses. When the operands contents of general register R + 1, and general
┌──────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬───────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴───────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌────────┬────────────────────────┐ │
│ R + 1 │////////│ First-Operand Length │ │////////│ First-Operand Length │ │
│ └────────┴───────────────────────┘ └────────┴────────────────────────┘ │
│ 8 31 8 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬───────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴───────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌────────┬────────────────────────┐ │
│ R + 1 │ Pad │ Second-Operand Length │ │ Pad │ Second-Operand Length │ │
│ └────────┴───────────────────────┘ └────────┴────────────────────────┘ │
│ 8 31 8 31 │
│ │
└──────────────────────────────────────────────────────────────────────────────────┘
Figure 7-63. Register Contents for MOVE LONG
registers R and R + 1 reflect the extent of the rent as observed by other CPUs, provided that
padding operation. both operands start on doubleword boundaries,
are an integral number of doublewords in length,
When the first-operand location includes the and do not overlap.
location of the instruction or of EXECUTE, the
instruction may be refetched from storage and As observed by other CPUs and by channel pro-
reinterpreted even in the absence of an inter- grams, that portion of the first operand which is
ruption during execution. The exact point in the filled with the padding byte is not necessarily
execution at which such a refetch occurs is unpre- stored into in a left-to-right direction and may
dictable. appear to be stored into more than once.
Padding byte values of B0 hex and B8 hex may At the completion of the operation, the length in
be used during the nonpadding part of the opera- general register R + 1 is decremented by the
tion by some models, in certain cases, as an indi- number of bytes stored at the first-operand
cation of whether the movement should be per- location, and the address in general register R is
formed bypassing the cache or using the cache, incremented by the same amount. The length in
respectively. Thus, a padding byte of B0 hex indi- general register R + 1 is decremented by the
cates no intention to reference the destination number of bytes moved out of the second-operand
area after the move, and a padding byte of B8 hex location, and the address in general register R is
indicates an intention to reference the destination incremented by the same amount. The leftmost
area. bits which are not part of the address in general
registers R and R are set to zeros, even when
For the nonpadding part of the operation, one or both of the original length values are zeros
accesses to the operands for MOVE LONG are or when condition code 3 is set. The contents of
single-access references. These accesses do not bit positions 0-7 of general registers R + 1 and
necessarily appear to occur in a left-to-right direc- R + 1 remain unchanged.
tion as observed by other CPUs and by channel
programs, unless the padding byte is B1 hex. When condition code 3 is set, no exceptions asso-
During the nonpadding part of the operation, oper- ciated with operand access are recognized. When
ands appear to be accessed doubleword concur- the length of an operand is zero, no access
exceptions for that operand are recognized. Simi- be such that the contents of all result fields
larly, when the second operand is longer than the are unpredictable; in the case of MOVE
first operand, access exceptions are not recog- LONG, this includes the condition code and
nized for the part of the second-operand field that the two even-odd general-register pairs, as
is in excess of the first-operand field. For oper- well as the first-operand location in main
ands longer than 2K bytes, access exceptions are storage. The following are situations that
not recognized for locations more than 2K bytes have actually occurred on one or more
beyond the current location being processed. models:
Access exceptions are not recognized for an
a. When a protection exception occurs on a
operand if the R field associated with that operand
4K-byte block of a first operand which is
is odd. Also, when the R field is odd, PER
several blocks in length, stores to the pro-
storage-alteration events are not recognized, and
tected block are suppressed. However,
no change bits are set.
the move continues into the subsequent
blocks of the first operand, which are not
Resulting Condition Code:
protected. Similarly, an addressing excep-
0 Operand lengths equal; no destructive overlap tion on a block does not necessarily sup-
1 First-operand length low; no destructive press processing of subsequent blocks
overlap which are available.
2 First-operand length high; no destructive
b. Some models may update the general
overlap
registers only when an external, I/O,
3 No movement performed because of destruc-
repressible machine-check, or restart
tive overlap
interruption occurs, or when a program
Program Exceptions: interruption occurs for which it is required
to nullify or suppress a unit of operation.
Access (fetch, operand 2; store, operand 1) Thus, if, after a move into several blocks
Specification of the first operand, an addressing or pro-
tection exception occurs, the general reg-
Programming Notes: isters may remain unchanged.
1. An example of the use of the MOVE LONG 4. When the first-operand length is zero, the
instruction is given in Appendix A, “Number operation consists in setting the condition
Representation and Instruction-Use code and setting the leftmost bits of general
Examples.” registers R and R to zero.
2. MOVE LONG may be used for clearing 5. When the contents of the R and R fields are
storage by setting the padding byte to zero the same, the contents of the designated reg-
and the second-operand length to zero. On isters are incremented or decremented only by
most models, this is the fastest instruction for the number of bytes moved, not by twice the
clearing storage areas in excess of 256 bytes. number of bytes moved. Condition code 0 is
However, the stores associated with this set.
clearing may be multiple-access stores and
should not be used to clear an area if the pos- 6. The following is a detailed description of those
sibility exists that another CPU or a channel cases in which movement takes place, that is,
program will attempt to access and use the where destructive overlap does not exist.
area as soon as it appears to be zero. For In the access-register mode, the contents of
more details, see “Storage-Operand the access registers used are called the effec-
Consistency” on page 5-87. tive space designations. When the effective
3. The program should avoid specification of a space designations are not equal, destructive
length for either operand which would result in overlap is declared not to exist and movement
an addressing exception. Addressing (and occurs. When the effective space desig-
also protection) exceptions may result in ter- nations are the same or when not in the
mination of the entire operation, not just the access-register mode, then the following
current unit of operation. The termination may cases apply.
8. Since the execution of MOVE LONG is inter- The handling of the addresses in general registers
ruptible, the instruction cannot be used for sit- R and R is dependent on the addressing mode.
uations where the program must rely on unin-
terrupted execution of the instruction. Simi- In the 24-bit addressing mode, the contents of bit
larly, the program should normally not let the positions 8-31 of general registers R and R con-
first operand of MOVE LONG include the stitute the address, and the contents of bit posi-
location of the instruction or of EXECUTE tions 0-7 are ignored. In the 31-bit addressing
because the new contents of the location may mode, the contents of bit positions 1-31 of general
be interpreted for a resumption after an inter- registers R and R constitute the address, and
ruption, or the instruction may be refetched the contents of bit position 0 are ignored.
without an interruption.
The second-operand address is not used to
9. Further programming notes concerning inter-
address data; instead, the rightmost eight bits of
ruptible instructions are included in “Interrup-
the second-operand address, bits 24-31, are the
tible Instructions” in Chapter 5, “Program
padding byte. Bits 0-23 of the second-operand
Execution.”
address are ignored.
10. In the access-register mode, access register 0
designates the primary address space regard- The contents of the registers and address just
less of the contents of access register 0. described are shown in Figure 7-64 on
page 7-88.
The result is obtained as if the movement starts at operand location is used as a source after data
the left end of both fields and proceeds to the has been moved into it.
right, byte by byte. The operation is ended when
the number of bytes specified in general register Operands do not overlap destructively if the left-
R + 1 have been placed at the first-operand most byte of the first operand does not coincide
location or when a CPU-determined number of with any of the third-operand bytes participating in
bytes have been placed, whichever occurs first. If the operation other than the leftmost byte of the
the third operand is shorter than the first operand, third operand. When an operand wraps around
the remaining rightmost bytes of the first-operand from location 2 - 1 (or 2 - 1) to location 0,
location are filled with the padding byte. operand bytes in locations up to and including
2 - 1 (or 2 - 1) are considered to be to the
When the operation is completed because the end left of bytes in locations from 0 up.
of the first operand has been reached, the condi-
tion code is set to 0 if the two operand lengths are In the 24-bit addressing mode, wraparound is from
equal, it is set to 1 if the first-operand length is location 2 - 1 to location 0; and, in the 31-bit
less than the third-operand length, or it is set to 2 addressing mode, wraparound is from location
if the first-operand length is greater than the third- 2 - 1 to location 0.
operand length. When the operation is completed
because a CPU-determined number of bytes have When the length specified in general register
been moved without reaching the end of the first R + 1 is zero, no movement takes place, and
operand, condition code 3 is set. condition code 0 or 1 is set to indicate the relative
values of the lengths.
No test is made for destructive overlap, and the
results in the first-operand location are unpredict- Padding byte values of B0 hex and B8 hex may
able when destructive overlap exists. Operands be used during the nonpadding part of the opera-
are said to overlap destructively when the first- tion by some models, in certain cases, as an indi-
┌───────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Third-Operand Address │ │/│ Third-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Third-Operand Length │ │ Third-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌───────────────────────┬────────┐ ┌───────────────────────┬────────┐ │
│ 2nd Op. │///////////////////////│ Pad │ │///////////////////////│ Pad │ │
│ Address └───────────────────────┴────────┘ └───────────────────────┴────────┘ │
│ 24 31 24 31 │
│ │
└───────────────────────────────────────────────────────────────────────────────────┘
Figure 7-64. Register Contents and Second-Operand Address for MOVE LONG EXTENDED
cation of whether the movement should be per- The padding byte may be formed from D(B)
formed bypassing the cache or using the cache, multiple times during the execution of the instruc-
respectively. Thus, a padding byte of B0 hex indi- tion, and the registers designated by R and R
cates no intention to reference the destination may be updated multiple times. Therefore, if B
area after the move, and a padding byte of B8 hex equals R, R + 1, R, or R + 1 and is subject
indicates an intention to reference the destination to change during the execution of the instruction,
area. the results are unpredictable.
For the nonpadding part of the operation, The amount of processing that results in the
accesses to the operands for MOVE LONG are setting of condition code 3 is determined by the
single-access references. These accesses do not CPU on the basis of improving system perform-
necessarily appear to occur in a left-to-right direc- ance, and it may be a different amount each time
tion as observed by other CPUs and by channel the instruction is executed. The maximum amount
programs, unless the padding byte is B1 hex. is approximately 4K bytes of either operand.
During the nonpadding part of the operation, oper-
ands appear to be accessed doubleword concur- At the completion of the operation, the leftmost
rent as observed by other CPUs, provided that bits which are not part of the address in general
both operands start on doubleword boundaries, registers R and R may be set to zeros or may
are an integral number of doublewords in length, remain unchanged from their original values, even
and do not overlap. when one or both of the original length values are
zeros.
As observed by other CPUs and by channel pro-
grams, that portion of the first operand which is When the length of an operand is zero, no access
filled with the padding byte is not necessarily exceptions for that operand are recognized. Simi-
stored into in a left-to-right direction and may larly, when the third operand is longer than the
appear to be stored into more than once. first operand, access exceptions are not recog-
nized for the part of the third-operand field that is
At the completion of the operation, the length in in excess of the first-operand field. For operands
general register R + 1 is decremented by the longer than 4K bytes, access exceptions are not
number of bytes stored at the first-operand recognized for locations more than 4K bytes
location, and the address in general register R is beyond the current location being processed.
incremented by the same amount. The length in Access exceptions are not recognized for an
general register R + 1 is decremented by the operand if the R field associated with that operand
number of bytes moved out of the third-operand is odd. Also, when the R field is odd, PER
location, and the address in general register R is storage-alteration events are not recognized, and
incremented by the same amount. no change bits are set.
MOVE LONG UNICODE The contents of the registers and address just
described are shown in Figure 7-65 on
MVCLU R,R,D(B) [RSE]
page 7-91.
┌────────┬────┬────┬────┬─/──┬────────┬────────┐
│ 'EB' │ R │ R │ B │ D │////////│ '8E' │ The result is obtained as if the movement starts at
└────────┴────┴────┴────┴─/──┴────────┴────────┘
8 12 16 2 32 4 47
the left end of both fields and proceeds to the
right, character by character. The operation is
ended when the number of characters specified by
All or part of the third operand is placed at the the contents of general register R + 1 have been
first-operand location. The remaining rightmost placed at the first-operand location or when a
two-byte character positions, if any, of the first- CPU-determined number of characters have been
operand location are filled with two-byte padding
┌───────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Third-Operand Address │ │/│ Third-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Third-Operand Length │ │ Third-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌───────────────┬────────────────┐ ┌───────────────┬────────────────┐ │
│ 2nd Op. │///////////////│ Pad │ │///////////////│ Pad │ │
│ Address └───────────────┴────────────────┘ └───────────────┴────────────────┘ │
│ 24 31 24 31 │
│ │
└───────────────────────────────────────────────────────────────────────────────────┘
Figure 7-65. Register Contents and Second-Operand Address for MOVE LONG UNICODE
placed, whichever occurs first. If the third operand cide with any of the third-operand characters par-
is shorter than the first operand, the remaining ticipating in the operation other than the leftmost
rightmost character positions of the first-operand character of the third operand. When an operand
location are filled with the two-byte padding char- wraps around from location 2 - 1 (or 2 - 1)
acter. to location 0, operand characters in locations up to
and including 2 - 1 (or 2 - 1) are considered
When the operation is completed because the end to be to the left of characters in locations from 0
of the first operand has been reached, the condi- up.
tion code is set to 0 if the two operand lengths are
equal, it is set to 1 if the first-operand length is In the 24-bit addressing mode, wraparound is from
less than the third-operand length, or it is set to 2 location 2 - 1 to location 0; and, in the 31-bit
if the first-operand length is greater than the third- addressing mode, wraparound is from location
operand length. When the operation is completed 2 - 1 to location 0.
because a CPU-determined number of characters
have been moved without reaching the end of the When the length specified in general register
first operand, condition code 3 is set. R + 1 is zero, no movement takes place, and
condition code 0 or 1 is set to indicate the relative
No test is made for destructive overlap, and the values of the lengths.
results in the first-operand location are unpredict-
able when destructive overlap exists. Operands For the nonpadding part of the operation,
are said to overlap destructively when the first- accesses to the operands for MOVE LONG
operand location is used as a source after data UNICODE are single-access references. These
has been moved into it. accesses do not necessarily appear to occur in a
left-to-right direction as observed by other CPUs
Operands do not overlap destructively if the left- and by channel programs. During the nonpadding
most character of the first operand does not coin- part of the operation, operands appear to be
accessed doubleword concurrent as observed by At the completion of the operation, the leftmost
other CPUs, provided that both operands start on bits which are not part of the address in general
doubleword boundaries, are an integral number of registers R and R may be set to zeros or may
doublewords in length, and do not overlap. remain unchanged from their original values,
including the case when one or both of the original
As observed by other CPUs and by channel pro- length values are zeros.
grams, that portion of the first operand which is
filled with the two-byte padding character is not When the length of an operand is zero, no access
necessarily stored into in a left-to-right direction exceptions for that operand are recognized. Simi-
and may appear to be stored into more than once. larly, when the third operand is longer than the
first operand, access exceptions are not recog-
At the completion of the operation, the length in nized for the part of the third-operand field that is
general register R + 1 is decremented by 2 in excess of the first-operand field. For operands
times the number of characters stored at the first- longer than 4K bytes, access exceptions are not
operand location, and the address in general reg- recognized for locations more than 4K bytes
ister R is incremented by the same amount. The beyond the current location being processed.
length in general register R + 1 is decremented Access exceptions are not recognized for an
by 2 times the number of characters moved out of operand if the R field or length associated with
the third-operand location, and the address in that operand is odd. Also, when the R field or
general register R is incremented by the same length is odd, PER storage-alteration events are
amount. not recognized, and no change bits are set.
┌────────┬────────┬────┬─/──┬────┬─/──┐ ┌────────────────┬────────┬────┬────┐
│ 'D1' │ L │ B │ D │ B │ D │ │ 'B254' │////////│ R │ R │
└────────┴────────┴────┴─/──┴────┴─/──┘ └────────────────┴────────┴────┴────┘
8 16 2 32 36 47 16 24 28 31
The rightmost four bits of each byte in the second This definition applies if move-page facility 1 is
operand are placed in the rightmost bit positions installed. The MOVE PAGE instruction of move-
of the corresponding bytes in the first operand. page facility 2 is defined in Chapter 10, “Control
The leftmost four bits of each byte in the first Instructions.”
operand remain unchanged.
The first operand is replaced by the second
Each operand is processed left to right. When the operand. The first and second operands both are
operands overlap, the result is obtained as if the 4K bytes on 4K-byte boundaries. The results are
operands were processed one byte at a time and indicated in the condition code.
each result byte were stored immediately after
The location of the leftmost byte of the first
fetching the necessary operand bytes.
operand and second operand is designated by the
Condition Code: The code remains unchanged. contents of general registers R and R, respec-
tively.
Program Exceptions:
Access (fetch, operand 2; fetch and store,
operand 1)
The handling of the addresses in general registers Certain conditions prevent data movement from
R and R depends on the addressing mode. In occurring and cause a nonzero condition code to
the 24-bit addressing mode, the contents of bit be set. Data movement is prevented, and condi-
positions 8-19 of a general register, with 12 right- tion code 1 is set, if (1) the second operand is
most zeros appended, are the address, and bits valid in either main storage or expanded storage,
0-7 and 20-31 in the register are ignored. In the but the first operand is invalid in both main
31-bit addressing mode, the contents of bit posi- storage and expanded storage; (2) both operands
tions 1-19 of a general register, with 12 rightmost are valid in expanded storage; or (3) data move-
zeros appended, are the address, and bits 0 and ment between main storage and expanded
20-31 in the register are ignored. storage is due to occur but the translation path for
the expanded-storage operand is locked or the
Bits 16-23 of general register 0 must be 00000001 expanded-storage block containing that operand
binary; otherwise, a specification exception is either is not available or causes an expanded-
recognized. Bits 0-15 and 24-31 of general reg- storage data error. When condition code 1 is set
ister 0 are ignored. because of an expanded-storage data error, the
contents of the first-operand location are unpre-
The contents of the registers just described are dictable. Data movement is prevented, and condi-
shown in Figure 7-66. tion code 2 is set, if the second operand is invalid
in both main storage and expanded storage.
When DAT is on and the page-invalid bit is one in
the page-table entry for an operand, additional When one operand is invalid in both main storage
address translation is performed to determine and expanded storage and an access exception
whether the operand is valid in expanded storage. can be recognized for the other operand, it is
As a result, the replacement of the first operand unpredictable whether a nonzero condition code is
by the second operand may be performed by set or the access exception is recognized.
moving data from main storage to main storage,
from main storage to expanded storage, or from The case when the page-table entry for an
expanded storage to main storage, depending on operand is outside the page table is treated as a
whether and where the operands are valid. When page-translation-exception condition.
4K bytes have been moved, condition code 0 is
set. When data is moved to or from expanded storage,
access-list-controlled, page, and key-controlled
protection apply, and it is unpredictable whether
┌────────────────────────────────────────────────────────────────────────────────────────┐
│ │
│ ┌────────────────┬────────┬────────┐ │
│ GR │////////////////│1│////////│ │
│ └────────────────┴────────┴────────┘ │
│ 16 24 31 │
│ │
│ 24-Bit Addressing Mode │
│ │
│ ┌────────┬────────────┬────────────┐ ┌────────┬────────────┬────────────┐ │
│ R │////////│Op1 Address │////////////│ R │////////│Op2 Address │////////////│ │
│ └────────┴────────────┴────────────┘ └────────┴────────────┴────────────┘ │
│ 8 2 31 8 2 31 │
│ │
│ 31-Bit Addressing Mode │
│ │
│ ┌─┬───────────────────┬────────────┐ ┌─┬───────────────────┬────────────┐ │
│ R │/│ Op1 Address │////////////│ R │/│ Op2 Address │////////////│ │
│ └─┴───────────────────┴────────────┘ └─┴───────────────────┴────────────┘ │
│ 1 2 31 1 2 31 │
│ │
└────────────────────────────────────────────────────────────────────────────────────────┘
Figure 7-66. Register Contents for MOVE PAGE of Move-Page Facility 1
When two or more CPUs move data to the same 2. Monitoring for PER storage-alteration events
expanded-storage block concurrently, the resulting is done using logical addresses. Thus, it
values in the expanded-storage block for each applies to the operands of MOVE PAGE
group of bytes transferred may be from any of the regardless of whether the operands are in
instructions being executed simultaneously. The main storage or expanded storage.
number of bytes transferred as a group is unpre-
dictable. MOVE STRING
Similarly, for concurrent movement to and from MVST R,R [RRE]
the same expanded-storage block, the resulting ┌────────────────┬────────┬────┬────┐
values for each group of bytes moved from │ 'B255' │////////│ R │ R │
expanded storage may be either the old or the └────────────────┴────────┴────┴────┘
16 24 28 31
new values from the expanded-storage block.
When data movement is due to occur between All or part of the second operand is placed in the
main storage and expanded storage, the trans- first-operand location. The operation proceeds
lation path being used for the expanded-storage until the end of the second operand is reached or
operand is set to the locked state. When this data a CPU-determined number of bytes have been
movement is completed successfully, or when moved, whichever occurs first. The
condition code 1 is due to be set because the CPU-determined number is at least one. The
movement cannot be completed successfully, the result is indicated in the condition code.
translation path is set to the unlocked state.
The location of the leftmost byte of the first
Resulting Condition Code: operand and second operand is designated by the
contents of general registers R and R, respec- The amount of processing that results in the
tively. setting of condition code 3 is determined by the
CPU on the basis of improving system perform-
The handling of the addresses in general registers ance, and it may be a different amount each time
R and R is dependent on the addressing mode. the instruction is executed.
In the 24-bit addressing mode, the contents of bit
positions 8-31 of general registers R and R con- Access exceptions for the first and second oper-
stitute the address, and the contents of bit posi- ands are recognized only for that portion of the
tions 0-7 are ignored. In the 31-bit addressing operand that is necessarily used in the operation.
mode, the contents of bit positions 1-31 of general
registers R and R constitute the address, and The storage-operand-consistency rules are the
the contents of bit position 0 are ignored. same as for the MOVE (MVC) instruction, except
that destructive overlap is not recognized.
The end of the second operand is indicated by an
ending character in the last byte position of the Resulting Condition Code:
operand. The ending character to be used to 0 --
determine the end of the second operand is speci- 1 Entire second operand moved; general reg-
fied in bit positions 24-31 of general register 0. Bit ister R updated with address of ending char-
positions 0-23 of general register 0 are reserved acter in first operand; general register R
for possible future extensions and must contain all unchanged
zeros; otherwise, a specification exception is 2 --
recognized. 3 CPU-determined number of bytes moved;
general registers R and R updated with
The operation proceeds left to right and ends as
addresses of next bytes
soon as the second-operand ending character has
been moved or a CPU-determined number of Program Exceptions:
second-operand bytes have been moved, which-
ever occurs first. The CPU-determined number is Access (fetch, operand 2; store, operand 1)
at least one. When the ending character is in the Operation (if the string-instruction facility is not
first byte position of the second operand, only the installed)
ending character is moved. When the ending Specification
character has been moved, condition code 1 is
set. When a CPU-determined number of second- Programming Notes:
operand bytes not including an ending character 1. An example of the use of the MOVE STRING
have been moved, condition code 3 is set. instruction is given in Appendix A, “Number
Destructive overlap is not recognized. If the Representation and Instruction-Use
second operand is used as a source after it has Examples.”
been used as a destination, the results are unpre-
2. When condition code 3 is set, the program
dictable to the extent that an ending character in
can simply branch back to the instruction to
the second operand may not be recognized.
continue the data movement. The program
When condition code 1 is set, the address of the need not determine the number of bytes that
ending character in the first operand is placed in were moved.
general register R, and the contents of general 3. R or R may be zero, in which case general
register R remain unchanged. When condition register 0 is treated as containing an address
code 3 is set, the address of the next byte to be and also the ending character.
processed in the first and second operands is
4. In the access-register mode, access register 0
placed in general registers R and R, respec-
designates the primary address space regard-
tively. Whenever an address is placed in a
less of the contents of access register 0.
general register, bits 0-7 of the register, in the
24-bit mode, or bit 0, in the 31-bit mode, are set to
zeros.
┌────────┬────┬────┬────┬────────────┐
│ '5C' │ R │ X │ B │ D │ MULTIPLY HALFWORD
└────────┴────┴────┴────┴────────────┘
8 12 16 2 31 IMMEDIATE
MHI R,I [RI]
The 32-bit first operand (the multiplicand), which is
┌────────┬────┬────┬────────────────┐
the second word at the first-operand location, is │ 'A7' │ R │'C' │ I │
multiplied by the 32-bit second-operand (the multi- └────────┴────┴────┴────────────────┘
plier), and the 64-bit product is placed at the first- 8 12 16 31
operand location.
The 32-bit first operand (multiplicand) is multiplied
The R field designates an even-odd pair of by the 16-bit second operand (multiplier), and the
general registers and must designate an even- rightmost 32 bits of the product are placed at the
numbered register; otherwise, a specification first-operand location. The second operand is two
exception is recognized. bytes in length and is treated as a 16-bit signed
binary integer.
The multiplicand is treated as a 32-bit signed and the 64-bit product is placed at the first-
binary integer and is replaced by the rightmost 32 operand location.
bits of the signed-binary-integer product. The bits
to the left of the 32 rightmost bits of the product The R field designates an even-odd pair of
are not tested for significance; no overflow indi- general registers and must designate an even-
cation is given. numbered register; otherwise, a specification
exception is recognized.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand Both the multiplicand and the multiplier are treated
sign, except that a zero result is always positive. as 32-bit unsigned binary integers. The multipli-
cand is in general register R + 1. The contents
Condition Code: The code remains unchanged. of general register R are ignored. The product is
a 64-bit unsigned binary integer. Bits 0-31 of the
Program Exceptions: product replace the contents of general register
Access (fetch, operand 2 of MH only) R, and bits 32-63 of the product replace the con-
Operation (MHI if the immediate- tents of general register R + 1. An overflow
and-relative-instruction facility is not installed) cannot occur.
The sign of the product is determined by the rules For OR (OI), the first operand is one byte in
of algebra from the multiplier and multiplicand length, and only one byte is stored.
sign, except that a zero result is always positive.
Resulting Condition Code:
Condition Code: The code remains unchanged.
0 Result zero
1 Result not zero
Program Exceptions:
2 --
Access (fetch, operand 2 of MS only) 3 --
Operation (if the immediate-
and-relative-instruction facility is not installed) Program Exceptions:
Access (fetch, operand 2, O and OC; fetch
OR and store, operand 1, OI and OC)
except the zone bits in the rightmost byte, which PACK ASCII
are treated as a sign.
PKA D(B),D(L,B) [SS]
The sign and digits are moved unchanged to the
first operand and are not checked for valid codes. ┌────────┬────────┬────┬─/──┬────┬─/──┐
│ 'E9' │ L │ B │ D │ B │ D │
The sign is placed in the rightmost four bit posi- └────────┴────────┴────┴─/──┴────┴─/──┘
tions of the rightmost byte of the result field, and 8 16 2 32 36 47
the digits are placed adjacent to the sign and to
each other in the remainder of the result field. The format of the second operand is changed
from ASCII to packed, and the result is placed at
The result is obtained as if the operands were
the first-operand location. The packed format is
processed right to left. When necessary, the
described in Chapter 8, “Decimal Instructions.”
second operand is considered to be extended on
the left with zeros. If the first operand is too short The second-operand bytes are treated as con-
to contain all digits of the second operand, the taining decimal digits, having the binary encoding
remaining leftmost portion of the second operand 0000-1001 for 0-9, in their rightmost four bit posi-
is ignored. Access exceptions for the unused tions. The leftmost four bit positions of a byte are
portion of the second operand may or may not be ignored. The second operand is considered to be
indicated. positive.
When the operands overlap, the result is obtained The implied positive sign (1100 binary) and the
as if each result byte were stored immediately source digits are placed at the first-operand
after fetching the necessary operand bytes. Two location. The source digits are moved unchanged
second-operand bytes are needed for each result and are not checked for valid codes. The sign is
byte, except for the rightmost byte of the result placed in the rightmost four bit positions of the
field, which requires only the rightmost second- rightmost byte of the result field, and the digits are
operand byte. placed adjacent to the sign and to each other in
the remainder of the result field.
Condition Code: The code remains unchanged.
The result is obtained as if the operands were
Program Exceptions:
processed right to left. When necessary, the
Access (fetch, operand 2; store, operand 1) second operand is considered to be extended on
the left with zeros.
Programming Notes:
The length of the first operand is 16 bytes.
1. An example of the use of the PACK instruc-
tion is given in Appendix A, “Number Repre-
The length of the second operand is designated
sentation and Instruction-Use Examples.”
by the contents of the L field. The second-
2. PACK may be used to interchange the two operand length must not exceed 32 bytes (L
hexadecimal digits in one byte by specifying a must be less than or equal to 31); otherwise, a
zero in the L and L fields and the same specification exception is recognized.
address for both operands.
When the length of the second operand is 32
3. To remove the zone bits of all bytes of a field,
bytes, the leftmost byte is ignored.
including the rightmost byte, both operands
should be extended on the right with a dummy The results are unpredictable if the first and
byte, which subsequently should be ignored in second operands overlap in any way.
the result field.
4. The storage-operand references for PACK As observed by other CPUs and by channel pro-
may be multiple-access references. (See grams, the first-operand location is not necessarily
“Storage-Operand Consistency” on stored into in any particular order.
page 5-87.)
Condition Code: The code remains unchanged.
The lock to be used is represented by a program For function codes 0, 8, and 12, the B! and D!
lock token (PLT) whose logical address is speci- fields of the instruction specify the fourth-operand
fied in general register 1. In the 24-bit addressing address.
mode, the PLT address is bits 8-31 of general reg-
ister 1, and bits 0-7 of the register are ignored. In For function codes 1, 5, 9, 13, 16, 17, 20, and 21,
the 31-bit addressing mode, the PLT address is the B! and D! fields of the instruction specify the
bits 1-31 of the register, and bit 0 of the register is address of a parameter list that is used by the
ignored. instruction, and this address is not called the
fourth-operand address. The parameter list con-
The contents of general registers 0 and 1 tains odd-numbered operands, including compar-
described above are as follows: ison and replacement values, and addresses of
even-numbered operands other than the second
GR operand. In the access-register mode, the param-
┌───────────────────────┬─┬────────┐
eter list also contains access-list-entry tokens
││T│ FC │
└───────────────────────┴─┴────────┘ (ALETs) associated with the even-
24 31 numbered-operand addresses.
┌────────────────────────────────┬────────────────────┬────────────┬────────┬────────────────────┐
│Func- │ │ Op3 │ │ Op5 Op7 │
│tion │ │ or │ │ and and │
│Code Operation │ Op1c Op1r Op2a │ Op3c Op3r │ Op4a │ Op6a Op8a PLa │
├────────────────────────────────┼────────────────────┼────────────┼────────┼────────────────────┤
│ Compare and load │ R - D(B) │ R │ D!(B!) │ - - - │
│ │ │ │ │ │
│ 1 Compare and load │ PL - D(B) │ PL │ PL │ - - D!(B!) │
│ │ │ │ │ │
│ 4 Compare and swap │ R R+1 D(B) │ - │ - │ - - - │
│ │ │ │ │ │
│ 5 Compare and swap │ PL PL D(B) │ - │ - │ - - D!(B!) │
│ │ │ │ │ │
│ 8 Double compare and swap │ R R+1 D(B) │ R R+1 │ D!(B!) │ - - - │
│ │ │ │ │ │
│ 9 Double compare and swap │ PL PL D(B) │ PL PL │ PL │ - - D!(B!) │
│ │ │ │ │ │
│ 12 Compare and swap and store│ R R+1 D(B) │ R │ D!(B!) │ - - - │
│ │ │ │ │ │
│ 13 Compare and swap and store│ PL PL D(B) │ PL │ PL │ - - D!(B!) │
│ │ │ │ │ │
│ 16 Compare and swap and │ R R+1 D(B) │ PL │ PL │ PL - D!(B!) │
│ double store │ │ │ │ │
│ │ │ │ │ │
│ 17 Compare and swap and │ PL PL D(B) │ PL │ PL │ PL - D!(B!) │
│ double store │ │ │ │ │
│ │ │ │ │ │
│ 2 Compare and swap and │ R R+1 D(B) │ PL │ PL │ PL PL D!(B!) │
│ triple store │ │ │ │ │
│ │ │ │ │ │
│ 21 Compare and swap and │ PL PL D(B) │ PL │ PL │ PL PL D!(B!) │
│ triple store │ │ │ │ │
├────────────────────────────────┴────────────────────┴────────────┴────────┴────────────────────┤
│Explanation: │
│ │
│ - Operand, value, or address is not used in the operation. │
│ OpNc Operand-N comparison value. │
│ OpNr Operand-N replacement value. │
│ OpNa Operand-N address. │
│ PL Operand, value, or address is in the parameter list. │
│ PLa Parameter-list address. │
└────────────────────────────────────────────────────────────────────────────────────────────────┘
Figure 7-69. Operand and Address Locations for PERFORM LOCKED OPERATION
Figure 7-69 on page 7-106 shows the locations of operand, and access register B! specifies the
the operands (including operand comparison and address space containing a fourth operand or a
replacement values), operand addresses, and parameter list as shown in Figure 7-69. Also, for
parameter-list address used by the instruction. an operand whose address is in the parameter
list, an access-list-entry token (ALET) is in the list
Operand addresses in a parameter list, if used, along with the address and is used in the access-
are in words in the list. In the 24-bit addressing register mode to specify the address space con-
mode, an operand address is bits 8-31 of a word, taining the operand.
and bits 0-7 of the word are ignored. In the 31-bit
addressing mode, an operand address is bits 1-31 In the access-register mode, if an access excep-
of a word, and bit 0 of the word is ignored. tion or PER storage-alteration event is recognized
for an operand whose address is in the parameter
In the access-register mode, access register 1 list, the associated ALET in the parameter list is
specifies the address space containing the loaded into access register R when the exception
program lock token (PLT), access register B or event is recognized. Then, during the resulting
specifies the address space containing the second program interruption, if a value is due to be stored
as the exception access identification at real Parameter List for Function Code 1
location 160 or the PER access identification at ┌─────────────────────────────────┐
real location 161, R is stored. If the instruction │ │
├─────────────────────────────────┤
execution is completed without the recognition of 8 │ Operand-1 Comparison Value │
an exception or event, the contents of access reg- ├─────────────────────────────────┤
ister R are unpredictable. When not in the 16 │ │
access-register mode, or when a parameter list ├─────────────────────────────────┤
containing an ALET is not used, the contents of 24 │ │
├─────────────────────────────────┤
access register R remain unchanged. 32 │ │
├─────────────────────────────────┤
The even-numbered (2, 4, 6, and 8) storage oper- 4 │ Operand 3 │
ands must be designated on an integral boundary, ├─────────────────────────────────┤
which is a word boundary for function codes that 48 │ │
are a multiple of 4 or a doubleword boundary for ├─────────────────────────────────┤
56 │ │
function codes that are one more than a multiple ├────────────────┬────────────────┤
of 4. A parameter list, if used, must be desig- 64 │ │ Operand-4 ALET │
nated on a doubleword boundary. Otherwise, a ├────────────────┼────────────────┤
specification exception is recognized. The 72 │ │ Operand-4 Adr. │
program-lock-token (PLT) address in general reg- └────────────────┴────────────────┘
ister 1 does not have a boundary-alignment
requirement. The first-operand comparison value is compared
to the second operand. When the first-operand
All unused fields in a parameter list, including bits comparison value is equal to the second operand,
0-7 of a word containing an address in the 24-bit the third operand is replaced by the fourth
addressing mode or bit 0 of a word containing an operand, and condition code 0 is set.
address in the 31-bit addressing mode, should
contain all zeros; otherwise, the program may not When the first-operand comparison value is not
operate compatibly in the future. equal to the second operand, the first-operand
comparison value is replaced by the second
A serialization operation is performed immediately operand, and condition code 1 is set.
after the lock is obtained and again immediately
before it is released. However, values fetched Function Codes 4 and 5 (Compare and Swap)
from the parameter list before the lock is obtained
are not necessarily refetched. A serialization The locations of the operands and addresses
operation is not performed if the test bit, bit 23 of used by the instruction are as shown in
general register 0, is one. Figure 7-69 on page 7-106.
In the following figures showing the parameter lists The parameter list used for function code 5 has
for the different function codes, the offsets shown the following format:
on the left are byte values.
Parameter List for Function Code 5
Function Codes 0 and 1 (Compare and Load) ┌─────────────────────────────────┐
│ │
├─────────────────────────────────┤
The locations of the operands and addresses 8 │ Operand-1 Comparison Value │
used by the instruction are as shown in ├─────────────────────────────────┤
Figure 7-69 on page 7-106. 16 │ │
├─────────────────────────────────┤
The parameter list used for function code 1 has 24 │ Operand-1 Replacement Value │
the following format: └─────────────────────────────────┘
the second-operand location, and condition code 0 The first-operand comparison value is compared
is set. to the second operand. When the first-operand
comparison value is equal to the second operand,
When the first-operand comparison value is not the third-operand comparison value is compared
equal to the second operand, the first-operand to the fourth operand. When the third-operand
comparison value is replaced by the second comparison value is equal to the fourth operand
operand, and condition code 1 is set. (after the first-operand comparison value has been
found equal to the second operand), the first-
Function Codes 8 and 9 (Double Compare and operand replacement value is stored at the
Swap) second-operand location, the third-operand
replacement value is stored at the fourth-operand
The locations of the operands and addresses location, and condition code 0 is set.
used by the instruction are as shown in
Figure 7-69 on page 7-106. When the first-operand comparison value is not
equal to the second operand, the first-operand
The parameter list used for function code 9 has comparison value is replaced by the second
the following format: operand, and condition code 1 is set.
Parameter List for Function Code 9
┌─────────────────────────────────┐ When the third-operand comparison value is not
│ │ equal to the fourth operand (after the first-operand
├─────────────────────────────────┤ comparison value has been found equal to the
8 │ Operand-1 Comparison Value │ second operand), the third-operand comparison
├─────────────────────────────────┤ value is replaced by the fourth operand, and con-
16 │ │ dition code 2 is set.
├─────────────────────────────────┤
24 │ Operand-1 Replacement Value │
├─────────────────────────────────┤
32 │ │
├─────────────────────────────────┤
4 │ Operand-3 Comparison Value │
├─────────────────────────────────┤
48 │ │
├─────────────────────────────────┤
56 │ Operand-3 Replacement Value │
├────────────────┬────────────────┤
64 │ │ Operand-4 ALET │
├────────────────┼────────────────┤
72 │ │ Operand-4 Adr. │
└────────────────┴────────────────┘
Function Codes 12 and 13 (Compare and Swap Function Codes 16 and 17 (Compare and Swap
and Store) and Double Store)
The locations of the operands and addresses The locations of the operands and addresses
used by the instruction are as shown in used by the instruction are as shown in
Figure 7-69 on page 7-106. Figure 7-69 on page 7-106.
The parameter list used for function code 13 has The parameter list used for function code 16 has
the following format: the following format:
Parameter List for Function Code 13 Parameter List for Function Code 16
┌─────────────────────────────────┐ ┌─────────────────────────────────┐
│ │ │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
8 │ Operand-1 Comparison Value │ 8 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
16 │ │ 16 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
24 │ Operand-1 Replacement Value │ 24 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
32 │ │ 32 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
4 │ │ 4 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
48 │ │ 48 │ │
├─────────────────────────────────┤ ├────────────────┬────────────────┤
56 │ Operand 3 │ 56 │ │ Operand 3 │
├────────────────┬────────────────┤ ├────────────────┼────────────────┤
64 │ │ Operand-4 ALET │ 64 │ │ Operand-4 ALET │
├────────────────┼────────────────┤ ├────────────────┼────────────────┤
72 │ │ Operand-4 Adr. │ 72 │ │ Operand-4 Adr. │
└────────────────┴────────────────┘ ├────────────────┴────────────────┤
8 │ │
├────────────────┬────────────────┤
The first-operand comparison value is compared 88 │ │ Operand 5 │
to the second operand. When the first-operand ├────────────────┼────────────────┤
comparison value is equal to the second operand, 96 │ │ Operand-6 ALET │
the first-operand replacement value is stored at ├────────────────┼────────────────┤
14 │ │ Operand-6 Adr. │
the second-operand location, the third operand is
└────────────────┴────────────────┘
stored at the fourth-operand location, and condi-
tion code 0 is set.
The parameter list used for function code 17 has Function Codes 20 and 21 (Compare and Swap
the following format: and Triple Store)
Parameter List for Function Code 17 The locations of the operands and addresses
┌─────────────────────────────────┐ used by the instruction are as shown in
│ │
├─────────────────────────────────┤ Figure 7-69 on page 7-106.
8 │ Operand-1 Comparison Value │
├─────────────────────────────────┤ The parameter list used for function code 20 has
16 │ │ the following format:
├─────────────────────────────────┤
24 │ Operand-1 Replacement Value │ Parameter List for Function Code 2
├─────────────────────────────────┤ ┌─────────────────────────────────┐
32 │ │ │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
4 │ │ 8 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
48 │ │ 16 │ │
├─────────────────────────────────┤ ├─────────────────────────────────┤
56 │ Operand 3 │ 24 │ │
├────────────────┬────────────────┤ ├─────────────────────────────────┤
64 │ │ Operand-4 ALET │ 32 │ │
├────────────────┼────────────────┤ ├─────────────────────────────────┤
72 │ │ Operand-4 Adr. │ 4 │ │
├────────────────┴────────────────┤ ├─────────────────────────────────┤
8 │ │ 48 │ │
├─────────────────────────────────┤ ├────────────────┬────────────────┤
88 │ Operand 5 │ 56 │ │ Operand 3 │
├────────────────┬────────────────┤ ├────────────────┼────────────────┤
96 │ │ Operand-6 ALET │ 64 │ │ Operand-4 ALET │
├────────────────┼────────────────┤ ├────────────────┼────────────────┤
14 │ │ Operand-6 Adr. │ 72 │ │ Operand-4 Adr. │
└────────────────┴────────────────┘ ├────────────────┴────────────────┤
8 │ │
├────────────────┬────────────────┤
The first-operand comparison value is compared 88 │ │ Operand 5 │
to the second operand. When the first-operand ├────────────────┼────────────────┤
comparison value is equal to the second operand, 96 │ │ Operand-6 ALET │
the first-operand replacement value is stored at ├────────────────┼────────────────┤
the second-operand location, the third operand is 14 │ │ Operand-6 Adr. │
├────────────────┴────────────────┤
stored at the fourth-operand location, the fifth 112 │ │
operand is stored at the sixth-operand location, ├────────────────┬────────────────┤
and condition code 0 is set. 12 │ │ Operand 7 │
├────────────────┼────────────────┤
When the first-operand comparison value is not 128 │ │ Operand-8 ALET │
equal to the second operand, the first-operand ├────────────────┼────────────────┤
136 │ │ Operand-8 Adr. │
comparison value is replaced by the second └────────────────┴────────────────┘
operand, and condition code 1 is set.
The first-operand comparison value is compared When PERFORM LOCKED OPERATION is exe-
to the second operand. When the first-operand cuted by this CPU and is to use a lock that is
comparison value is equal to the second operand, already held by another CPU due to the execution
the first-operand replacement value is stored at of a PERFORM LOCKED OPERATION instruction
the second-operand location, the third operand is by the other CPU, the execution by this CPU is
stored at the fourth-operand location, the fifth delayed until the lock is no longer held. An exces-
operand is stored at the sixth-operand location, sive delay can be caused only by a machine mal-
the seventh operand is stored at the eighth- function and is a machine-check condition.
operand location, and condition code 0 is set.
The order in which multiple requests for the same
When the first-operand comparison value is not lock are satisfied is undefined.
equal to the second operand, the first-operand
comparison value is replaced by the second A nonrecoverable failure of a CPU while holding a
operand, and condition code 1 is set. lock may result in a machine check, entry into the
check-stop state, or system check stop. The
machine check is processing backup if all oper-
ands are undamaged or processing damage if
register operands are damaged. If a machine When a comparison is made between an operand
check or the check-stop state is the result, either comparison value and an operand before the lock
no storage operands have been changed or else is obtained and indicates inequality, the lock still is
all storage operands that were due to be changed obtained. The condition code is set only as a
have been correctly changed, and, in either case, result of a comparison made while the lock is
the lock has been released. If the storage oper- held. When condition code 1 or 2 is set, the first-
ands are not in either their correct original state or operand comparison value or third-operand com-
their correct final state, the result is system check parison value is replaced only by means of a fetch
stop. of the second operand or fourth operand, respec-
tively, made while the lock is held, as observed by
Storage-Operand References other CPUs.
The accesses to the even-numbered storage oper- In those cases when a store is performed to the
ands appear to be word concurrent, as observed second-operand location and one or more of the
by other CPUs, for function codes that are a mul- fourth-, sixth-, and eighth-operand locations, the
tiple of 4 or doubleword concurrent for function store to the second-operand location is always
codes that are one more than a multiple of 4. The performed last, as observed by other CPUs and
accesses to the doublewords in the parameter list by channel programs.
appear to be doubleword concurrent, as observed
by other CPUs, regardless of the function code. Stores into the parameter list may be performed
while the lock is held or after it has been released.
As observed by other CPUs, all storage operands
may be tested for access exceptions before a lock A serialization operation is performed immediately
is obtained. (A channel program cannot observe after the lock is obtained and again immediately
a lock.) before it is released. However, values fetched
from the parameter list before the lock is obtained
As observed by other CPUs, in all operations are not necessarily refetched. A serialization
except the compare-and-swap operation (which operation is not performed if the test bit, bit 23 of
does not have a fourth operand), the fourth general register 0, is one.
operand is accessed while the lock is held only if
a comparison of the first-operand comparison Access exceptions may be recognized for
value to the second operand while the lock is held parameter-list locations even when the locations
has indicated equality. In these operations, the are not required in the operation. The locations
fourth operand is accessed before the lock is held are those beginning at offset 0 and extending up
only if a comparison of the first-operand compar- through the last location defined for the function
ison value to the second operand has indicated code used.
equality and only if, when DAT is on, an INVALI-
DATE PAGE TABLE ENTRY instruction executed For the compare-and-load and compare-and-swap
by another CPU after the fetch of the second operations, the operation is suppressed on all
operand will not be the cause of a page- addressing and protection exceptions.
translation exception recognized for the fourth
operand, which it will if it sets to one the page- When a nonrecoverable failure of a CPU while
invalid bit in the page-table entry for the fourth holding a lock results in a machine check or entry
operand when this CPU does not have a TLB into the check-stop state, either no storage oper-
entry corresponding to that page-table entry. In ands have been changed or else all storage oper-
the compare-and-swap-and-double-store and ands that were due to be changed have been cor-
compare-and-swap-and-triple-store operations, the rectly changed. The latter may be accomplished
sixth operand, and also the eighth operand in the by repeating stores that were performed success-
triple-store operation, are treated the same as the fully before the failure. Therefore, there may be
fourth operand described above. The reason for two single-access store references (possibly the
this specification about INVALIDATE PAGE store part of an update reference and then a store
TABLE ENTRY is given in programming note 6 on reference) to the store-type operands, with the first
page 7-113. value stored equal to the second value stored.
first-operand and third-operand replace- that the page has been freemained and
ment values) in both operand 2 and that, therefore, a reference to the page
operand 4. With the lock not held, the should result in presentation by the control
PLO instruction fetches operand 2 and program of an addressing exception to the
compares it, with an equal result, to the program making the reference.
first-operand comparison value.
e. CPU 1 attempts to do DAT for operand 4
b. CPU 2 completely executes a PLO.DCS and sees that the page-invalid bit is one.
instruction to dequeue element X, which is CPU 1 performs a program interruption
the only element on the queue, from the indicating a page-translation exception.
queue. The PLO instruction stores 0 in The exception handler sees that the soft-
Qtail and also in Qhead, which is a ware bit indicating freemained is one, and
location containing the address of the first it presents an addressing exception to the
element on the queue. The program on CPU 1 program, which causes an abend
CPU 2 processes the dequeued element of the program.
and then invokes the freemain service of
If CPU 1 had had a TLB entry for the page, its
the control program to deallocate the
PLO instruction would not have been inter-
storage containing the element. The
rupted, and the comparison of the first-
freemain service uses IPTE to set the
operand comparison value to the second
page-invalid bit to one in the page-table
operand while the lock was held would indi-
entry for the page containing element X.
cate that CPU 2 had changed the second
The IPTE instruction immediately sets the
operand. The PLO instruction would set con-
page-invalid bit to one, and then it waits
dition code 1. If CPU 1 did not have a TLB
for the signal that all other CPUs have
entry but IPTE could not set the page-invalid
cleared their TLBs of entries corre-
bit to one while CPU 1 was executing an
sponding to the page.
instruction, CPU 1 could successfully translate
c. CPU 1 attempts to fetch operand 4. CPU the operand-4 address and, again, discover
1 does not have a TLB entry for the while the lock was held that operand 2 had
operand-4 page. CPU 1 signals CPU 2 changed. The case when operand 2 points to
that the CPU 2 IPTE instruction may element X but the freemained bit for the
proceed. element-X page is one is a programming
error.
d. CPU 2 completes its IPTE instruction.
The program on CPU 2 sets a software bit 7. Figure 7-70 on page 7-115 summarizes the
in the page-table entry to one to indicate results of the operation.
┌────────┬────────┬────┬───────────────────────────────────────────────┐
│ │ │Cond│ │
│Op1c=Op2│Op3c=Op4│Code│ Action │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes and 1 (Compare and Load) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ - │ │ Op4 ── Op3 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes 4 and 5 (Compare and Swap) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ - │ │ Op1r ── Op2 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes 8 and 9 (Double Compare and Swap) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ No │ 2 │ Op4 ── Op3c │
│ Yes │ Yes │ │ Op1r ── Op2 Op3r ── Op4 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes 12 and 13 (Compare and Swap and Store) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ - │ │ Op1r ── Op2 Op3 ── Op4 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes 16 and 17 (Compare and Swap and Double Store) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ - │ │ Op1r ── Op2 Op3 ── Op4 │
│ │ │ │ Op5 ── Op6 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│ Function Codes 2 and 21 (Compare and Swap and Triple Store) │
│ │
│ No │ - │ 1 │ Op2 ── Op1c │
│ Yes │ - │ │ Op1r ── Op2 Op3 ── Op4 │
│ │ │ │ Op5 ── Op6 │
│ │ │ │ Op7 ── Op8 │
├────────┴────────┴────┴───────────────────────────────────────────────┤
│Explanation: │
│ │
│ - Not applicable. │
│ OpNc Operand-N comparison value. │
│ OpNr Operand-N replacement value. │
└──────────────────────────────────────────────────────────────────────┘
Figure 7-70. Summary of PERFORM LOCKED OPERATION Results
ROTATE LEFT SINGLE LOGICAL In the 24-bit addressing mode, the contents of bit
positions 8-31 of general registers R and R con-
RLL R,R,D(B) [RSE] stitute the address, and the contents of bit posi-
tions 0-7 are ignored. In the 31-bit addressing
┌────────┬────┬────┬────┬─/──┬────────┬────────┐
│ 'EB' │ R │ R │ B │ D │////////│ '1D' │ mode, the contents of bit positions 1-31 of general
└────────┴────┴────┴────┴─/──┴────────┴────────┘ register R and R constitute the address, and the
8 12 16 2 32 4 47 contents of bit position 0 are ignored.
The third operand is rotated left the number of bits In the access-register mode, the address space
specified by the second-operand address, and the containing the second operand is specified only by
result is placed at the first-operand location. The means of access register R. The contents of
third operand remains unchanged in general reg- access register R are ignored.
ister R.
The character for which the search occurs is spec-
The second-operand address is not used to ified in bit positions 24-31 of general register 0.
address data; its rightmost six bits indicate the Bit positions 0-23 of general register 0 are
number of bit positions to be rotated. The reserved for possible future extensions and must
remainder of the address is ignored. contain all zeros; otherwise, a specification excep-
tion is recognized.
All 32 bits of the third operand participate in a left
shift. Each bit shifted out of the leftmost bit posi- The operation proceeds left to right and ends as
tion of the operand reenters in the rightmost bit soon as the specified character has been found in
position of the operand. the second operand, the address of the next
second-operand byte to be examined equals the
Condition Code: The code remains unchanged. address in general register R, or a
CPU-determined number of second-operand bytes
Program Exceptions: have been examined, whichever occurs first. The
CPU-determined number is at least 256. When
Operation (if z/Architecture is not installed)
the specified character is found, condition code 1
is set. When the address of the next second-
SEARCH STRING operand byte to be examined equals the address
in general register R, condition code 2 is set.
SRST R,R [RRE]
When a CPU-determined number of second-
┌────────────────┬────────┬────┬────┐ operand bytes have been examined, condition
│ 'B25E' │////////│ R │ R │ code 3 is set. When the CPU-determined number
└────────────────┴────────┴────┴────┘ of second-operand bytes have been examined
16 24 28 31
and the address of the next second-operand byte
is in general register R, it is unpredictable
The second operand is searched until a specified whether condition code 2 or 3 is set.
character is found, the end of the second operand
is reached, or a CPU-determined number of bytes When condition code 1 is set, the address of the
have been searched, whichever occurs first. The specified character found in the second operand is
CPU-determined number is at least 256. The placed in general register R, and the contents of
result is indicated in the condition code. general register R remain unchanged. When
condition code 3 is set, the address of the next
The location of the leftmost byte of the second byte to be processed in the second operand is
operand is designated by the contents of general placed in general register R, and the contents of
register R. The location of the first byte after the general register R remain unchanged. When
second operand is designated by the contents of condition code 2 is set, the contents of general
general register R. registers R and R remain unchanged. When-
ever an address is placed in a general register,
The handling of the addresses in general registers bits 0-7 of the register, in the 24-bit mode, or bit 0,
R and R is dependent on the addressing mode. in the 31-bit mode, are set to zeros.
The amount of processing that results in the 4. R or R may be zero, in which case general
setting of condition code 3 is determined by the register 0 is treated as containing an address
CPU on the basis of improving system perform- and also the specified character.
ance, and it may be a different amount each time
5. When it is desired to search a string of
the instruction is executed.
unknown length for its ending character, and
assuming that (1) the string does not start
Access exceptions for the second operand are
below location 256 (or below location 1 if the
recognized only for that portion of the operand
ending character is 00 hex), (2) the string
that is necessarily examined.
does not wrap around to location 0, and (3)
The storage-operand-consistency rules are the the specified character in general register 0
same as for the COMPARE LOGICAL LONG need not be preserved, then R can be zero
instruction. in order to have SEARCH STRING use only
two general registers instead of three.
Resulting Condition Code:
0 -- SET ACCESS
1 Specified character found; general register R SAR R,R [RRE]
updated with address of character; general
register R unchanged ┌────────────────┬────────┬────┬────┐
│ 'B24E' │////////│ R │ R │
2 Specified character not found in entire second └────────────────┴────────┴────┴────┘
operand; general registers R and R 16 24 28 31
unchanged
3 CPU-determined number of bytes searched;
The contents of general register R are placed in
general register R unchanged; general reg-
access register R.
ister R updated with address of next byte
Condition Code: The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2) Program Exceptions: None.
Operation (if the string-instruction facility is not
installed) SET ADDRESSING MODE
Specification
SAM24 [E]
Programming Notes:
┌────────────────┐
1. Examples of the use of the SEARCH STRING │ '1C' │
instruction are given in Appendix A, “Number └────────────────┘
15
Representation and Instruction-Use Examples”
SAM31 [E]
The instruction address in the PSW is updated Condition Code: The code is set as specified by
under the control of the new addressing mode, as bits 2 and 3 of general register R.
follows. The value 2 (the instruction length) is
added to the contents of bit positions 33-63 of the Program Exceptions: None.
PSW, or the value 4 is added if the instruction is
the target of EXECUTE. In either case, a carry Programming Notes:
out of bit position 33 is ignored. Then bits 33-39 1. Bits 2-7 of the general register may have been
of the PSW are set to zeros if the new addressing loaded from the PSW by execution of
mode is the 24-bit mode. BRANCH AND LINK in the 24-bit addressing
mode or by execution of INSERT PROGRAM
The instruction is completed only if the new MASK in either the 24-bit or 31-bit addressing
addressing mode and the unupdated instruction mode.
address in the PSW are a valid combination.
When the new addressing mode is to be the 24-bit 2. SET PROGRAM MASK permits setting of the
mode, bits 33-39 of the unupdated PSW must be condition code and the mask bits in either the
all zeros; otherwise, a specification exception is problem state or the supervisor state.
recognized. 3. The program should take into consideration
that the setting of the program mask can have
Condition Code: The code remains unchanged. a significant effect on subsequent execution of
the program. Not only do the four mask bits
Program Exceptions:
control whether the corresponding inter-
Operation (if z/Architecture is not installed) ruptions occur, but the exponent-underflow
Specification (SAM24 only) and significance masks also determine the
result which is obtained.
Programming Note: Checking the unupdated
instruction address prevents completion in a major
case: the instruction is located at address 2 or SHIFT LEFT DOUBLE
above and the new addressing mode is to be the
SLDA R,D(B) [RS]
24-bit mode. In this case, if the instruction were
completed, the updating of the instruction address ┌────────┬────┬────┬────┬────────────┐
under the control of the new addressing mode │ '8F' │ R │////│ B │ D │
would cause one or more leftmost bits of the └────────┴────┴────┴────┴────────────┘
8 12 16 2 31
address to be set to zeros, which would cause the
next instruction to be fetched from other than the
next sequential location. This action is sometimes The 63-bit numeric part of the signed first operand
called a “wild branch.” A wild branch still can is shifted left the number of bits specified by the
occur if the instruction is located at 2 - 2, or at second-operand address, and the result is placed
2 - 4 if EXECUTE is used. at the first-operand location.
shift in the same manner as the other numeric The 64-bit first operand is shifted left the number
bits. Zeros are supplied to the vacated bit posi- of bits specified by the second-operand address,
tions on the right. and the result is placed at the first-operand
location.
If one or more bits unlike the sign bit are shifted
out of bit position 1 of the even-numbered register, The R field designates an even-odd pair of
an overflow occurs, and condition code 3 is set. If general registers and must designate an even-
the fixed-point-overflow mask bit is one, a program numbered register; otherwise, a specification
interruption for fixed-point overflow occurs. exception is recognized.
mask bit is one, a program interruption for fixed- inspected and are lost. Zeros are supplied to the
point overflow occurs. vacated bit positions on the right.
SHIFT RIGHT DOUBLE LOGICAL The first operand is treated as a 32-bit signed
binary integer. The sign of the first operand
SRDL R,D(B) [RS] remains unchanged. All 31 numeric bits of the
operand participate in the right shift. Bits shifted
┌────────┬────┬────┬────┬────────────┐
│ '8C' │ R │////│ B │ D │ out of bit position 31 are not inspected and are
└────────┴────┴────┴────┴────────────┘ lost. Bits equal to the sign are supplied to the
8 12 16 2 31 vacated bit positions on the left.
The 64-bit first operand is shifted right the number Resulting Condition Code:
of bits specified by the second-operand address, 0 Result zero
and the result is placed at the first-operand 1 Result less than zero
location. 2 Result greater than zero
3 --
The R field designates an even-odd pair of
general registers and must designate an even- Program Exceptions: None.
numbered register; otherwise, a specification
exception is recognized. Programming Notes:
1. A right shift of one bit position is equivalent to
The second-operand address is not used to
division by 2 with rounding downward. When
address data; its rightmost six bits indicate the
an even number is shifted right one position,
number of bit positions to be shifted. The
the result is equivalent to dividing the number
remainder of the address is ignored.
by 2. When an odd number is shifted right
All 64 bits of the first operand participate in the one position, the result is equivalent to
shift. Bits shifted out of bit position 31 of the odd- dividing the next lower number by 2. For
numbered register are not inspected and are lost. example, +5 shifted right by one bit position
Zeros are supplied to the vacated bit positions on yields +2, whereas -5 yields -3.
the left. 2. Shift amounts from 31 to 63 cause the entire
numeric part to be shifted out of the register,
Condition Code: The code remains unchanged. leaving a result of -1 or zero, depending on
whether or not the initial contents were nega-
Program Exceptions: tive.
Specification
SHIFT RIGHT SINGLE LOGICAL
SHIFT RIGHT SINGLE
SRL R,D(B) [RS]
SRA R,D(B) [RS]
┌────────┬────┬────┬────┬────────────┐
│ '88' │ R │////│ B │ D │
┌────────┬────┬────┬────┬────────────┐
└────────┴────┴────┴────┴────────────┘
│ '8A' │ R │////│ B │ D │
8 12 16 2 31
└────────┴────┴────┴────┴────────────┘
8 12 16 2 31
The 32-bit first operand is shifted right the number
The 31-bit numeric part of the signed first operand of bits specified by the second-operand address,
is shifted right the number of bits specified by the and the result is placed at the first-operand
second-operand address, and the result is placed location.
at the first-operand location.
The second-operand address is not used to
The second-operand address is not used to address data; its rightmost six bits indicate the
address data; its rightmost six bits indicate the number of bit positions to be shifted. The
number of bit positions to be shifted. The remainder of the address is ignored.
remainder of the address is ignored.
All 32 bits of the first operand participate in the
shift. Bits shifted out of bit position 31 are not
inspected and are lost. Zeros are supplied to the Program Exceptions:
vacated bit positions on the left.
Access (store, operand 2)
Specification
Condition Code: The code remains unchanged.
┌────────┬────┬────┬────┬────────────┐ ┌────────┬────┬────┬────┬────────────┐
│ '9B' │ R │ R │ B │ D │ │ 'BE' │ R │ M │ B │ D │
└────────┴────┴────┴────┴────────────┘ └────────┴────┴────┴────┴────────────┘
8 12 16 2 31 8 12 16 2 31
The contents of the set of access registers starting Bytes selected from general register R under
with access register R and ending with access control of a mask are placed at contiguous byte
register R are stored at the locations designated locations beginning at the second-operand
by the second-operand address. address.
The storage area where the contents of the The contents of the M field are used as a mask.
access registers are placed starts at the location These four bits, left to right, correspond one for
designated by the second-operand address and one with the four bytes, left to right, of general
continues through as many storage words as the register R. The bytes corresponding to ones in
number of access registers specified. The con- the mask are placed in the same order at succes-
tents of the access registers are stored in sive and contiguous storage locations beginning at
ascending order of their register numbers, starting the second-operand address. When the mask is
with access register R and continuing up to and not zero, the length of the second operand is
including access register R, with access register equal to the number of ones in the mask. The
0 following access register 15. The contents of contents of the general register remain
the access registers remain unchanged. unchanged.
The second operand must be designated on a When the mask is not zero, exceptions associated
word boundary; otherwise, a specification excep- with storage-operand accesses are recognized
tion is recognized. only for the number of bytes specified by the
mask.
Condition Code: The code remains unchanged.
When the mask is zero, the single byte designated STORE CLOCK
by the second-operand address remains
unchanged; however, on some models, the con- STCK D(B) [S]
tents may be fetched and subsequently stored
┌────────────────┬────┬────────────┐
back unchanged at the same storage location. │ 'B25' │ B │ D │
This update appears to be an interlocked-update └────────────────┴────┴────────────┘
reference as observed by other CPUs. 16 2 31
Condition Code: The code remains unchanged. The current value of bits 0-63 of the TOD clock is
stored in the eight-byte field designated by the
Program Exceptions:
second-operand address, provided the clock is in
Access (store, operand 2) the set, stopped, or not-set state.
time-of-day and calendar indication. Condition Zeros are stored at the operand location when the
code 1 indicates that the clock value is the clock is in the error state or the not-operational
elapsed time since the power for the clock state.
was turned on. In this case, the value may be
used in elapsed-time measurements but is not The quality of the clock value stored by the
a valid time-of-day indication. Condition instruction is indicated by the resultant condition-
codes 2 and 3 mean that the value provided code setting.
by STORE CLOCK cannot be used for time
measurement or indication. A serialization function is performed before the
value of the clock is fetched and again after the
3. If a problem program written for ESA/390 is to value is placed in storage.
be executed also on a system in the
System/370 mode, then the program should Resulting Condition Code:
take into account that, in the System/370
mode, the value stored when the condition 0 Clock in set state
code is 2 is not necessarily zero. 1 Clock in not-set state
2 Clock in error state
3 Clock in stopped state or not-operational state
STORE CLOCK EXTENDED
Program Exceptions:
STCKE D(B) [S]
Access (store, operand 2)
┌────────────────┬────┬────────────┐
│ 'B278' │ B │ D │ Operation (if the extended-TOD-clock facility is
└────────────────┴────┴────────────┘ not installed)
16 2 31
Programming Notes:
The current value of bits 0-103 of the TOD clock 1. Condition code 0 normally indicates that the
is stored in byte positions 1-13 of the sixteen-byte clock has been set by the control program.
field designated by the second-operand address, Accordingly, the value may be used in
provided the clock is in the set, stopped, or not-set elapsed-time measurements and as a valid
state. Zeros are stored in byte position 0. The time-of-day and calendar indication. Condition
TOD programmable field, bits 16-31 of the TOD code 1 indicates that the clock value is the
programmable register, is stored in byte positions elapsed time since the power for the clock
14 and 15. was turned on. In this case, the value may be
used in elapsed-time measurements but is not
The operand just described has the following a valid time-of-day indication. Condition
format: codes 2 and 3 mean that the value provided
┌─────┬─────────────────────────────┬──────────┐ by STORE CLOCK EXTENDED cannot be
│ │ │Programm- │ used for time measurement or indication.
│Zeros│ TOD Clock │able Field│
└─────┴─────────────────────────────┴──────────┘ 2. Programming notes beginning on page 4-33
8 112 127
show hex values related to the TOD clock as
it is stored by the STORE CLOCK instruction.
When the clock is stopped, zeros are stored in the
Notes 3-5, below, are repetitions of those
clock value in positions to the right of the right-
notes except with the text and hex values
most bit position that is incremented when the
adjusted so they apply to bits 0-71 of the
clock is running. The programmable field still is
value stored by STORE CLOCK EXTENDED.
stored.
3. The following chart shows the time interval
When the value of a running clock is stored, the between instants at which various bits of the
value in bit positions 64-103 of the clock (bit posi- TOD-clock value stored by STORE CLOCK
tions 72-111 of the storage operand) is always EXTENDED are stepped. This time value
nonzero; this ensures that values stored by may also be considered as the weighted time
STORE CLOCK EXTENDED are unique when value that the bit, when one, represents. The
compared with values stored by STORE CLOCK
and extended with zeros.
┌────────┬────┬────┬────┬────────────┐ ┌────────┬────┬────┬────┬─/──┬────────┬────────┐
│ '4' │ R │ X │ B │ D │ │ 'E3' │ R │ X │ B │ D │////////│ '3F' │
└────────┴────┴────┴────┴────────────┘ └────────┴────┴────┴────┴─/──┴────────┴────────┘
8 12 16 2 31 8 12 16 2 32 4 47
Program Exceptions:
The contents of the set of general registers
Access (store, operand 2)
starting with general register R and ending with
Operation (if z/Architecture is not installed)
general register R are placed in the storage area
beginning at the location designated by the
Programming Notes:
second-operand address and continuing through
as many locations as needed. 1. The instruction can be used to convert two or
four bytes from a “little-endian” format to a
The general registers are stored in the ascending “big-endian” format, or vice versa. In the big-
order of their register numbers, starting with endian format, the bytes in a left-to-right
general register R and continuing up to and sequence are in the order most significant to
including general register R, with general register least significant. In the little-endian format,
0 following general register 15. the bytes are in the order least significant to
most significant. For example, the bytes
Condition Code: The code remains unchanged. ABCD in the big-endian format are DCBA in
the little-endian format.
Program Exceptions:
2. The storage-operand references of STORE
Access (store, operand 2) REVERSED may be multiple-access refer-
Programming Note: An example of the use of ences. (See “Storage-Operand Consistency”
the STORE MULTIPLE instruction is given in on page 5-87.)
Appendix A, “Number Representation and
Instruction-Use Examples.”
┌────────┬────┬────┐ ┌────────┬────┬────┬────┬────────────┐
│ '1B' │ R │ R │ │ '4B' │ R │ X │ B │ D │
└────────┴────┴────┘ └────────┴────┴────┴────┴────────────┘
8 12 15 8 12 16 2 31
SL R,D(X,B) [RX]
┌────────┬────┬────┬────┬────────────┐
│ '5F' │ R │ X │ B │ D │
└────────┴────┴────┴────┴────────────┘
8 12 16 2 31
The second operand is subtracted from the first SLB R,D(X,B) [RXE]
operand, and the difference is placed at the first- ┌────────┬────┬────┬────┬─/──┬────────┬────────┐
operand location. The operands and the differ- │ 'E3' │ R │ X │ B │ D │////////│ '99' │
ence are treated as 32-bit unsigned binary inte- └────────┴────┴────┴────┴─/──┴────────┴────────┘
gers. 8 12 16 2 32 4 47
Resulting Condition Code: The second operand and the borrow are sub-
0 -- tracted from the first operand, and the difference
1 Result not zero; borrow is placed at the first-operand location. The oper-
2 Result zero; no borrow ands, the borrow, and the difference are treated
3 Result not zero; no borrow as 32-bit unsigned binary integers.
┌────────┬────────┐ ┌────────┬────────┬────┬────────────┐
│ 'A' │ I │ │ '93' │////////│ B │ D │
└────────┴────────┘ └────────┴────────┴────┴────────────┘
8 15 8 16 2 31
The instruction causes a supervisor-call inter- The leftmost bit (bit 0) of the byte located at the
ruption, with the I field of the instruction providing second-operand address is used to set the condi-
the rightmost byte of the interruption code. tion code, and then the byte is set to all ones.
Bits 8-15 of the instruction, with eight zeros The byte in storage is set to all ones as it is
appended on the left, are placed in the supervisor- fetched for the testing of bit 0. This update
call interruption code that is stored in the course appears to be an interlocked-update reference as
of the interruption. See “Supervisor-Call observed by other CPUs.
Interruption” on page 6-46.
A serialization function is performed before the
A serialization and checkpoint-synchronization byte is fetched and again after the storing of all
function is performed. ones.
┌────────┬────────┬────┬────────────┐ ┌────────┬────┬────┬────────────────┐
│ '91' │ I │ B │ D │ │ 'A7' │ R │'1' │ I │
└────────┴────────┴────┴────────────┘ └────────┴────┴────┴────────────────┘
8 16 2 31 8 12 16 31
A mask is used to select bits of the first operand, A mask is used to select bits of the first operand,
and the result is indicated in the condition code. and the result is indicated in the condition code.
The byte of immediate data, I, is used as an The contents of the I field are used as a 16-bit
eight-bit mask. The bits of the mask are made to mask. The bits of the mask are made to corre-
correspond one for one with the bits of the byte in spond one for one with 16 bits of the first operand.
storage designated by the first-operand address. For TEST UNDER MASK HIGH, the mask is
made to correspond with bits 0-15 of the first
A mask bit of one indicates that the storage bit is operand. For TEST UNDER MASK LOW, the
to be tested. When the mask bit is zero, the mask is made to correspond with bits 16-31 of the
storage bit is ignored. When all storage bits thus first operand.
selected are zero, condition code 0 is set. Condi-
tion code 0 is also set when the mask is all zeros. A mask bit of one indicates that the first-operand
When the selected bits are all ones, condition bit is to be tested. When the mask bit is zero, the
code 3 is set; otherwise, condition code 1 is set. first-operand bit is ignored. When all first-operand
bits thus selected are zero, condition code 0 is
Access exceptions associated with the storage set. Condition code 0 is also set when the mask
operand are recognized for one byte even when is all zeros. When the selected bits are mixed
the mask is all zeros. zeros and ones, condition code 1 is set if the left-
most selected bit is zero, or condition code 2 is
Resulting Condition Code: set if the leftmost selected bit is one. When the
0 Selected bits all zeros; or mask bits all zeros selected bits are all ones, condition code 3 is set.
1 Selected bits mixed zeros and ones
2 -- Resulting Condition Code:
3 Selected bits all ones 0 Selected bits all zeros; or mask bits all zeros
1 Selected bits mixed zeros and ones, and left-
Program Exceptions: most is zero
Access (fetch, operand 1) 2 Selected bits mixed zeros and ones, and left-
most is one
Programming Note: An example of the use of 3 Selected bits all ones
the TEST UNDER MASK instruction is given in
Appendix A, “Number Representation and Program Exceptions:
Instruction-Use Examples.”
Operation (if the immediate-
and-relative-instruction facility is not installed)
TEST UNDER MASK HIGH
Programming Note: When the mask selects
TMH R,I [RI] exactly two bits, the two selected bits effectively
are loaded into the condition code.
┌────────┬────┬────┬────────────────┐
│ 'A7' │ R │'' │ I │
└────────┴────┴────┴────────────────┘
8 12 16 31
The bytes of the first operand are selected one by Program Exceptions:
one for translation, proceeding from left to right.
Access (fetch, operands 1 and 2)
The first operand remains unchanged in storage.
Calculation of the address of the function byte is
Programming Notes:
performed as in the TRANSLATE instruction. The
function byte retrieved from the list is inspected for 1. An example of the use of the TRANSLATE
a value of zero. AND TEST instruction is given in Appendix A,
“Number Representation and Instruction-Use
When the function byte is zero, the operation pro- Examples.”
ceeds with the next byte of the first operand.
2. TRANSLATE AND TEST may be used to
When the first-operand field is exhausted before a
scan the first operand for characters with
nonzero function byte is encountered, the opera-
special meaning. The second operand, or list,
tion is completed by setting condition code 0. The
is set up with all-zero function bytes for those
contents of general registers 1 and 2 remain
characters to be skipped over and with
unchanged.
nonzero function bytes for the characters to
be detected.
When the function byte is nonzero, the operation
is completed by inserting the function byte in
general register 2 and the related argument TRANSLATE EXTENDED
address in general register 1. This address points
TRE R,R [RRE]
to the argument byte last translated. The function
byte replaces bits 24-31 of general register 2, and ┌────────────────┬────────┬────┬────┐
bits 0-23 of this register remain unchanged. In the │ 'B2A5' │////////│ R │ R │
24-bit addressing mode, the address replaces bits └────────────────┴────────┴────┴────┘
16 24 28 31
8-31 of general register 1, and bits 0-7 of this reg-
ister remain unchanged. In the 31-bit addressing
mode, the address replaces bits 1-31 of general The bytes of the first operand are compared to a
register 1, and bit 0 of this register is set to zero. test byte in general register 0 and, unless an
equal comparison occurs, are used as eight-bit
When the function byte is nonzero, either condi- arguments to reference a 256-byte translation
tion code 1 or 2 is set, depending on whether the table designated by the second-operand address.
argument byte is the rightmost byte of the first Each function byte selected from the second
operand. Condition code 1 is set if one or more operand replaces the corresponding argument in
argument bytes remain to be translated. Condi- the first operand. The operation proceeds until a
tion code 2 is set if no more argument bytes first-operand byte equal to the test byte is
remain.
encountered, the end of the first operand is The operation proceeds until a first-operand byte
reached, or a CPU-determined number of bytes equal to the test byte is encountered, the first-
have been processed, whichever occurs first. The operand location is exhausted, or a
result is indicated in the condition code. CPU-determined number of first-operand bytes
have been processed.
The R field designates an even-odd pair of
general registers and must designate an even- When a first-operand byte equal to the test byte is
numbered register; otherwise, a specification encountered, condition code 1 is set. When the
exception is recognized. first-operand location is exhausted without finding
a byte equal to the test byte, condition code 0 is
The location of the leftmost byte of the first set. When a CPU-determined number of bytes
operand and second operand is designated by the have been processed, condition code 3 is set.
contents of general registers R and R, respec- Condition code 3 may be set even when the next
tively. The number of bytes in the first-operand byte to be processed is equal to the test byte or
location is specified by bits 0-31 of general reg- when the first-operand location is exhausted. In
ister R + 1. The contents of general register these cases, condition code 1 or 0, respectively,
R + 1 are treated as a 32-bit unsigned binary will be set when the instruction is executed again.
integer.
If the operation is completed with condition code
The handling of the addresses in general registers 0, the contents of general register R are incre-
R and R is dependent on the addressing mode. mented by the contents of general register R + 1
and then the contents of general register R + 1
In the 24-bit addressing mode, the contents of bit are set to zero. If the operation is completed with
positions 8-31 of general registers R and R con- condition code 1, the contents of general register
stitute the address, and the contents of bit posi- R + 1 are decremented by the number of bytes
tions 0-7 are ignored. In the 31-bit addressing processed before the first-operand byte equal to
mode, the contents of bit positions 1-31 of the reg- the test byte was encountered, and the contents
isters constitute the address, and the contents of of general register R are incremented by the
bit position 0 are ignored. same number, so that general register R contains
the address of the equal byte. If the operation is
The test byte is in bit positions 24-31 of general completed with condition code 3, the contents of
register 0, and the contents of bit positions 0-23 of general register R + 1 are decremented by the
this register are ignored. number of bytes processed, and the contents of
general register R are incremented by the same
The contents of the registers just described are
number, so that the instruction, when reexecuted,
shown in Figure 7-71 on page 7-134.
resumes at the next byte to be processed. When
general register R is updated, the bits in it that
The bytes of the first operand are selected one by
are not part of the address may be set to zeros or
one for translation, proceeding left to right. Each
may remain unchanged from their original values.
argument byte is first compared to the test byte in
general register 0. If the result is an equal com-
The amount of processing that results in the
parison, the operation is completed. If the argu-
setting of condition code 3 is determined by the
ment byte is not equal to the test byte, the argu-
CPU on the basis of improving system perform-
ment byte is added to the initial second-operand
ance, and it may be a different amount each time
address. The addition is performed following the
the instruction is executed.
rules for address arithmetic, with the argument
byte treated as an eight-bit unsigned binary When the R register is the same register as the
integer and extended with zeros on the left. The R register, the results are unpredictable.
sum is used as the address of the function byte,
which then replaces the original argument byte. When the R register or the R register is zero,
The second operand is not altered unless an the results are unpredictable.
overlap occurs.
When the second operand overlaps the first
operand, the results are unpredictable.
┌─────────────────────────────────────────────────────────────────────────────────┐
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ First-Operand Length │ │ First-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ Second-Operand Address│ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌───────────────────────┬────────┐ ┌───────────────────────┬────────┐ │
│ GR │///////////////////////│ Test │ │///////////////////////│ Test │ │
│ └───────────────────────┴────────┘ └───────────────────────┴────────┘ │
│ 24 31 24 31 │
└─────────────────────────────────────────────────────────────────────────────────┘
31-bit addressing mode, the contents of bit posi- The length of the translation table designated by
tions 1-31 of registers R and R and 1-28 or 1-19 the address contained in general register 1 is as
of 1 constitute the address, and the contents of bit follows:
position 0 are ignored.
For TRANSLATE ONE TO ONE, the
translation-table length is 256 bytes; each of
The contents of the registers just described are
the 256 function characters is a single byte.
shown in Figure 7-72.
For TRANSLATE ONE TO TWO, the
In the access-register mode, the contents of translation-table length is 512 bytes; each of
access registers R, R, and 1 are used for the 256 function characters is a double byte.
accessing the first operand, second operand, and
For TRANSLATE TWO TO ONE, the
translation table, respectively.
translation-table length is 65,536 (64K) bytes;
each of the 64K function characters is a single
byte.
┌────────────────────────────────────────────────────────────────────────────────────┐
│ │
│ For TRANSLATE ONE TO ONE For TRANSLATE ONE TO TWO │
│ and TRANSLATE TWO TO ONE and TRANSLATE TWO TO TWO │
│ ┌───────────────────────┬────────┐ ┌───────────────┬────────────────┐ │
│ GR │///////////////////////│ Test │ │///////////////│ Test │ │
│ └───────────────────────┴────────┘ └───────────────┴────────────────┘ │
│ 24 31 16 31 │
│ │
├────────────────────────────────────────────────────────────────────────────────────┤
│ │
│ 24-Bit Addressing Mode 31-Bit Addressing Mode │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│ First-Operand Address │ │/│ First-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ ┌────────────────────────────────┐ ┌────────────────────────────────┐ │
│ R + 1 │ Second-Operand Length │ │ Second-Operand Length │ │
│ └────────────────────────────────┘ └────────────────────────────────┘ │
│ 31 31 │
│ │
│ ┌────────┬───────────────────────┐ ┌─┬──────────────────────────────┐ │
│ R │////////│Second-Operand Address │ │/│ Second-Operand Address │ │
│ └────────┴───────────────────────┘ └─┴──────────────────────────────┘ │
│ 8 31 1 31 │
│ │
│ For TRANSLATE ONE TO ONE For TRANSLATE ONE TO ONE │
│ and TRANSLATE ONE TO TWO and TRANSLATE ONE TO TWO │
│ ┌────────┬───────────────────┬───┐ ┌─┬──────────────────────────┬───┐ │
│ GR1 │////////│Trans.-Table Addr. │///│ │/│Translation-Table Address │///│ │
│ └────────┴───────────────────┴───┘ └─┴──────────────────────────┴───┘ │
│ 8 29 31 1 29 31 │
│ │
│ For TRANSLATE TWO TO ONE For TRANSLATE TWO TO ONE │
│ and TRANSLATE TWO TO TWO and TRANSLATE TWO TO TWO │
│ ┌────────┬──────────┬────────────┐ ┌─┬─────────────────┬────────────┐ │
│ GR1 │////////│Tr.Tab.Adr│////////////│ │/│Trans.-Table Addr│////////////│ │
│ └────────┴──────────┴────────────┘ └─┴─────────────────┴────────────┘ │
│ 8 2 31 1 2 31 │
└────────────────────────────────────────────────────────────────────────────────────┘
Figure 7-72. Register Contents for TRANSLATE ONE TO ONE, TRANSLATE ONE TO TWO, TRANSLATE TWO
TO ONE, and TRANSLATE TWO TO TWO
For TRANSLATE TWO TO TWO, the ered, the second-operand location is exhausted,
translation-table length is 131,072 (128K) or a CPU-determined number of second-operand
bytes; each of the 64K function characters is a characters have been processed.
double byte.
When a selected function character equal to the
The characters of the second operand are test character is encountered, condition code 1 is
selected one by one for translation, proceeding left set. When the second-operand location is
to right. Each argument character is added to the exhausted without finding a selected function char-
initial translation-table address. The addition is acter equal to the test character, condition code 0
performed following the rules for address arith- is set. When a CPU-determined number of char-
metic, with the argument character treated as acters have been processed, condition code 3 is
follows: set. Condition code 3 may be set even when the
next character to be processed results in a func-
For TRANSLATE ONE TO ONE, the argu-
tion character equal to the test character or when
ment character is treated as an eight-bit
the second-operand location is exhausted. In
unsigned binary integer extended on the left
these cases, condition code 1 or 0, respectively,
with 24 zeros.
will be set when the instruction is executed again.
For TRANSLATE ONE TO TWO, the argu-
ment character is treated as an eight-bit If the operation is completed with condition code
unsigned binary integer extended on the right 0, the contents of general register R are incre-
with a zero and on the left with 23 zeros. mented by the contents of general register
R + 1, and the contents of general register R
For TRANSLATE TWO TO ONE, the argu-
are incremented as follows:
ment character is treated as a 16-bit unsigned
binary integer extended on the left with 16 For TRANSLATE ONE TO ONE and TRANS-
zeros. LATE TWO TO TWO, the same as for general
register R.
For TRANSLATE TWO TO TWO, the argu-
ment character is treated as a 16-bit unsigned For TRANSLATE ONE TO TWO, by twice the
binary integer extended on the right with a amount for general register R.
zero and on the left with 15 zeros.
For TRANSLATE TWO TO ONE, by one half
the amount for general register R.
The rightmost bits of the translation-table address
that are ignored (29-31 or 20-31) are treated as
The contents of general register R + 1 are then
zeros during this addition.
set to zero.
The sum is used as the address of the function
If the operation is completed with condition code
character.
1, the contents of general register R + 1 are
decremented by the number of second-operand
Each function character selected as described
bytes processed before the character that selected
above is first compared to the test character in
a function character equal to the test character
general register 0. If the result is an equal com-
was encountered, and the contents of general reg-
parison, the operation is completed. If the func-
ister R are incremented by the same number, so
tion character is not equal to the test character,
that general register R contains the address of
the function character is placed in the next avail-
the character that selected a function character
able character position in the first operand, that is,
equal to the test character. The contents of
the first function character is placed at the begin-
general register R are incremented by the same,
ning of the first-operand location, and each suc-
twice, or one half the number, as described above
cessive function character is placed immediately
for condition code 0.
to the right of the preceding character. The
second operand and the translation table are not
If the operation is completed with condition code
altered unless an overlap occurs.
3, the contents of general register R + 1 are
decremented by the number of second-operand
The operation proceeds until a selected function
bytes processed, and the contents of general reg-
character equal to the test character is encount-
ister R are incremented by the same number, so
that the instruction, when reexecuted, contains the Access exceptions are not recognized if the R
address of the next character to be processed. field is odd. When the length of the second
The contents of general register R are incre- operand is zero, no access exceptions for the first
mented by the same, twice, or one half the or second operand are recognized, and access
number, as described above for condition code 0. exceptions for the translation table may or may
not be recognized.
When general registers R and R are updated,
the bits in them that are not part of the address Resulting Condition Code:
may be set to zeros or may remain unchanged
0 Entire second operand processed without
from their original values.
finding a resulting function character equal to
the test character
The contents of general registers 0 and 1 remain
1 Second-operand character found resulting in
unchanged.
a function character equal to the test char-
The amount of processing that results in the acter
setting of condition code 3 is determined by the 2 --
CPU on the basis of improving system perform- 3 CPU-determined number of characters proc-
ance, and it may be a different amount each time essed
the instruction is executed.
Program Exceptions:
During instruction execution, CPU retry may result Access (fetch, operand 2 and translation table;
in condition code 3 being set with possibly incor- store, operand 1)
rect data having been stored in the first operand Operation (if the extended-translation facility 2
location at or to the right of the location desig- is not installed)
nated by the final address in general register R. Specification
The amount of data stored depends on the opera-
tion and the point in time at which CPU retry Programming Notes:
occurred. In all cases, the storing will occur
1. These instructions differ from the TRANS-
again, with correct data stored, when the instruc-
LATE EXTENDED instruction by having the
tion is executed again to continue processing the
following attributes:
same operands.
Depending on the instruction used, the
When the R register is the same register as the sets of argument characters and function
R register, the R or R register is register 0, or characters each can contain single-byte or
the R register is register 1, the results are unpre- double-byte characters.
dictable.
The test character is compared to a
resulting function character instead of to
When any of the first and second operands and
an argument character.
the translation table overlaps another of them, the
results are unpredictable. The argument (source) and function (des-
tination) operands are different operands.
Access exceptions for the portion of the first or
2. When condition code 3 is set, the program
second operand to the right of the last character
can simply branch back to the instruction to
processed may or may not be recognized. For an
continue the translation. The program need
operand longer than 4K bytes, access exceptions
not determine the number of characters that
are not recognized for locations more than 4K
were translated.
bytes beyond the last character processed.
3. The storage-operand references of these
Access exceptions for all characters of the trans- instructions may be multiple-access refer-
lation table may be recognized even if not all char- ences. (See “Storage-Operand Consistency”
acters are used. on page 5-87.)
Access (fetch, operand 2; store, operand 1) The converted last digit is placed in the rightmost
byte position of the result field, and the other con-
verted digits are placed adjacent to the last and to ASDIGITS DS CL31
each other in the remainder of the result field. PKDIGITS DS PL16
DC X'123456789'
The result is obtained as if the operands were DC X'123456789'
processed right to left. DC X'123456789'
DC X'1C'
The length of the second operand is 16 bytes. ...
The second operand consists of 31 digits and a UNPKA ASDIGITS(31),PKDIGITS
sign. 2. The storage-operand references of UNPACK
ASCII may be multiple-access references.
The length of the first operand is designated by (See “Storage-Operand Consistency” on
the contents of the L field. The first-operand page 5-87.)
length must not exceed 32 bytes (L must be less
than or equal to 31); otherwise, a specification
exception is recognized. UNPACK UNICODE
UNPKU D(L,B),D(B) [SS]
If the first operand is too short to contain all digits
of the second operand, the remaining leftmost ┌────────┬────────┬────┬─/──┬────┬─/──┐
portion of the second operand is ignored. Access │ 'E2' │ L │ B │ D │ B │ D │
└────────┴────────┴────┴─/──┴────┴─/──┘
exceptions for the unused portion of the second 8 16 2 32 36 47
operand may or may not be indicated.
When the length of the first operand is 32 bytes, The format of the second operand is changed
the leftmost byte is set to ASCII zero, 30 hex. from packed to Unicode Basic Latin, and the result
is placed at the first-operand location. The
The results are unpredictable if the first and packed format is described in Chapter 8, “Decimal
second operands overlap in any way. Instructions.”
As observed by other CPUs and by channel pro- The second operand is treated as having the
grams, the first operand is not necessarily stored packed format. Its digits are converted to two-
into in any particular order. byte Unicode characters by extending them on the
left with 000000000011 binary (003 hex), and the
Resulting Condition Code: Unicode characters are then placed at the first
operand location. The digits are not checked for
0 Sign is plus
valid codes. The sign of the second operand is
1 Sign is minus
not transferred to the first operand but is checked
2 --
for validity and determines the condition code. If
3 Sign is invalid
the sign is 1010, 1100, 1110 or 1111 binary (plus),
condition code 0 is set. If the sign is 1011 or
Program Exceptions:
1101 binary (minus), condition code 1 is set. If
Access (fetch, operand 2; store, operand 1) the sign is not one of the codes for plus or minus,
Operation (if the extended-translation facility 2 condition code 3 is set.
is not installed)
Specification The converted last digit is placed in the rightmost
character position of the result field, and the other
Programming Notes: converted digits are placed adjacent to the last
1. The following example illustrates the use of and to each other in the remainder of the result
the instruction to unpack to ASCII digits: field.
is low, the contents of general-register pair 0-1 are Refer to “Sorting Instructions” on page A-51
interchanged with those of the node, and a unit of for a discussion of trees and their use in
operation is completed. If the register operand is sorting.
high, no additional action is taken, and the unit of
3. The program should avoid placing a nonzero
operation is completed. If the compare values are
value in bit positions 0-6 of general register 5
equal, general-register pair 2-3 is loaded from the
when in the 24-bit addressing mode. If any bit
currently addressed node, the instruction is com-
in bit positions 0-6 is a one, the nodes of the
pleted, and condition code 0 is set.
tree will not be examined successively.
In those cases when the value in the first word of 4. When general register 0 is negative, and pro-
the node is less than or equal to the value in the vided that the tree has been updated properly
register, the contents of the node remain previously, the node represented by the
unchanged. However, in some models, these general-register pair 0-1 either is the node or
contents may be fetched and subsequently stored is equal to the node (equal keys) that would
back. be selected if the unit of operation continued.
In this case, ending the unit of operation and
Access exceptions are recognized only for one setting condition code 3 is a faster means of
doubleword node at a time. Access exceptions, selecting an appropriate node because it does
change-bit action, and PER storage alteration do not require further examination and updating
not occur for subsequent nodes until the previous of the tree.
node has been successfully compared and
5. Setting condition code 3 provides improved
updated, and they also do not occur if a
performance when the replacement record is
specification-exception condition exists.
equal to the old winner and, more importantly
Resulting Condition Code: (since the first case can be detected by
means of the condition code of CFC), when
0 Equal compare values at currently addressed the update path contains a negative
node codeword, indicating equality with the old
1 No equal compare values found on path, or winner.
no comparison made
2 -- 6. In those cases when the value in the first
3 General register 5 nonzero and general reg- word of the node is less than or equal to the
ister 0 negative value in the register, depending on the model,
the contents of the node may be fetched and
Program Exceptions: subsequently stored back. As a result, any of
the following may occur for the storage
Access (fetch and store, nodes of tree) location containing the node: a PER storage-
Specification alteration event may be recognized; a pro-
tection exception for storing may be recog-
Programming Notes:
nized; and, provided no access exceptions
1. An example of the use of UPDATE TREE is exist, the change bit may be set to one.
given in “Sorting Instructions” in Appendix A, Because the contents of storage remain
“Number Representation and Instruction-Use unchanged, the change bit may or may not be
Examples.” one when a PER storage-alteration event is
recognized.
2. For use in sorting, when equal compare
values have been found, the contents of 7. Special precautions should be taken when
general registers 1 and 3 can be appropriate UPDATE TREE is made the target of
(depending on the contents of the tree) for the EXECUTE. See the programming note con-
subsequent execution of COMPARE AND cerning interruptible instructions under
FORM CODEWORD. The contents of general EXECUTE.
register 2, shifted right 16 bit positions, can be
8. Further programming notes concerning inter-
similarly appropriate, and they can provide for
ruptible instructions are included in “Interrup-
minimal recomparison of partially equal keys.
tible Instructions” on page 5-17.
9. The storage-operand references for UPDATE 10. Figure 7-73 is a summary of the operation of
TREE may be multiple-access references. UPDATE TREE.
(See “Storage-Operand Consistency” on
page 5-87.)
┌───────────────────────────────────┐ No
│Bits 29-31 of GR4 and GR5 all zeros├────── Specification Exception
└─────────────────┬─────────────────┘
┌─────────┐ │ Yes
│Unit-of- │ │
│operation├─────────────────────│
│boundary │ │
└─────────┘
┌────────────────────────────────────────────┐
│ │GR5 shifted right one position ── TEMPWORD1│
│ │ │
│ │ ── Bit 29 of TEMPWORD1 │
│ └─────────────────────┬──────────────────────┘
│ │
│
│ ┌─────────────┐ Yes ┌───────────────┐
│ │TEMPWORD1 = ├─────────────────│ ── GR5 ├────┐
│ └──────┬──────┘ │ │ │
│ │ No │1 ── Cond Code│ │
│ │ └───────────────┘ │
│ │
│ ┌────────────────┐ Yes │
│ │Bit of GR one├────────────────────────┐ │
│ └───────┬────────┘ │ │
│ │ No │
│ │ ┌──────────────────┐ │
│ │ │TEMPWORD1 ── GR5 │ │
│ │ │ │ │
│ │3 ── Cond Code │ │
│ ┌───────────────────────────────┐ └───────┬──────────┘ │
│ │GR4 + TEMPWORD1 ── TEMPADDRESS│ │ │
│ └───────────────┬───────────────┘ │───────────┘
│ │
│ End operation
│ ┌──────────────────────────────────┐
│ │Fetch doubleword from location in │
│ │storage designated by TEMPADDRESS;│
│ │ │
│ │Bits -31 ── TEMPWORD2 │
│ │ │
│ │Bits 32-64 ── TEMPWORD3 │
│ └────────────────┬─────────────────┘
│ │
│
│ ┌─────────────────┐
│ │TEMPWORD1 ── GR5│
│ └────────┬────────┘
│ │
│
│ GR high ┌─────────────────────────┐ GR equal
│──────────────┤Compare GR and TEMPWORD2├─────────────────────┐
└────────────┬────────────┘ │
│ │ GR low │
│ │
│ ┌─────────────────┐
│ ┌────────────────────────────────────┐ │TEMPWORD2 ── GR2│
│ │Store contents of GR and GR1 in │ │ │
│ │doubleword designated by TEMPADDRESS│ │TEMPWORD3 ── GR3│
│ └──────────────────┬─────────────────┘ │ │
│ │ │ ── Cond Code │
│ └────────┬────────┘
│ ┌─────────────────┐ │
│ │TEMPWORD2 ── GR│
│ │ │ End operation
│ │TEMPWORD3 ── GR1│
│ └────────┬────────┘
│ │
└────────────────────────────┘
Figure 7-73. Execution of UPDATE TREE
The decimal instructions of this chapter perform Decimal digits in the zoned format may be part of
arithmetic and editing operations on decimal data. a larger character set, which includes also alpha-
Additional operations on decimal data are pro- betic and special characters. The zoned format is,
vided by several of the instructions in Chapter 7, therefore, suitable for input, editing, and output of
“General Instructions.” Decimal operands always numeric data in human-readable form. There are
| reside in storage, and most decimal instructions no decimal-arithmetic instructions which operate
use the SS instruction format. Decimal operands directly on decimal numbers in the zoned format;
occupy storage fields that can start on any byte such numbers must first be converted to the
boundary. packed format.
When an invalid sign or digit code is detected, a Figure 8-1. Summary of Digit and Sign Codes
data exception is recognized. For the decimal-
arithmetic instructions and CONVERT TO Programming Note: Since 1111 is both the
BINARY, the action taken for a data exception zone code and an alternate code for plus,
depends on whether a sign code is invalid. When unsigned (positive) decimal numbers may be
a sign code is invalid, the operation is suppressed represented in the zoned format with 1111 zone
regardless of whether any other condition causing codes in all byte positions. The result of the
a data exception exists. When an invalid digit PACK instruction converting such a number to the
code is detected but no sign code is invalid, the packed format may be used directly as an
operation is terminated on some models and sup- operand for decimal instructions.
pressed on others.
For the editing instructions EDIT and EDIT AND Decimal Operations
MARK, an invalid sign code is not recognized. The decimal instructions in this chapter consist of
The operation is terminated for a data exception two classes, the decimal-arithmetic instructions
due to an invalid digit code. No validity checking and the editing instructions.
is performed by MOVE NUMERICS, MOVE WITH
OFFSET, MOVE ZONES, PACK, and UNPACK.
Decimal-Arithmetic Instructions
The zone code 1111 is generated in the left four
The decimal-arithmetic instructions perform addi-
bit positions of each byte representing a zone and
tion, subtraction, multiplication, division, compar-
a decimal digit in zoned-format results. Zoned-
ison, and shifting.
format results are produced by EDIT, EDIT AND
MARK, and UNPACK. For EDIT and EDIT AND
Operands of the decimal-arithmetic instructions
MARK, each result byte representing a zoned-
are in the packed format and are treated as
format decimal digit contains the zone code 1111
signed decimal integers. A decimal integer is
in the left four bit positions and the decimal-digit
represented in true form as an absolute value with
code in the right four bit positions. For UNPACK,
a separate plus or minus sign. It contains an odd
zone bits with a coding of 1111 are supplied for all
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│ADD DECIMAL │AP │SS C │ A │Dd DF │ ST│B B│FA │
│COMPARE DECIMAL │CP │SS C │ A │Dd │ │B B│F9 │
│DIVIDE DECIMAL │DP │SS │ A SP│Dd DK │ ST│B B│FD │
│EDIT │ED │SS C │ A │Dd │ ST│B B│DE │
│EDIT AND MARK │EDMK │SS C │ A │Dd G1 │ R ST│B B│DF │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│MULTIPLY DECIMAL │MP │SS │ A SP│Dd │ ST│B B│FC │
│SHIFT AND ROUND DECIMAL │SRP │SS C │ A │Dd DF │ ST│B │F │
│SUBTRACT DECIMAL │SP │SS C │ A │Dd DF │ ST│B B│FB │
│TEST DECIMAL │TP │RSL C E2│ A │ │ │B │EBC│
│ZERO AND ADD │ZAP │SS C │ A │Dd DF │ ST│B B│F8 │
├────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┤
│Explanation: │
│ │
│ A Access exceptions for logical addresses. │
│ B B field designates an access register in the access-register mode. │
│ B B field designates an access register in the access-register mode. │
│ C Condition code is set. │
│ Dd Decimal-operand data exception. │
│ DF Decimal-overflow exception. │
│ DK Decimal-divide exception. │
│ E2 Extended-translation facility 2. │
│ G1 Instruction execution includes the implied use of general register 1. │
│ R PER general-register-alteration event. │
│ RSL RSL instruction format. │
│ SP Specification exception. │
│ SS SS instruction format. │
│ ST PER storage-alteration event. │
└────────────────────────────────────────────────────────────────────────────────────────────────┘
Figure 8-2. Summary of Decimal Instructions
┌────────┬────┬────┬────┬─/──┬────┬─/──┐ ┌────────┬────┬────┬────┬─/──┬────┬─/──┐
│ 'FA' │ L │ L │ B │ D │ B │ D │ │ 'F9' │ L │ L │ B │ D │ B │ D │
└────────┴────┴────┴────┴─/──┴────┴─/──┘ └────────┴────┴────┴────┴─/──┴────┴─/──┘
8 12 16 2 32 36 47 8 12 16 2 32 36 47
The second operand is added to the first operand, The first operand is compared with the second
and the resulting sum is placed at the first- operand, and the result is indicated in the condi-
operand location. The operands and result are in tion code. The operands are in the packed
the packed format. format.
Addition is algebraic, taking into account the signs Comparison is algebraic and follows the procedure
and all digits of both operands. All sign and digit for decimal subtraction, except that both operands
codes are checked for validity. remain unchanged. When the difference is zero,
the operands are equal. When a nonzero differ-
If the first operand is too short to contain all left- ence is positive or negative, the first operand is
most nonzero digits of the sum, decimal overflow high or low, respectively.
occurs. The operation is completed. The result is
obtained by ignoring the overflow digits, and con- Overflow cannot occur because the difference is
dition code 3 is set. If the decimal-overflow mask discarded.
is one, a program interruption for decimal overflow
occurs. All sign and digit codes are checked for validity.
The sign of the sum is determined by the rules of Resulting Condition Code:
algebra. In the absence of overflow, the sign of a 0 Operands equal
zero result is made positive. If overflow occurs, a 1 First operand low
zero result is given either a positive or negative 2 First operand high
sign, as determined by what the sign of the 3 --
correct sum would have been.
Program Exceptions:
Resulting Condition Code:
Access (fetch, operands 1 and 2)
0 Result zero; no overflow Data
1 Result less than zero; no overflow
2 Result greater than zero; no overflow Programming Notes:
3 Overflow
1. An example of the use of the COMPARE
Program Exceptions: DECIMAL instruction is given in Appendix A,
“Number Representation and Instruction-Use
Access (fetch, operand 2; fetch and store, Examples.”
operand 1)
Data 2. The preferred and alternate sign codes for a
Decimal overflow particular sign are treated as equivalent for
comparison purposes.
Programming Note: An example of the use of
the ADD DECIMAL instruction is given in 3. A negative zero and a positive zero compare
Appendix A, “Number Representation and equal.
Instruction-Use Examples.”
Programming Notes:
The first operand (the dividend) is divided by the
1. An example of the use of the DIVIDE
second operand (the divisor). The resulting quo-
DECIMAL instruction is given in Appendix A,
tient and remainder are placed at the first-operand
“Number Representation and Instruction-Use
location. The operands and results are in the
Examples.”
packed format.
2. The dividend cannot exceed 31 digits and
The quotient is placed leftmost in the first-operand sign. Since the remainder cannot be shorter
location. The number of bytes in the quotient field than one digit and sign, the quotient cannot
is equal to the difference between the dividend exceed 29 digits and sign.
and divisor lengths (L - L). The remainder is
3. The condition for a decimal-divide exception
placed rightmost in the first-operand location and
can be determined by a trial comparison. The
has a length equal to the divisor length. Together,
leftmost digit of the divisor is aligned one digit
the quotient and remainder fields occupy the
to the right of the leftmost dividend digit, with
entire first operand; therefore, the address of the
rightmost zeros appended up to the length of
quotient is the address of the first operand.
the dividend. When the divisor, so aligned, is
The divisor length cannot exceed 15 digits and less than or equal to the dividend, ignoring
sign (L not greater than seven) and must be less signs, a divide exception is indicated.
than the dividend length (L less than L); other- 4. If a data exception does not exist, a decimal-
wise, a specification exception is recognized. divide exception occurs when the leftmost divi-
dend digit is not zero.
The dividend, divisor, quotient, and remainder are
each signed decimal integers in the packed format
and are right-aligned in their fields. All sign and
EDIT
digit codes of the dividend and divisor are ED D(L,B),D(B) [SS]
checked for validity.
┌────────┬────────┬────┬─/──┬────┬─/──┐
The sign of the quotient is determined by the rules │ 'DE' │ L │ B │ D │ B │ D │
└────────┴────────┴────┴─/──┴────┴─/──┘
of algebra from the dividend and divisor signs. 8 16 2 32 36 47
The sign of the remainder has the same value as
the dividend sign. These rules hold even when
The second operand (the source), which normally
the quotient or remainder is zero.
contains one or more decimal numbers in the
Overflow cannot occur. If the divisor is zero or the packed format, is changed to the zoned format
quotient is too large to be represented by the and modified under the control of the first operand
number of digits specified, a decimal-divide excep- (the pattern). The edited result replaces the first
tion is recognized. This includes the case of divi- operand.
sion of zero by zero. The decimal-divide excep-
The length field specifies the length of the first
tion is indicated only if the sign codes of both the
operand, which may contain bytes of any value.
dividend and divisor are valid, and only if the digit
or digits used in establishing the exception are
The length of the source is determined by the
valid.
operation according to the contents of the pattern.
The source normally consists of one or more
Condition Code: The code remains unchanged.
decimal numbers, each in the packed format. The
leftmost four bits of each source byte must specify
The result is obtained as if both operands were Fill Byte: The first byte of the pattern is used as
processed left to right one byte at a time. Over- the fill byte. The fill byte can have any code and
lapping pattern and source fields give unpredict- may concurrently specify a control function. If this
able results. byte is a digit selector or significance starter, the
indicated editing action is taken after the code has
During the editing process, each byte of the been assigned to the fill byte.
pattern is affected in one of three ways:
Source Digits: Each time a digit selector or sig-
1. It is left unchanged.
nificance starter is encountered in the pattern, a
2. It is replaced by a source digit expanded to new source digit is examined for placement in the
the zoned format. pattern field. Either the source digit is disre-
3. It is replaced by the first byte in the pattern, garded, or it is expanded to the zoned format, by
called the fill byte. appending the zone code 1111 on the left, and
stored in place of the pattern byte.
Which of the three actions takes place is deter-
mined by one or more of the following: the type of Execution is as if the source digits were selected
the pattern byte, the state of the significance indi- one byte at a time and as if a source byte were
cator, and whether the source digit examined is fetched for inspection only once during an editing
zero. operation. Each source digit is examined only
once for a zero value. The leftmost four bits of
Pattern Bytes: There are four types of pattern each byte are examined first, and the rightmost
bytes: digit selector, significance starter, field sep- four bits, when they represent a decimal-digit
arator, and message byte. Their coding is as code, remain available for the next pattern byte
follows: that calls for a digit examination. When the left-
┌──────────────────────┬───────────┐ most four bits contain an invalid digit code, a data
│ │ Code │ exception is recognized, and the operation is ter-
│ Name │ (Binary) │ minated.
├──────────────────────┼───────────┤
│ Digit selector │ 1 │
At the time the left digit of a source byte is exam-
│ Significance starter │ 1 1 │
│ Field separator │ 1 1 │ ined, the rightmost four bits are checked for the
│ Message byte │ Any other │ existence of a sign code. When a sign code is
└──────────────────────┴───────────┘ encountered in the rightmost four bit positions,
these bits are not treated as a decimal-digit code,
The detection of either a digit selector or a signif-
and a new source byte is fetched from storage
icance starter in the pattern causes an examina-
when the next pattern byte calls for a source-digit
tion to be made of the significance indicator and of
examination.
a source digit. As a result, either the expanded
source digit or the fill byte, as appropriate, is
When the pattern contains no digit selector or sig-
selected to replace the pattern byte. Additionally,
nificance starter, no source bytes are fetched and
encountering a digit selector or a significance
examined.
starter may cause the significance indicator to be
changed. Significance Indicator: The significance indi-
cator is turned on or off to indicate the significance
The field separator identifies individual fields in a
or nonsignificance, respectively, of subsequent
multiple-field editing operation. It is always
source digits or message bytes. Significant
replaced in the result by the fill byte, and the sig-
source digits replace their corresponding digit
nificance indicator is always off after the field sep-
arator is encountered.
1. An example of the use of the MULTIPLY For a right shift, the I field, bits 12-15 of the
DECIMAL instruction is given Appendix A, instruction, is used as a decimal rounding digit.
“Number Representation and Instruction-Use The first operand, which is treated as positive by
Examples.” ignoring the sign, is rounded by decimally adding
the rounding digit to the leftmost of the digits to be
2. The product cannot exceed 31 digits and sign. shifted out and by propagating the carry, if any, to
The leftmost digit of the product is always the left. The result of this addition is then shifted
zero. right. Except for validity checking and the partic-
ipation in rounding, the digits shifted out of the
SHIFT AND ROUND DECIMAL rightmost decimal-digit position are ignored and
are lost.
SRP D(L,B),D(B),I [SS]
If one or more nonzero digits are shifted out
┌────────┬────┬────┬────┬─/──┬────┬─/──┐
│ 'F' │ L │ I │ B │ D │ B │ D │ during a left shift, decimal overflow occurs. The
└────────┴────┴────┴────┴─/──┴────┴─/──┘ operation is completed. The result is obtained by
8 12 16 2 32 36 47 ignoring the overflow digits, and condition code 3
is set. If the decimal-overflow mask is one, a
The first operand is shifted in the direction and for program interruption for decimal overflow occurs.
the number of decimal-digit positions specified by Overflow cannot occur for a right shift, with or
the second-operand address, and, when shifting to without rounding, or when no shifting is specified.
the right is specified, the absolute value of the first
operand is rounded by the rounding digit, I. The In the absence of overflow, the sign of a zero
first operand and the result are in the packed result is made positive. If overflow occurs, the
format. sign of the result is the same as the original sign
but with the preferred sign code.
The first operand is considered to be in the
packed-decimal format. Only its digit portion is A data exception is recognized when the first
shifted; the sign position does not participate in operand does not have valid sign and digit codes
the shifting. Zeros are supplied for the vacated or when the rounding digit is not a valid digit code.
digit positions. The result replaces the first The validity of the first-operand codes is checked
Programming Notes:
TEST DECIMAL
1. Examples of the use of the SHIFT AND
ROUND DECIMAL instruction are given in TP D(L,B) [RSL]
Appendix A, “Number Representation and ┌────────┬────┬────┬────┬─/──┬────────┬────────┐
Instruction-Use Examples.” │ 'EB' │ L │////│ B │ D │////////│ 'C' │
└────────┴────┴────┴────┴─/──┴────────┴────────┘
2. SHIFT AND ROUND DECIMAL can be used 8 12 16 2 32 4 47
for shifting up to 31 digit positions left and up
to 32 digit positions right. This is sufficient to
The first operand is tested for valid decimal digits
clear all digits of any decimal number even
and a valid sign code, and the result is indicated
with rounding.
in the condition code. The operand is in the
3. For right shifts, the rounding digit 5 provides packed format.
conventional rounding of the result. The
rounding digit 0 specifies truncation without Resulting Condition Code:
rounding. 0 All digit codes and the sign valid
4. When the B field is zero, the six-bit shift 1 Sign invalid
value is obtained directly from bits 42-47 of 2 At least one digit code invalid
the instruction. 3 Sign invalid and at least one digit code invalid
Program Exceptions:
SUBTRACT DECIMAL
Access (fetch, operand 1)
SP D(L,B),D(L,B) [SS] Operation (if the extended-translation facility 2
┌────────┬────┬────┬────┬─/──┬────┬─/──┐
is not installed)
│ 'FB' │ L │ L │ B │ D │ B │ D │
└────────┴────┴────┴────┴─/──┴────┴─/──┘
8 12 16 2 32 36 47 ZERO AND ADD
ZAP D(L,B),D(L,B) [SS]
The second operand is subtracted from the first
┌────────┬────┬────┬────┬─/──┬────┬─/──┐
operand, and the resulting difference is placed at │ 'F8' │ L │ L │ B │ D │ B │ D │
the first-operand location. The operands and └────────┴────┴────┴────┴─/──┴────┴─/──┘
result are in the packed format. 8 12 16 2 32 36 47
SUBTRACT DECIMAL is executed the same as The second operand is placed at the first-operand
ADD DECIMAL, except that the second operand is location. The operation is equivalent to an addi-
considered to have a sign opposite to the sign in tion to zero. The operand and result are in the
packed format.
Floating-point instructions are used to perform cal- hexadecimal numbers. The exponent range is the
culations on operands having a wide range of same for the short, long, and extended formats.
magnitude and to obtain results scaled to preserve The results of most operations on HFP data are
precision. truncated to fit into the target format, but there are
instructions available to round the result when
Floating-point operands have formats based on converting to a narrower format. For HFP oper-
either the radix 16 or, when the binary- ands, the implicit unit digit of the significand is
floating-point facility is installed, the radix 2. The always zero. Since the value of the significand
radix values 16 and 2 lead to the terminology and fraction are the same, HFP operations are
“hexadecimal” and “binary” floating point (HFP and described in terms of the fraction, and the term
BFP). The formats are also based on three significand is not used.
operand lengths: short (32 bits), long (64 bits),
and extended (128 bits). Short operands require Binary-floating-point (BFP) operands have formats
less storage than long or extended operands. On which provide for exponents that specify powers of
the other hand, long and extended operands the radix 2 and significands that are binary
permit greater precision in computation. numbers. The exponent range differs for different
formats, the range being greater for the longer
A floating-point operand may be numeric or, for formats. In the long and extended formats, the
BFP only, nonnumeric (a not-a-number, or NaN). exponent range is significantly greater for BFP
A numeric operand, called a floating-point number, data than for HFP data. The results of operations
has three components: a sign bit, a signed binary performed on BFP data are rounded automatically
exponent, and a significand. The significand con- to fit into the target format; the manner of rounding
sists of an implicit unit digit to the left of an implied is determined by a program-settable rounding
radix point and an explicit fraction field to the right. mode.
The significand digits are based on the radix, 2 or
16. The magnitude (an unsigned value) of the Either normalized or unnormalized numbers may
number is the product of the significand and the be used as operands for any HFP operation,
radix raised to the power of the exponent. The where a normalized number is one having a
number is positive or negative depending on nonzero leftmost fraction digit. Most HFP
whether the sign bit is zero or one, respectively. instructions generate normalized results for
A nonnumeric BFP operand also has a sign bit, greatest precision. HFP add and subtract
signed exponent, and fraction field. instructions that generate unnormalized results are
also available.
Hexadecimal-floating-point (HFP) operands have
formats which provide for exponents that specify There are no unnormalized operands for BFP
powers of the radix 16 and significands that are operations. For normalized BFP numbers, the
SUBTRACT NORMALIZED — GD — Figure 9-2. Number Ranges for BFP and HFP
SUBTRACT UNNORMAL- Formats
IZED — GD —
Explanation: Equivalent BFP and HFP Number
Representations
BR Biased round to nearest.
CRM Rounded according to current rounding The exponent of an HFP number is represented in
mode. the number as an unsigned seven-bit binary
E Result is exact, no rounding is required. integer called the characteristic. The character-
GD Round using a guard digit; see the istic is obtained by adding 64 to the exponent
instruction definition. This is almost, but value (excess-64 notation). The range of the
not quite, round toward 0. characteristic is 0 to 127, which corresponds to an
M Rounding is specified by a modifier field exponent range of −64 to +63.
in the instruction.
RTZ Round toward 0. The exponent of a BFP number is represented in
the number as an unsigned binary integer called
Figure 9-1. Comparison of Rounding Action the biased exponent. The biased exponent is
obtained by adding a bias to the exponent value.
The number of bit positions containing the biased
exponent, the value of the bias, and the exponent
range depend on the number format (short, long,
or extended) and are shown for the three formats
in Figure 19-7 on page 19-5. Biased exponents
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┐
│ │Mne- │ │Op │
│ Name │monic│ Characteristics │Code│
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┤
│CONVERT BFP TO HFP (long) │THDR │RRE C FX│ │Da │ │ │B359│
│CONVERT BFP TO HFP (short to long) │THDER│RRE C FX│ │Da │ │ │B358│
│CONVERT HFP TO BFP (long) │TBDR │RRF C FX│ SP│Da │ │ │B351│
│CONVERT HFP TO BFP (long to short) │TBEDR│RRF C FX│ SP│Da │ │ │B35│
│LOAD (extended) │LXR │RRE FX│ SP│Da │ │ │B365│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│LOAD (long) │LDR │RR │ SP│Da │ │ │28 │
│LOAD (long) │LD │RX │ A SP│Da │ │ B│68 │
│LOAD (short) │LER │RR │ SP│Da │ │ │38 │
│LOAD (short) │LE │RX │ A SP│Da │ │ B│78 │
│LOAD ZERO (extended) │LZXR │RRE FX│ SP│Da │ │ │B376│
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┤
│LOAD ZERO (long) │LZDR │RRE FX│ │Da │ │ │B375│
│LOAD ZERO (short) │LZER │RRE FX│ │Da │ │ │B374│
│STORE (long) │STD │RX │ A SP│Da │ ST│ B│6 │
│STORE (short) │STE │RX │ A SP│Da │ ST│ B│7 │
├────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┤
│Explanation: │
│ │
│ A Access exceptions for logical addresses. │
│ B B field designates an access register in the access-register mode. │
│ C Condition code is set. │
│ Da AFP-register data exception. │
│ FX Floating-point-support extensions facility. │
│ RR RR instruction format. │
│ RRE RRE instruction format. │
│ RRF RRF instruction format. │
│ RX RX instruction format. │
│ SP Specification exception. │
│ ST PER storage-alteration event. │
└────────────────────────────────────────────────────────────────────────────────────────────────┘
Figure 9-5. Summary of Floating-Point-Support Instructions
For numeric operands, the sign of the result is the −∞ ≤ a < −Hmax T(−Hmax), cc3
sign of the source operand. If the source operand −Hmax ≤ a ≤ −Hmin T(r), cc1
has a sign bit of one and all other operand bits
are zeros, the result also is a one followed by all −Hmin < a < 0 T(−0), cc1
zeros. −0 T(−0), cc0
CONVERT HFP TO BFP one and all other operand bits are zeros, the
result also is a one followed by all zeros.
Mnemonic R,M,R [RRF]
See Figure 9-8 on page 9-10 for a detailed
┌────────────────┬────┬────┬────┬────┐
│ Op Code │ M │////│ R │ R │ description of the results of this instruction.
└────────────────┴────┴────┴────┴────┘
16 2 24 28 31 The M field must designate a valid modifier; oth-
erwise, a specification exception is recognized.
Mnemonic Op Code Operands
TBEDR 'B35' Long HFP operand,
short BFP result Resulting Condition Code:
TBDR 'B351' Long HFP operand,
long BFP result 0 Source was zero
1 Source was less than zero
The second operand (the source operand) is con- 2 Source was greater than zero
verted from the hexadecimal-floating-point (HFP) 3 Special case
format to the binary-floating-point (BFP) format,
and the result rounded according to the rounding Program Exceptions:
method specified by the M field is placed at the Data with DXC 1, AFP register
first-operand location. The sign and magnitude of Operation (if the floating-point-support-
the source operand are tested to determine the extensions facility is not installed)
setting of the condition code. Specification
Mnemonic R [RRE]
Figure 9-10. BFP and HFP Instructions with All Operands of Same Length
Figure 9-11. BFP and HFP Instructions with Result Longer than Source
Figure 9-12. BFP and HFP Instructions with Result Shorter than Source
This chapter includes all privileged and semiprivi- ments are not met generates a privileged-
leged instructions described in this publication, operation exception or some other program-
except the input/output instructions, which are interruption condition depending on the particular
described in Chapter 14, “I/O Instructions.” requirement which is violated. Those require-
ments which cause a privileged-operation excep-
Privileged instructions may be executed only when tion to be generated in the problem state are not
the CPU is in the supervisor state. An attempt to enforced when execution is attempted in the
execute a privileged instruction in the problem supervisor state.
state generates a privileged-operation exception.
The control instructions and their mnemonics,
The semiprivileged instructions are those formats, and operation codes are listed in
instructions that can be executed in the problem Figure 10-1 on page 10-3. The figure also indi-
state when certain authority requirements are met. cates when the condition code is set, the instruc-
An attempt to execute a semiprivileged instruction tion fields that designate access registers, and the
in the problem state when the authority require-
The contents of general registers R and R when If R is nonzero, bits 32-63 of the current PSW,
the execution of the instruction begins in the base- including the addressing-mode bit and the updated
authority state are as follows: instruction address, are placed in general register
R. If R is zero, general register 0 remains
┌────────────────┬────────┬────┬────┐ unchanged.
R │ Key Mask │ │Key │ │
└────────────────┴────────┴────┴────┘
16 24 28 31 PSW bits 32-63, the PKM, the PSW key, and the
problem-state bit are restored from the DUCT, and
┌─┬─────────────────────────────────┐ the RA bit in the DUCT is set to zero. There is no
R │A│ Branch Address │ test for whether the restored PSW key is author-
└─┴─────────────────────────────────┘ ized by the restored PKM.
1 31
Special Conditions
PSW bits 32-63, the PKM, the PSW key, and the
problem-state bit are saved in the DUCT, the RA The instruction can be executed successfully only
bit in the DUCT is set to one, and bits 16-23, 29, when the address-space-function control, bit 15 of
and 30 of word 9 of the DUCT are set to zeros. control register 0, is one. In addition, R must be
nonzero in the base-authority state and zero in the
Bits 24-27 of general register R are placed in bit reduced-authority state. If any of these rules is
positions 8-11 of the PSW as the new PSW key. violated, a special-operation exception is recog-
In the problem state, the new PSW key must be nized, and the operation is suppressed.
authorized by the PKM; otherwise, if the new PSW
key is not authorized, a privileged-operation In the problem state, the execution of the instruc-
exception is recognized. tion in the base-authority state is subject to control
by the PSW-key mask in control register 3. When
After the new PSW key has been placed in the the bit in the PSW-key mask corresponding to the
PSW, bits 0-15 of general register R are ANDed PSW-key value to be set is one, the instruction is
with the PKM in control register 3, and the result executed successfully. When the selected bit in
replaces the PKM in control register 3. the PSW-key mask is zero, a privileged-operation
exception is recognized. In the supervisor state,
The problem-state bit in the PSW is set to one. any value for the PSW key is valid.
Bit 0 of general register R is placed in bit position Key-controlled protection does not apply to any
32 of the PSW as the new addressing-mode bit. access made during the operation. Low-address
A branch address is generated from bits 1-31 of protection does apply.
general register R under the control of the new
addressing mode, and the result is placed in bit The contents of word 8 of the DUCT are not
positions 33-63 of the PSW as the new instruction checked for validity before they are loaded into the
address. PSW. However, after loading, a specification
exception is recognized, and a program inter-
Bits 16-23 and 28-31 of general register R may ruption occurs, when the newly loaded PSW con-
be used for future extensions and should be
Addressing (dispatchable-unit control table) 2. Only one base-authority state and one
Operation (if the branch-and-set-authority reduced-authority state are available to a
facility is not installed) dispatchable unit. Nested use of BRANCH
Privileged operation (selected PSW-key-mask AND SET AUTHORITY, that is, use within dif-
bit is zero in the problem state, base-authority ferent subroutine levels, is not possible. The
operation only) requirement that R must be nonzero in the
Protection (low-address; dispatchable-unit base-authority state and zero in the reduced-
control table) authority state provides detection of an
Special operation attempt to use BRANCH AND SET
Specification AUTHORITY in the base-authority state when
Trace the dispatchable unit is already in the
reduced-authority state because of a previous
use of the instruction in the base-authority
state.
3. The instruction may be referred to as BSA-ba
or BSA-ra depending on whether it is exe-
cuted in the base-authority state or the
reduced-authority state, respectively.
The branch state entry is formed and information The operation is suppressed on all addressing and
is placed in it as described in “Stacking Process” protection exceptions.
on page 5-73. The entry-type code in the state
entry is 0000100 binary. The priority of recognition of program exceptions
for the instruction is shown in Figure 10-3 on
Key-controlled protection does not apply to page 10-12.
accesses to the linkage stack, but low-address
and page protection do apply. Condition Code: The code remains unchanged.
If the DASTE specifies the base space of the sub- The operation, since it changes a translation
space group, the PSTD in control register 1 is parameter in control register 1, causes all copies
replaced by the STD in the DASTE. If the DASTE of prefetched instructions to be discarded, except
specifies a subspace, bits 1-23 and 25-31 of the when in the home-space mode.
PSTD are replaced by the same bits of the STD in
the DASTE, and bit 0 of the PSTD, the space- Special Conditions
switch-event-control bit, and bit 24 of the PSTD,
the storage-alteration-event bit, remain The address-space-function control, bit 15 of
unchanged. control register 0, must be one, and DAT must be
on; otherwise, a special-operation exception is
If R is nonzero, bits 32-63 of the current PSW, recognized. A special-operation exception is also
including the updated instruction address, are recognized if the current primary address space is
placed in general register R. If R is zero, not in a subspace group associated with the
general register 0 remains unchanged. current dispatchable unit, if the ALET in access
register R is ALET 1 but a subspace has not pre-
┌──────────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B.1 Operation exception due to subspace-group facility not being │
│ installed. │
│ │
│ 7.B.2 Special-operation exception due to DAT being off or the │
│ address-space-function control, bit 15 of control register , │
│ being zero. │
│ │
│ 8.A Trace exceptions. │
│ │
│ 8.B Protection exception (low-address protection) for access to │
│ dispatchable-unit control table. │
│ │
│ 8.C.1 Addressing exception for access to dispatchable-unit control │
│ table. │
│ │
│ 8.C.2 Special-operation exception due to current primary address │
│ space not being in a subspace group associated with the │
│ current dispatchable unit (primary-ASTE origin in control │
│ register 5 not equal to base-ASTE origin in dispatchable-unit │
│ control table). │
│ │
│ Note: Exception 8.C.3.A can occur only if the access-list- │
│ entry token (ALET) in access register R is ALET . │
│ │
│ 8.C.3.A Addressing exception for access to base ASTE (ASTE designated │
│ by base-ASTE origin in dispatchable-unit control table). │
└──────────────────────────────────────────────────────────────────────────┘
Figure 10-4 (Part 1 of 2). Priority of Execution: BRANCH IN SUBSPACE GROUP
┌────────────────┬────────┬────┬────┐
Bits 8-31 may be used as in the SI or RS formats, │ 'B226' │////////│ R │////│
or in some other way, to specify the particular └────────────────┴────────┴────┴────┘
diagnostic function. The use depends on the 16 24 28 31
model.
The 16-bit PASN, bits 16-31 of control register 4,
The execution of the instruction may affect the is placed in bit positions 16-31 of general register
state of the CPU and the contents of a register or R. Bits 0-15 of the general register are set to
storage location, as well as the progress of an I/O zeros.
operation. Some diagnostic functions may cause
the test indicator to be turned on. Bits 16-23 and 28-31 of the instruction are
ignored.
Resulting Condition Code: The code is unpre-
dictable. Special Conditions
The priority of recognition of program exceptions The priority of recognition of program exceptions
for the instruction is shown in Figure 10-6. for the instruction is shown in Figure 10-7.
Condition Code: The code remains unchanged. Condition Code: The code remains unchanged.
┌──────────────────────────────────────────────┐ ┌──────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as │ │ 1.-6. Exceptions with the same priority as │
│ the priority of program-interruption │ │ the priority of program-interruption │
│ conditions for the general case. │ │ conditions for the general case. │
│ │ │ │
│ 7.A Access exceptions for second instruc- │ │ 7.A Access exceptions for second instruc- │
│ tion halfword. │ │ tion halfword. │
│ │ │ │
│ 7.B Special-operation exception due to │ │ 7.B Special-operation exception due to │
│ DAT being off. │ │ DAT being off. │
│ │ │ │
│ 8. Privileged-operation exception due to │ │ 8. Privileged-operation exception due to │
│ extraction-authority control, bit 4 of│ │ extraction-authority control bit 4 of │
│ control register , being zero in │ │ control register , being zero in │
│ problem state. │ │ problem state. │
└──────────────────────────────────────────────┘ └──────────────────────────────────────────────┘
Figure 10-6. Priority of Execution: EXTRACT Figure 10-7. Priority of Execution: EXTRACT SEC-
PRIMARY ASN ONDARY ASN
┌────────────────┬────────┬────┬────┐ ┌────────────────┬────────┬────┬────┐
│ 'B227' │////////│ R │////│ │ 'B249' │////////│ R │ R │
└────────────────┴────────┴────┴────┘ └────────────────┴────────┴────┴────┘
16 24 28 31 16 24 28 31
The 16-bit SASN, bits 16-31 of control register 3, The contents of a set of general registers and a
is placed in bit positions 16-31 of general register set of access registers that were saved in the last
R. Bits 0-15 of the general register are set to state entry in the linkage stack are restored to the
zeros. registers. Each set of registers begins with reg-
ister R and ends with register R.
Bits 16-23 and 28-31 of the instruction are
ignored. For each of the general registers and the access
registers, the registers are loaded in ascending
Special Conditions order of their register numbers, starting with reg-
ister R and continuing up to and including reg-
The instruction must be executed with DAT on; ister R, with register 0 following register 15.
otherwise, a special-operation exception is recog- Each register is loaded from the position in the
nized. state entry where the contents of the register were
┌──────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B Special-operation exception due to DAT being off, the CPU │
│ being in the secondary-space mode or the address-space- │
│ function control, bit 15 of control register , being zero. │
│ │
│ 8. Access exceptions (fetch) for entry descriptor of the current │
│ linkage-stack entry. │
│ │
│ 9. Stack-type exception due to current entry not being a state │
│ entry or header entry. │
│ │
│ Note: Exceptions 1-14 can occur only if the current entry │
│ is a header entry. │
│ │
│1. Access exceptions (fetch) for second word of the header entry.│
│ │
│11. Stack-empty exception due to backward stack-entry validity │
│ bit in the header entry being zero. │
│ │
│12. Access exceptions (fetch) for entry descriptor of preceding │
│ entry, which is the entry designated by the backward stack- │
│ entry address in the current (header) entry. │
│ │
│13. Stack-specification exception due to preceding entry being a │
│ header entry. │
│ │
│14. Stack-type exception due to preceding entry not being a state │
│ entry. │
│ │
│15. Access exceptions (fetch) for the selected contents of the │
│ state entry. │
└──────────────────────────────────────────────────────────────────────┘
Figure 10-8. Priority of Execution: EXTRACT STACKED REGISTERS
Code (Bits 24-31 of State-Entry Byte Posi- Key-controlled protection does not apply to refer-
Gen. Reg. R) tions Selected ences to the linkage stack.
0 128-135
1 136-143 Bits 16-23 of the instruction and bits 0-23 of
2 144-151 general register R are ignored.
3 152-159
Special Conditions
The format of byte positions 128-159 of the state
entry is as follows: A specification exception is recognized when R is
odd or the code in bit positions 24-31 of general
┌────────┬────────┬────────┬────────┐ register R is greater than 3.
│ PKM │ SASN │ EAX │ PASN │
└────────┴────────┴────────┴────────┘ The CPU must be in the primary-space mode,
128 13 132 134 135 access-register mode, or home-space mode, and
the address-space-function control, bit 15 of
┌───────────────────────────────────┐ control register 0, must be one; otherwise, a
│ PSW │ special-operation exception is recognized.
└───────────────────────────────────┘
136 143 A stack-empty, stack-specification, or stack-type
exception may be recognized during the
In a Branch State Entry unstacking process.
┌─────────────────┬─┬───────────────┐
│ │A│Branch Address │
The operation is suppressed on all addressing
└─────────────────┴─┴───────────────┘
144 148 151 exceptions.
┌──────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B Special-operation exception due to DAT being off, the CPU │
│ being in the secondary-space mode or the address-space- │
│ function control, bit 15 of control register , being zero. │
│ │
│ 8.A Specification exception due to R being odd or bits 24-31 of │
│ general register R having a value greater than 3. │
│ │
│ 8.B.1 Access exceptions (fetch) for entry descriptor of the current │
│ linkage-stack entry. │
│ │
│ 8.B.2 Stack-type exception due to current entry not being a state │
│ entry or header entry. │
│ │
│ Note: Exceptions 8.B.3-8.B.7 can occur only if the current │
│ entry is a header entry. │
│ │
│ 8.B.3 Access exceptions (fetch) for second word of the header entry.│
│ │
│ 8.B.4 Stack-empty exception due to backward stack-entry validity │
│ bit in the header entry being zero. │
│ │
│ 8.B.5 Access exceptions (fetch) for entry descriptor of preceding │
│ entry, which is the entry designated by the backward stack- │
│ entry address in the current (header) entry. │
│ │
│ 8.B.6 Stack-specification exception due to preceding entry being a │
│ header entry. │
│ │
│ 8.B.7 Stack-type exception due to preceding entry not being a state │
│ entry. │
│ │
│ 8.B.8 Access exceptions (fetch) for the selected contents of the │
│ state entry. │
└──────────────────────────────────────────────────────────────────────┘
Figure 10-9. Priority of Execution: EXTRACT STACKED STATE
Condition Code: The code remains unchanged. The contents of general register R have the
format of a segment-table entry, with only the
Program Exceptions: page-table origin used. The contents of general
Access (except for protection, address speci- register R have the format of a virtual address,
fied by general register R) with only the page index used. The contents of
Privileged operation (extraction-authority fields that are not part of the page-table origin or
control is zero in the problem state) page index are ignored.
Special operation
The contents of the general registers just
┌──────────────────────────────────────────────┐ described are as follows:
│ 1.-6. Exceptions with the same priority as │
│ the priority of program-interruption │ ┌─┬─────────────────────────┬──────┐
│ conditions for the general case. │ R │/│ Page-Table Origin │//////│
│ │ └─┴─────────────────────────┴──────┘
│ 7.A Access exceptions for second instruc- │
│ tion halfword. │
1 26 31
│ │
│ 7.B Special-operation exception due to DAT │ ┌────────────┬────────┬────────────┐
│ being off. │
│ │
R │////////////│ PX │////////////│
│ 8. Privileged-operation exception due to │ └────────────┴────────┴────────────┘
│ extraction-authority control, bit 4 of │ 12 2 31
│ control register , being zero. │
│ │
│ 9. Access exceptions (except for protec- │ The page-table origin and the page index desig-
│ tion) for address specified by general │ nate a page-table entry in accordance with the
│ register R. │ dynamic-address-translation rules for page-table
└──────────────────────────────────────────────┘
lookup. The page-table origin is treated as a
Figure 10-11. Priority of Execution: INSERT VIRTUAL 31-bit address, and the addition is performed by
STORAGE KEY using the rules for 31-bit address arithmetic,
regardless of the setting of the addressing mode,
Programming Notes:
which is specified by bit 32 of the current PSW. A
1. Since all bytes in a 4K-byte block are associ- carry into bit position 0 as a result of the addition
ated with the same page and the same of the page index and page-table origin is ignored.
storage key, bits 20-31 of general register R The address formed from these two components
essentially are ignored. is a real address. The page-invalid bit of this
page-table entry is set to one. During this proce-
2. In the access-register mode, access register 0
dure, no page-table-length check is made, and the
designates the primary address space regard-
| page-table entry is not inspected for whether the
less of the contents of access register 0.
| page-invalid bit is already one or for format errors.
Additionally, the page-frame real address con-
INVALIDATE PAGE TABLE tained in the entry is not checked for an
ENTRY addressing exception.
The page-frame real address contained in the 2. The clearing of TLB entries may make use of
designated page-table entry the page-frame real address in the page-table
entry. Therefore, if the page-table entry, when
The execution of INVALIDATE PAGE TABLE in the attached state, ever contained a page-
ENTRY is not completed on the CPU which exe- frame real address that is different from the
cutes it until (1) all entries corresponding to the current value, copies of entries containing the
specified parameters have been cleared from the previous values may remain in the TLB.
TLB of this CPU and (2) all other CPUs in the
configuration have completed any storage 3. INVALIDATE PAGE TABLE ENTRY cannot be
accesses, including the updating of the change safely used to update a shared location in
and reference bits, by using TLB entries corre- main storage if the possibility exists that
sponding to the specified parameters. another CPU or a channel program may also
be updating the location.
Special Conditions 4. The address of the page-table entry for
INVALIDATE PAGE TABLE ENTRY is a 31-bit
When bit positions 8-12 of control register 0 real address, and the address arithmetic is
contain an invalid code, a translation-specification performed by following the normal rules for
exception is recognized. The exception is recog- 31-bit address arithmetic with wraparound at
nized regardless of whether DAT is on or off. 2 - 1. Contrast this with implicit translation
and the translation for LOAD REAL
The operation is suppressed on all addressing and
ADDRESS, both of which, depending on the
protection exceptions.
model, may treat addresses of DAT-table
entries as either real or absolute and may
Condition Code: The code remains unchanged.
result either in wraparound or in an
addressing exception when a carry occurs into
Program Exceptions:
bit position 0. Accordingly, the DAT tables
Addressing (page-table entry) should not be specified to wrap from
Privileged operation maximum storage locations to location 0 and
Protection (fetch and store, page-table entry, should not be placed at storage locations
key-controlled protection, and low-address whose real and absolute addresses are dif-
protection) ferent.
Translation specification (bits 8-12 in control
register 0 only)
When PASN translation is called for and com- 0 Translation and authorization complete;
pleted and any required subspace-replacement parameters loaded
operation on the STD-p is also completed, and 1 Primary ASN or subspace not available;
then either (1) the current primary space-switch- parameters not loaded
event-control bit, bit 0 of control register 1, is one 2 Secondary ASN not available or not author-
or (2) the space-switch-event-control bit in the ized, or secondary subspace not available;
ASTE designated by PASTEO-p is one, condition parameters not loaded
code 3 is set, and the control registers are not 3 Space-switch event specified; parameters not
changed. loaded
When SASN translation is called for and the trans- Program Exceptions:
lation cannot be completed because bit 0 is one in Access (fetch, operand 1)
either the ASN-first-table entry or the ASTE, or if it Addressing (ASN-first-table entry,
can be completed but (1) SASN authorization is ASN-second-table entry, authority-table entry,
called for and the SASN is not authorized, or (2) a dispatchable-unit control table)
subspace-replacement-exception condition exists ASN-translation specification
due to bit 0 or the ASTE sequence number in the Privileged operation
subspace ASTE during a subspace-replacement Special operation
operation on the STD-s, condition code 2 is set, Specification
and the control registers are not changed.
┌────────┬───────────┬───────────┬──────────────────────────────────────────────────┐
│ │ Second- │ │ │
│ │ Operand- │ │ │
│ │ Address │ │ │
│PASN-d │ Bits │ PASN │ Result Field │
│Equals ├─────┬─────┤Translation├────────┬──────┬────────┬───────┬────────┬────────┤
│PASN-old│ 29 │ 3 │ Performed │PSTD-new│AX-new│CR5-new│PKM-new│SASN-new│PASN-new│
├────────┼─────┼─────┼───────────┼────────┼──────┼────────┼───────┼────────┼────────┤
│ Yes │ │ │ No │PSTD-old│AX-old│CR5-old │PKM-d │SASN-d │PASN-d │
│ Yes │ │ 1 │ No │PSTD-old│AX-d │CR5-old │PKM-d │SASN-d │PASN-d │
│ Yes │ 1 │ │ Yes │STD-p │AX-p │CR5-p │PKM-d │SASN-d │PASN-d │
│ Yes │ 1 │ 1 │ Yes │STD-p │AX-d │CR5-p │PKM-d │SASN-d │PASN-d │
│ No │ - │ │ Yes │STD-p │AX-p │CR5-p │PKM-d │SASN-d │PASN-d │
│ No │ - │ 1 │ Yes │STD-p │AX-d │CR5-p │PKM-d │SASN-d │PASN-d │
└────────┴─────┴─────┴───────────┴────────┴──────┴────────┴───────┴────────┴────────┘
Figure 10-13 (Part 1 of 2). Summary of Actions: LOAD ADDRESS SPACE PARAMETERS
┌───────────────────────┬──────────────────────┐
│ First-Operand │ │
│ Bit Positions │ Abbreviation │
├───────────────────────┼──────────────────────┤
│ -15 │ PKM-d │
│ 16-31 │ SASN-d │
│ 32-47 │ AX-d │
│ 48-63 │ PASN-d │
└───────────────────────┴──────────────────────┘
┌──────────────────┬───────────────────────────┐
│ │ Abbreviation Used for │
│ │ the Field When Accessed │
│ │ as Part of │
│ Field in ASN- ├─────────────┬─────────────┤
│ Second-Table │ PASN │ SASN │
│ Entry │ Translation │ Translation │
├──────────────────┼─────────────┼─────────────┤
│ 1-29 │ - │ ATO-s │
│ 32-47 │ AX-p │ - │
│ 48-59 │ - │ ATL-s │
│ 64-95 │ STD-p │ STD-s │
│ 96-127 │ LTD-p │ - │
├──────────────────┴─────────────┴─────────────┤
│Explanation: │
│ │
│ - The field is not used in this case. │
│ │
│ STD-rp is formed from STD-p, and STD-rs is│
│ formed from STD-s, by a subspace- │
│ replacement operation. │
│ │
│ LTD-p is accessed only when the ASF con- │
│ trol is zero. When the ASF control is │
│ one, PASTEO-p is used in the operation, │
│ and it is bits 1-25 of the address of the │
│ ASN-second-table entry. │
└──────────────────────────────────────────────┘
Figure 10-14. Summary of Abbreviations for LOAD
ADDRESS SPACE PARAMETERS
2. Loading of control registers on some models A one is introduced into an unassigned bit
may require a significant amount of time. This position of the PSW (that is, any of bit posi-
is particularly true for changes in significant tions 0, 2-4, or 24-31).
parameters.
The real address corresponding to the second- The addresses of the segment-table entry and
operand virtual address is placed in general reg- page-table entry are treated as 31-bit addresses,
ister R. regardless of the current addressing mode speci-
fied by bit 32 of the current PSW. It is unpredict-
The virtual address specified by the X, B, and able whether the addresses of these entries are
D fields is translated by means of the dynamic- treated as real or absolute addresses.
address-translation facility, regardless of whether
DAT is on or off. Condition code 0 is set when both ART, if appli-
cable, and DAT can be completed, that is, when a
DAT is performed by using a segment-table desig- segment-table designation can be obtained and
nation that depends on the current value of the the entry in each DAT table lies within the speci-
address-space-control bits, bits 16 and 17 of the fied table length and has a zero I bit.
PSW, as shown in the following table:
When PSW bits 16 and 17 are 01 binary and a
segment-table designation cannot be obtained
because of a situation that would normally cause
one of the exceptions shown in the following table,
(1) the interruption code assigned to the exception
is placed in bit positions 16-31 of general register
R, and bit 0 of this register is set to one and bits
When ART is completed normally, the operation is The operation is suppressed on all addressing
continued through the performance of DAT. exceptions.
When the I bit in the segment-table entry is one, Resulting Condition Code:
condition code 1 is set, and the real or absolute 0 Translation available
address of the segment-table entry is placed in 1 Segment-table entry invalid (I bit is one)
general register R. When the I bit in the page- 2 Page-table entry invalid (I bit is one)
table entry is one, condition code 2 is set, and the 3 Segment-table designation not available or
real or absolute address of the page-table entry is segment- or page-table length exceeded
placed in general register R. When either the
segment-table entry or the page-table entry is Program Exceptions:
outside the table, condition code 3 is set, and
Addressing (effective access-list designation,
general register R is loaded with the real or
access-list entry, ASN-second-table entry,
absolute address of the entry that would have
authority-table entry, segment-table entry, or
been fetched if the length violation had not
page-table entry)
occurred. In all these cases, the address placed
ASN-translation specification
in general register R is real or absolute in
Privileged operation
accordance with the type of address that was
Translation specification
used during the attempted translation, a zero is
appended on the left of the resultant 31-bit Programming Note: Caution must be exercised
address to produce a 32-bit result, and the 32-bit in the use of LOAD REAL ADDRESS in a multi-
result is placed in the register. processing configuration. Since INVALIDATE
PAGE TABLE ENTRY may set the I bit in storage
to one before causing the corresponding entries in
In the 24-bit addressing mode, bits 8-31 of general Bits 16-23 and 28-31 of the instruction are
register R designate a real-storage location on a ignored.
word boundary, and bits 0-7 of the register are
ignored. In the 31-bit addressing mode, bits 1-31 Special Conditions
of general register R designate a real-storage
A specification exception is recognized when R is
location on a word boundary, and bit 0 of the reg-
odd.
ister is ignored.
The CPU must be in the primary-space mode,
Because it is a real address, the address desig-
access-register mode, or home-space mode, and
nating the storage word is not subject to dynamic
the address-space-function control, bit 15 of
address translation.
control register 0, must be one; otherwise, a
Special Conditions special-operation exception is recognized.
Condition Code: The code remains unchanged. The operation is suppressed on all addressing and
protection exceptions.
Program Exceptions:
The priority of recognition of program exceptions
Addressing (address specified by general reg- for the instruction is shown in Figure 10-16 on
ister R) page 10-41.
Privileged operation
┌──────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B Special-operation exception due to the CPU being in the real │
│ mode or secondary-space mode or the address-space-function │
│ control, bit 15 of control register , being zero. │
│ │
│ 8.A Specification exception due to R being odd. │
│ │
│ 8.B.1 Access exceptions for entry descriptor of the current linkage-│
│ stack entry. │
│ │
│ 8.B.2 Stack-type exception due to current entry not being a state │
│ entry or header entry. │
│ │
│ Note: Exceptions 8.B.3-8.B.7 can occur only if the current │
│ entry is a header entry. │
│ │
│ 8.B.3 Access exceptions for second word of the header entry. │
│ │
│ 8.B.4 Stack-empty exception due to backward stack-entry validity │
│ bit in the header entry being zero. │
│ │
│ 8.B.5 Access exceptions for entry descriptor of preceding entry, │
│ which is the entry designated by the backward stack-entry │
│ address in the current (header) entry. │
│ │
│ 8.B.6 Stack-specification exception due to preceding entry being a │
│ header entry. │
│ │
│ 8.B.7 Stack-type exception due to preceding entry not being a state │
│ entry. │
│ │
│ 8.B.8 Access exceptions for the modifiable area of the state entry. │
└──────────────────────────────────────────────────────────────────────┘
Figure 10-16. Priority of Execution: MODIFY STACKED STATE
the instruction ending is not true nullification in this When data is moved to or from expanded storage,
case. access-list-controlled, page, and key-controlled
protection apply, and it is unpredictable whether
When a page-translation-exception condition low-address protection applies. The protection
exists as described in the preceding paragraph, mechanisms apply to main storage in the normal
except when the condition is that the page-table way.
entry is outside the page table, the exception is
not recognized if the condition-code-option bit, bit When the first operand is valid in main storage
23 in general register 0, is one; instead, condition and the second operand is valid in expanded
code 1 or 2 is set. Condition code 1 is set in all storage, but the expanded-storage block con-
cases, except that condition code 2 is set if the taining the second operand is unavailable, a
second operand is invalid in both main storage storage-alteration PER event may be recognized,
and expanded storage, regardless of the validity of and the change bit may be set, for the first
the first operand. operand even though the first-operand location
remains unchanged.
When an access exception can be recognized for
both operands, it is unpredictable for which Operation in a Multiple-CPU Configuration
operand an exception is recognized. If one of the
exceptions is a page-translation exception that The references to main storage and to expanded
would cause condition code 1 or 2 to be set, it is storage are not necessarily single-access refer-
unpredictable whether the access exception for ences and are not necessarily performed in a left-
the other operand is recognized or condition code
1 or 2 is set.
Bits 24-27 of general register 1 are used as the MOVE WITH KEY
specified access key. Bits 0-23 and 28-31 of
MVCK D(R,B),D(B),R [SS]
general register 1 are ignored.
┌────────┬────┬────┬────┬─/──┬────┬─/──┐
The contents of general registers 0 and 1 are as │ 'D9' │ R │ R │ B │ D │ B │ D │
follows: └────────┴────┴────┴────┴─/──┴────┴─/──┘
8 12 16 2 32 36 47
┌─────────────────────────┬─────────┐
GR │/////////////////////////│ L │ The first operand is replaced by the second
└─────────────────────────┴─────────┘
24 31 operand. The fetch accesses to the second-
operand location are performed by using the key
specified in the third operand, and the store
┌─────────────────────────┬────┬────┐
accesses to the first-operand location are per-
GR1 │/////////////////////////│Key │////│
└─────────────────────────┴────┴────┘ formed by using the PSW key.
24 28 31
Bit positions 24-27 of general register R are used
as the source access key. Bit positions 0-23 and
L specifies the number of bytes to the right of the
28-31 of the register are ignored.
first byte of each operand. Therefore, the length
in bytes of each operand is 1-256, corresponding The contents of general register R are a 32-bit
to a length code in L of 0-255. unsigned value called the true length.
The fetch accesses to the second-operand The contents of the general registers just
location are performed by using the PSW key, and described are as follows:
the store accesses to the first-operand location
are performed by using the key specified in ┌──────────────────────────────────┐
general register 1. R │ True Length │
└──────────────────────────────────┘
Each of the operands is processed left to right. 31
When the operands overlap destructively in real
storage, the results in the first-operand location ┌────────────────────────┬────┬────┐
are unpredictable. Except for this unpredictability R │////////////////////////│Key │////│
└────────────────────────┴────┴────┘
in the case of destructive overlap, the storage-
24 28 31
operand-consistency rules are the same as for the
MOVE (MVC) instruction.
┌────────────────┬────┬─/──┬────┬─/──┐
Resulting Condition Code: │ 'E5E' │ B │ D │ B │ D │
└────────────────┴────┴─/──┴────┴─/──┘
0 True length less than or equal to 256 16 2 32 36 47
1 --
2 --
3 True length greater than 256 The first operand is replaced by the second
operand. The accesses to the source-operand
Program Exceptions: location are performed by using the key specified
in general register 1, and the accesses to the
Access (fetch, operand 2; store, operand 1) destination-operand location are performed by
Privileged operation (selected PSW-key-mask using the PSW key.
bit is zero in the problem state)
The first and second operands are of the same
length, which is specified by bits 24-31 of general
register 0. Bits 0-23 of general register 0 are
ignored.
A page-in operation is performed which transfers a If the expanded-storage block is not available, that
4K-byte block to the real-storage location desig- is, the block is not provided or is not currently in
nated by general register R from the expanded- the configuration, then condition code 3 is set, and
storage block designated by general register R. no other action is taken.
Bits 16-23 of the instruction are ignored. Operation of PAGE IN in a Multiple-CPU Con-
figuration
The contents of general register R are a 32-bit
unsigned binary integer called the expanded- The accesses to main storage and to expanded
storage-block number. This number designates storage by PAGE IN are not necessarily single-
the 4K-byte block of expanded storage which is to access references and are not necessarily per-
be transferred. If the expanded-storage-block formed in a left-to-right direction, as observed by
number designates an inaccessible block in other CPUs and by channel programs.
expanded storage, condition code 3 is set.
See also the description under PAGE OUT.
The contents of general register R are a real
Resulting Condition Code:
address which designates a 4K-byte block in main
storage. In the 24-bit-addressing mode, bits 8-19 0 Page-in operation completed
designate the block, and bits 0-7 are ignored. In 1 Expanded-storage data error
the 31-bit-addressing mode, bits 1-19 designate 2 --
the block, and bit 0 is ignored. In both modes, 3 Expanded-storage block not available
bits 20-31 of the address are ignored.
Program Exceptions:
Because it is a real address, the address desig-
Addressing (block designated by general reg-
nating the main-storage block is not subject to
ister R)
dynamic address translation. PAGE IN is not
Operation (if the expanded-storage facility is
subject to key-controlled storage protection, but
not installed)
low-address protection does apply. PAGE IN is
Privileged operation
not subject to program-event recording for storage
Protection (block designated by general reg-
alteration.
ister R; low-address protection)
It is unpredictable whether the page-in operation Programming Note: The fact that it is unpredict-
causes change-bit action. However, if the able whether the page-in operation performs
asynchronous-pageout facility is installed, PAGE change-bit action is usually not a problem
IN sets the change bit and reference bit to one. because the normal action after executing PAGE
IN is to set the storage key with the change bit
A serialization and checkpoint-synchronization zero. However, when PAGE IN is being simulated
function is performed before the operation begins by a host program on behalf of the guest, special
and again after the operation is completed. precautions must be taken in order for the host
not to lose track of the fact that the page has
If the page-in operation is completed with no been changed.
errors, condition code 0 is set.
The contents of general register R are a real If two or more CPUs issue PAGE IN or PAGE
address which designates a 4K-byte block in main OUT instructions at approximately the same
storage. In the 24-bit-addressing mode, bits 8-19 instant in time, depending on the model, the oper-
designate the block, and bits 0-7 are ignored. In ations may be performed one at a time, or the
the 31-bit-addressing mode, bits 1-19 designate operations may be performed concurrently. Con-
the block, and bit 0 is ignored. In both modes, current operation may occur even if the
bits 20-31 of the address are ignored. instructions address the same expanded-storage
block.
Because it is a real address, the address desig-
nating the main-storage block is not subject to When two or more PAGE OUT instructions
dynamic address translation. PAGE OUT is not addressing the same expanded-storage block are
subject to key-controlled protection. executed concurrently, the resulting values in the
expanded-storage block for each group of bytes
A serialization and checkpoint-synchronization transferred may be from any of the instructions
function is performed before the operation begins being executed simultaneously. The number of
and again after the operation is completed. bytes transferred as a group depends on the
model.
Depending on the model, after the data has been
written to the expanded-storage block, a read- Similarly, for concurrent execution of a PAGE IN
back-check operation may be performed to deter- and a PAGE OUT instruction for the same
mine whether the data was written correctly. If the expanded-storage block, the resulting values for
read-back-check operation determines that the each group of bytes transferred as a result of the
data has been written correctly, condition code 0 execution of the PAGE IN instruction may be
is set. If the read-back-check operation either the old or new values from the expanded-
encounters an expanded-storage data error, con- storage block.
dition code 1 is set.
Concurrent operation of paging instructions does
Most models do not perform the read-back-check not result in expanded-storage data errors.
operation, and, after the page-out operation is
completed, condition code 0 is set. Resulting Condition Code:
0 Page-out operation completed
Basic PROGRAM CALL loads the addressing- In both PC-cp and PC-ss, the SASN and SSTD
mode bit, updated instruction address, and are set equal to the original PASN and PSTD,
problem-state bit from the PSW into general reg- respectively. However, the space-switching
Second-Operand Address
Bits 128-143 of the ETE have the following
┌──────PC Number──────┐ detailed format:
┌────────────┬────────────┬────────┐
│////////////│ LX │ EX │ ┌─┬──┬─┬─┬─┬─┬─┬────┬────┐
└────────────┴────────────┴────────┘ │T│ │K│M│E│C│S│ EK │ │
12 24 31 └─┴──┴─┴─┴─┴─┴─┴────┴────┘
128 131 136 143
Linkage Index (LX): Bits 12-23 of the second-
operand address are the linkage index and are When bit 32 of the ETE is zero (24-bit addressing
used to select an entry from the linkage table des- mode), bits 33-39 of the ETE must be zeros; oth-
ignated by the linkage-table designation. When erwise, a PC-translation-specification exception is
the ASF control, bit 15 of control register 0, is recognized.
zero, the linkage-table designation is in control
register 5. When the ASF control is one, the After the ETE has been fetched, if the current
linkage-table designation is in the primary PSW specifies the problem state, the current
ASN-second-table entry (primary ASTE), and the PSW-key mask in control register 3 is tested
primary-ASTE origin is in control register 5. against the AKM field in the ETE to determine
whether the program is authorized to access this
Entry Index (EX): Bits 24-31 of the second- entry. The AKM and PSW-key mask are ANDed,
operand address are the entry index and are used and, if the result is zero, a privileged-operation
to select an entry from the entry table designated exception is recognized. The PSW-key mask in
by the linkage-table entry. control register 3 remains unchanged. When
PROGRAM CALL is executed in the supervisor
Bits 0-11 of the second-operand address are state, the AKM field is ignored.
ignored.
If the result of the AND of the AKM and the
The linkage-table and entry-table lookup process PSW-key mask is not zero, or if the CPU is in the
is depicted in part 1 of Figure 10-21 on supervisor state, the execution of the instruction
page 10-59. The detailed definition of this table- continues.
lookup process is in “PC-Number Translation” on
page 5-27. The 16-byte entry-table entry (ETE) is If a 16-byte ETE has been fetched, or if a 32-byte
identical to the first 16 bytes of the 32-byte ETE. ETE has been fetched but bit 128 of the ETE (T)
The 32-byte ETE has the following format: is zero, the basic PROGRAM CALL operation is
specified. If a 32-byte ETE has been fetched and
Basic PROGRAM CALL When bit 131 of the ETE (K) is zero, bits 8-11 of
the PSW (the PSW key) remain unchanged.
The following operations are performed when When bit 131 of the ETE is one, bits 136-139 of
basic PROGRAM CALL is specified. the ETE (the EK) replace the PSW key in the
PSW.
Bits 32-62 of the current PSW (the addressing-
mode bit and the updated instruction address) are When bit 132 of the ETE (M) is zero, bits 96-111
placed in bit positions 0-30 of general register 14. of the ETE (the EKM) are ORed with the PSW-key
Bit 15 of the PSW (the problem-state bit) is placed mask, bits 0-15 of control register 3, and the result
in bit position 31 of general register 14. replaces the PSW-key mask in control register 3.
When bit 132 of the ETE is one, bits 96-111 of the
Bits 32-62 of the ETE (A and the EIA), with a zero ETE replace the PSW-key mask in control register
appended on the right, are placed in PSW bit 3.
positions 32-63 (the addressing-mode bit and the
instruction address). Bit 63 of the ETE (P) is When bit 133 of the ETE (E) is zero, the EAX, bits
placed in PSW bit position 15 (the problem-state 0-15 of control register 8, remains unchanged.
bit). When bit 133 of the ETE is one, bits 144-159 of
the ETE (the EEAX) replace the EAX in control
The PSW-key mask, bits 0-15 of control register 3, register 8.
is placed in bit positions 0-15 of general register 3,
and the current PASN, bits 16-31 of control reg- When bit 134 of the ETE (C) is zero, bits 16 and
ister 4, is placed in bit positions 16-31 of general 17 of the PSW (the address-space-control bits)
register 3. are set to 00 binary (primary-space mode). When
bit 134 of the ETE is one, the address-
Bits 96-111 of the ETE (the EKM) are ORed with space-control bits in the PSW are set to 01 binary
the PSW-key mask, bits 0-15 of control register 3, (access-register mode).
and the result replaces the PSW-key mask in
control register 3. Bits 64-95 of the ETE (the entry parameter) are
loaded into general register 4.
Bits 64-95 of the ETE (the entry parameter) are
loaded into general register 4. Key-controlled protection does not apply to refer-
ences to the linkage stack, but low-address and
Stacking PROGRAM CALL page protection do apply.
The following operations are performed when PROGRAM CALL to Current Primary (PC-cp)
stacking PROGRAM CALL is specified.
If bits 16-31 of the ETE (the ASN) are zeros,
The stacking process is performed to form a PROGRAM CALL to current primary (PC-cp) is
linkage-stack program-call state entry and place specified, and the execution of the instruction is
the following information in the state entry: completed after the operations described in
current PSW (with an unpredictable PER mask), “PROGRAM CALL PC-Number Translation” and
PSW-key mask, PASN, SASN, EAX, called-space either “Basic PROGRAM CALL” or “Stacking
identification, program-call number, contents of PROGRAM CALL” have been performed and the
general registers 0-15, and contents of access following operations have been performed.
registers 0-15. This is described in “Stacking
Process” on page 5-73. The entry-type code in The current PASN, bits 16-31 of control register 4,
the state entry is 0000101 binary. is placed in bit positions 16-31 of control register 3
to become the current SASN.
Bits 32-62 of the ETE (A and the EIA), with a zero
appended on the right, are placed in PSW bit The current PSTD, bits 0-31 of control register 1,
positions 32-63 (the addressing-mode bit and the is placed in control register 7 to become the
instruction address). Bit 63 of the ETE (P) is current SSTD.
R: Address is real.
: In stacking PC, PC number is placed in linkage stack.
: Second 16 bytes of ETE exist only if CR.15 = 1.
Figure 10-21 (Part 1 of 4). Execution of PROGRAM CALL
PSW ┌──────┬─┬──────┬─┬──────────┬─┐
before│ │P│ │A│ IA ││
└──────┴┬┴──────┴┬┴─────┬────┴─┘
│ │ │
└────────┼──────┼─────┐
│ │ │
GR14 ┌─┬──────────┬─┐
after│A│ IA │P│
└─┴──────────┴─┘
Figure 10-21 (Part 2 of 4). Execution of PROGRAM CALL
: If PC-ss and S=1, SASN is replaced by new PASN, and SSTD is replaced by new PSTD.
Figure 10-21 (Part 3 of 4). Execution of PROGRAM CALL
R: Address is real.
: If CR.15 = 1, ASTE address may be obtained by ASN translation or directly from ETE.
: ASTE is 64 bytes if CR.15 = 1; last 48 bytes are not shown.
: If subspace-group facility installed and CR.15 = 1, bits 1-23 and 25-31 of PSTD
may be replaced from a subspace STD.
Programming Note: To ensure predictable oper- address in the entry-table entry must be the same
ation of PC-ss when the address-space-function as the one that would result from ASN translation
control is one, the ASN-second-table-entry of the ASN in the entry-table entry.
┌───────────────────────┬───────────────────────┐
The PCF entry table resides in real storage, is │ │ Entry Parameter │
8K-bytes long on a 4K-byte boundary, and con- └───────────────────────┴───────────────────────┘
448 48 511
tains 128 64-byte entries.
The 31-bit real address of the PCF-entry-table Bits 64-160, 186-223, and 320-479 in the
entry is obtained by appending 12 zeros on the PCF-entry-table entry are reserved for future
right to the PCF-entry-table origin and adding the extensions and should be zeros; otherwise, the
EX, with 6 rightmost and 18 leftmost zeros program may not operate compatibly in the future.
appended. When a carry into bit position 0 occurs
during the addition, an addressing exception may The PCF-entry-table entry causes a space-
be recognized, or the carry may be ignored, switching operation to occur if it contains a
causing the table to wrap from 2 - 1 to zero. nonzero ASN. When the PCF-entry-table entry
All 31 bits of the address are used, regardless of contains a zero ASN, the operation is called
If the ASN in the PCF-entry-table entry is zero, Bits 161-185 of the PCF-entry-table entry (the
PROGRAM CALL FAST to current primary is ASTEO) are placed in bit positions 1-25 of control
specified, and the execution of the instruction is register 5 as the new primary-ASTE origin, and
completed after the following operations have zeros are placed in bit positions 0 and 26-31.
been performed.
The PASN existing before the PASN is replaced
A stacking process is performed to form a linkage- from the PCF-entry-table entry is placed in bit
stack program-call state entry and place the fol- positions 16-31 of control register 3 to become the
lowing information in the state entry: current PSW current SASN, and the PSTD existing before the
(with an unpredictable PER mask), PSW-key PSTD is replaced from the PCF-entry-table entry
mask, PASN, SASN, EAX, called-space identifica- is placed in control register 7 to become the
tion, program-call number, contents of general current SSTD. (The SASN and SSTD are set
registers 0-15, and contents of access registers equal to the old PASN and PSTD, respectively.)
0-15. This is described in “Stacking Process” on
page 5-73. The entry-type code in the state entry Bits 288-303 of the PCF-entry-table entry (the
is 0000101 binary. The called-space identification PKM) replace the PSW-key mask in bit positions
in a program-call state entry formed by either 0-15 of control register 3.
PCF-cp or PCF-ss is always all zeros.
PROGRAM CALL FAST Serialization
Bits 8-63 of the PCF-entry-table entry are placed
in PSW bit positions 8-63. A serialization and checkpoint-synchronization
function is performed before the operation begins
Bits 480-511 of the PCF-entry-table entry (the and again after the operation is completed.
entry parameter) are loaded into general register
4. Special Conditions
Key-controlled protection does not apply to refer- The operation can be performed successfully only
ences to the linkage stack, but low-address and when the CPU is in the primary-space mode or
page protection do apply. access-register mode at the beginning of the oper-
ation and the address-space-function control, bit
PROGRAM CALL FAST with Space Switching 15 of control register 0, is one. If either of these
(PCF-ss) Operations rules is violated, a special-operation exception is
recognized.
If the ASN in the PCF-entry-table entry is nonzero,
PROGRAM CALL FAST with space switching Bits 304-319 (flags) of the PCF-entry-table entry
(PCF-ss) is specified, and the execution of the are available to control the operation. If any of
instruction is completed after the operations speci- bits 304-319 is a one, an EX-translation exception
fied in “PROGRAM CALL FAST to current primary is recognized in both the problem and supervisor
(PCF-cp)” have been performed and the following states. The program-call number is stored in bit
operations have been performed. positions 12-31 of the word at real location 144,
bits 0-10 of the word are set to zeros, and bit 11
Bits 272-287 of the PCF-entry-table entry (the of the word is set to one to indicate that the
ASN) are placed in bit positions 16-31 of control exception was recognized by PROGRAM CALL
register 4 as the new PASN. FAST.
The PSW, except for the PER-mask bit and the PASN Translation
condition code, saved in the last linkage-stack
If the new PASN is equal to the old PASN in bit
state entry is restored as the current PSW. The
positions 16-31 of control register 4, PASN trans-
PER mask in the current PSW remains
lation is not performed, and the authorization
unchanged. The resulting value of the condition
index (AX), PASN, PSTD, and
code in the current PSW is unpredictable. The
primary-ASN-second-table-entry (primary-ASTE)
contents of general registers 2-14 and access reg-
origin in the control registers are not changed.
isters 2-14 also are restored from the state entry.
When the entry-type code in the entry descriptor
If the new PASN is not equal to the old PASN, the
of the state entry is 0000101 binary, indicating a
| new PASN replaces the PASN in bit positions
program-call state entry, the primary ASN (PASN),
| 16-31 of control register 4 and is translated to
secondary ASN (SASN), PSW-key mask (PKM),
locate a 64-byte ASTE. The ASN table-lookup
and extended authorization index (EAX) in the
process is described in “ASN Translation” on
control registers also are restored from the state
page 3-18. The exceptions associated with ASN
entry. When the entry-type code is 0000100
translation are collectively called ASN-translation
binary, indicating a branch state entry, the current
exceptions. These exceptions and their priority
PASN, SASN, PKM, and EAX remain unchanged.
are described in Chapter 6, “Interruptions.”
The last state entry is located, and information in it
Bits 64-95 of the ASTE are placed in control reg-
is restored, as described in “Unstacking Process”
ister 1 as the new PSTD. Bits 32-47 of the ASTE
on page 5-75. The state entry is logically deleted
are placed in bit positions 0-15 of control register
from the linkage stack, and the linkage-stack-entry
4 as the new AX. Bits 1-25 of the ASTE address
address in control register 15 is replaced by the
are placed in bit positions 1-25 of control register
address of the next preceding state or header
5 as the new primary-ASTE origin, and zeros are
entry. This also is described in “Unstacking
placed in bit positions 0 and 26-31.
Process.”
The description in this paragraph applies if the
When the state entry is a program-call state entry,
subspace-group facility is installed and PASN
it causes a space-switching operation to occur if it
translation has occurred. If (1) the subspace-
contains a PASN that is not equal to the current
group-control bit, bit 22, in the new PSTD is one,
PASN. When the state entry contains a PASN
(2) the dispatchable unit is subspace active, and
that is equal to the current PASN, the operation is
(3) the new primary-ASTE origin designates the
called PROGRAM RETURN to current primary
ASTE for the base space of the dispatchable unit,
(PR-cp); when the state entry contains a PASN
then bits 1-23 and 25-31 of the new PSTD in
that is not equal to the current PASN, the opera-
control register 1 are replaced by bits 1-23 and
tion is called PROGRAM RETURN with space
25-31 of the STD in the ASTE for the subspace in
switching (PR-ss). PASN translation occurs in
which the dispatchable unit last had control. This
PR-ss. SASN translation and authorization may
replacement occurs, in the case when the new
occur in either PR-cp or PR-ss. The terms PR-cp
SASN is equal to the new PASN, before the
and PR-ss do not apply when the state entry is a
SSTD is set equal to the PSTD. Further details
branch state entry.
are in “Subspace-Replacement Operations” on
page 5-59.
Key-controlled protection does not apply to
accesses to the linkage stack, but low-address
and page protection do apply.
┌──────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program-│
│ interruption conditions for the general case. │
│ │
│ 7. Special-operation exception due to DAT being off, the CPU │
│ being in secondary-space mode or home-space mode, or the │
│ address-space-function control, bit 15 of control register ,│
│ being zero. │
│ │
│ 8.A Trace exceptions. │
│ │
│ 8.B.1 Access exceptions (fetch) for entry descriptor of the current│
│ linkage-stack entry. │
│ │
│ 8.B.2 Stack-type exception due to current entry not being a state │
│ entry or header entry. │
│ │
│ Note: Exceptions 8.B.3-8.B.7 can occur only if the current │
│ entry is a header entry. │
│ │
│ 8.B.3 Stack-operation exception due to unstack-suppression bit │
│ in the header entry being one. │
│ │
│ 8.B.4 Access exceptions (fetch) for second word of the header │
│ entry. │
│ │
│ 8.B.5 Stack-empty exception due to backward stack-entry validity │
│ bit in the header entry being zero. │
│ │
│ 8.B.6 Access exceptions (fetch) for entry descriptor of preceding │
│ entry, which is the entry designated by the backward │
│ stack-entry address in the header entry. │
│ │
│ 8.B.7 Stack-specification exception due to preceding entry being a │
│ header entry. │
└──────────────────────────────────────────────────────────────────────┘
Figure 10-23 (Part 1 of 2). Priority of Execution: PROGRAM RETURN
Program Exceptions:
Privileged operation
| The instruction address space is the address Unassigned fields in the PSW may be assigned in
| space from which instructions are fetched. It is the future and may then be among those restored
| composed of real addresses if DAT is off. by RESUME PROGRAM. Therefore, these fields
in the PSW field in the second operand should
The parameter list has the following format: contain zeros; otherwise, the program may not
operate compatibly in the future.
┌────────────────┬─────────────────┐
││Offset of PSW Fld│ The fields in the second operand are fetched
└────────────────┴─────────────────┘ before the contents of access register B and
16 331 general register B are changed.
┌────────────────┬─────────────────┐
│Offset of AR Fld│Offset of GR Fld │ When RESUME PROGRAM is the target of an
└────────────────┴─────────────────┘ EXECUTE instruction, the parameter list imme-
32 48 663 diately follows the RESUME PROGRAM instruc-
tion, not the EXECUTE instruction.
Bits 16-31 of the parameter list are an unsigned
The references to the parameter list are storage-
binary integer that is the offset in bytes from the
operand fetches, not instruction fetches.
beginning of the second operand to a field that
has the format of a PSW and from which fields in
Special Conditions
the current PSW will be replaced. Bits 32-47 and
48-63 similarly are offsets to four-byte fields from The instruction is completed only if bits 32-63 of
which the contents of access register B and the PSW field in the second operand are valid for
general register B, respectively, will be replaced. placement in the current PSW. If bit 32 is zero
Bits 0-15 must be zeros; otherwise, a specification and bits 33-39 are not all zeros, or if bit 63 is one,
exception is recognized. a specification exception is recognized.
A PSW has the following format: When DAT is on, the address-space-function
┌─┬─┬─────┬─┬─┬─┬─────┬─┬─┬─┬─┬───┬───┬──────┬───────────────┐ control, bit 15 of control register 0, must be one
│ │ │ │ │I│E│ │ │ │ │ │ │ │ Prog │ │
││R│ │T│O│X│ Key │1│M│W│P│A S│C C│ Mask │ │
when the operation is to set the access-register
└─┴─┴─────┴─┴─┴─┴─────┴─┴─┴─┴─┴───┴───┴──────┴───────────────┘ mode; otherwise, a special-operation exception is
5 8 12 16 18 2 24 31
recognized. Also, the CPU must be in the super-
┌─┬──────────────────────────────────────────────────────────┐
│ │ │ visor state when the operation is to set the home-
│A│ Instruction Address │ space mode; otherwise, a privileged-operation
└─┴──────────────────────────────────────────────────────────┘
32 63 exception is recognized. When DAT is off, the
values of bits 16 and 17 of the PSW field in the
second operand are not tested.
SET ADDRESS SPACE CONTROL The following figure summarizes the operation of
SET ADDRESS SPACE CONTROL and SET
SAC D(B) [S] ADDRESS SPACE CONTROL FAST:
┌────────────────┬────┬────────────┐ ┌──────────────────────────────────────────────┐
│ 'B219' │ B │ D │ │ Second-Operand Address │
└────────────────┴────┴────────────┘ │ ┌────────────────────┬────┬────────┐ │
16 2 31 │ │////////////////////│Code│////////│ │
│ └────────────────────┴────┴────────┘ │
│ 2 24 31 │
│ │
SET ADDRESS SPACE CONTROL │ Result in │
│ PSW Bits │
FAST │ Code Name of Mode 16 and 17 │
│ │
SACF D(B) [S] │ Primary space │
│ 1 Secondary space 1 │
┌────────────────┬────┬────────────┐ │ 1 Access register 1 │
│ 'B279' │ B │ D │ │ 11 Home space 11 │
└────────────────┴────┴────────────┘ │ All others Invalid Unchanged │
16 2 31 └──────────────────────────────────────────────┘
Access (fetch, operand 2) Only those bits of the operand are set in the CPU
Privileged operation timer that correspond to the bit positions to be
Specification updated; the contents of the remaining rightmost
bit positions of the operand are ignored and are
not preserved in the CPU timer.
Bits 16-23 and 28-31 of the instruction are The authority-table origin from the ASTE is used
ignored. as a base for a third table lookup. The current
authorization index, bits 0-15 of control register 4,
is used, after it has been checked against the
authority-table length, as the index to locate the
┌──────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword. │
│ │
│ 7.B Special-operation exception due to DAT being off, or the ASN- │
│ translation control, bit 12 of control register 14, being │
│ zero. │
│ │
│ 8.A Trace exceptions. │
│ │
│ 8.B.1 ASN-translation exceptions (SSAR-ss only). │
│ │
│ Note: Subspace-replacement exceptions, which are not shown │
│ in detail in this figure, can occur with any priority after │
│ 8.B.1. │
│ │
│ 8.B.2 Secondary-authority exception due to authority-table entry │
│ being outside table (SSAR-ss only). │
│ │
│ 8.B.3 Addressing exception for access to authority-table entry │
│ (SSAR-ss only). │
│ │
│ 8.B.4 Secondary-authority exception due to S bit in authority- │
│ table entry being zero (SSAR-ss only). │
└──────────────────────────────────────────────────────────────────────┘
Figure 10-28. Priority of Execution: SET SECONDARY ASN
R: Address is real.
: ASTE is 64 bytes if CR.15 = 1; last 48 bytes are not shown.
: For SSAR-ss only, if subspace-group facility installed and CR.15 = 1, bits 1-23 and
25-31 of SSTD may be replaced from a subspace STD.
Figure 10-29. Execution of SET SECONDARY ASN
┌────────────────┬────────┬────┬────┐ ┌────────┬────────┬────┬────────────┐
│ 'B22B' │////////│ R │ R │ │ '8' │////////│ B │ D │
└────────────────┴────────┴────┴────┘ └────────┴────────┴────┴────────────┘
16 24 28 31 8 16 2 31
The storage key for the 4K-byte block that is Bits 0-7 of the current PSW are replaced by the
addressed by the contents of general register R byte at the location designated by the second-
is replaced by bits from general register R. operand address.
Bits 16-23 of the instruction are ignored. Bits 8-15 of the instruction are ignored.
| For any store access, by any CPU or channel The operation is suppressed on all addressing and
| program, completed to the designated 4K-byte protection exceptions.
| block either before or after the execution of this
| instruction, the associated setting of the reference Condition Code: The code remains unchanged.
| and change bits to one in the storage key for the
| block also is completed before or after, respec- Program Exceptions:
| tively, the execution of this instruction. Access (fetch, operand 2)
Privileged operation
Condition Code: The code remains unchanged.
Special operation
Specification
Program Exceptions:
Addressing (address specified by general reg-
ister R)
Privileged operation
The current value of the clock comparator is Condition Code: The code remains unchanged.
stored at the doubleword location designated by
the second-operand address. Program Exceptions:
Zeros are provided for the rightmost bit positions Access (store, operand 2)
of the clock comparator that are not compared Privileged operation
with the TOD clock. Specification
The information stored has the following format: 1. The program should allow for the possibility
that the CPU identification number may
┌────────┬──────────────────────────┐ contain the digits A-F as well as the digits 0-9.
│Version │ CPU Identification │
│ Code │ Number │ | 2. When the format bit in bit position 48 of the
└────────┴──────────────────────────┘ | second operand is zero, the CPU identification
8 31 number, in conjunction with the machine-type
number, provides a unique CPU identification
| ┌─────────────────┬─┬───────────────┐ that can be used in associating results with an
| │ Machine-Type │ │ │ individual machine.
| │ Number │F││
| └─────────────────┴─┴───────────────┘ | When the format bit is one, the
32 48 63 | CPU-identification number identifies the
| system configuration as opposed to an indi-
| vidual CPU within the configuration, and it
| Bits 6-15 and 21-31 are reserved for indication of Depending on a function code in general register
new facilities. The bits are currently stored as 0, either an identification of the level of the config-
zeros but may be stored as ones in the future. uration executing the program is placed in general
register 0 or information about a component or
The second-operand address is ignored but components of a configuration is stored in a
should be zero to permit possible future exten- system-information block (SYSIB). When informa-
sions. tion about a component or components is
requested, the information is specified by further
Key-controlled and low-address protection do not contents of general register 0 and by contents of
apply. general register 1. The SYSIB, if any, is desig-
nated by the second-operand address.
Condition Code: The code remains unchanged.
The machine is considered to provide one, two, or
Program Exceptions: three levels of configuration. The levels are:
| Operation (if z/Architecture is not installed) 1. The basic machine, which is the machine as if
Privileged operation it were operating in the basic mode.
2. A logical partition, which is provided if the
machine is operating in the LPAR, or logically-
partitioned, mode. A logical partition is pro-
Reserved: The contents of words 0-7, 13-15, May not use the same method to determine
and 25-63 are reserved and are stored as zeros. the contents of fields such as the sequence-
The contents of words 64-1023 are reserved and code field.
Condition Code: The code remains unchanged. Bits 0-7 of the current PSW are stored at the first-
operand location. Then the contents of bit posi-
tions 0-7 of the current PSW are replaced by the
logical OR of their original contents and the
second operand.
2. When an ALET equal to 00000000 hex is program. Condition code 0 of TEST ACCESS
passed during a program linkage performed indicates a 00000000 hex ALET so that the
by PROGRAM CALL with space switching ALET can be changed to 00000001 hex by
(PC-ss), and the ALET conceptually desig- the called program.
nates the calling program's primary address
3. PROGRAM CALL to current primary (PC-cp)
space and the called program's secondary
sets the secondary address space equal to
address space, the ALET must be changed to
the primary address space. PC-ss sets the
00000001 hex before it is used by the called
secondary address space equal to the calling
Access-register translation applies to TEST The trace entry is composed of an entry-type iden-
PROTECTION only when the CPU is in the tifier, a count of the number of general registers
access-register mode (DAT is on), whereas it whose contents are placed in the entry, bits 16-63
applies to LOAD REAL ADDRESS when PSW of the TOD clock, the second operand, and the
bits 16 and 17 are 01 binary regardless of contents of a range of general registers. The
whether DAT is on or off. When condition general registers are stored in ascending order of
code 3 is set because of an exception condi- their register numbers, starting with general reg-
tion in access-register translation, LOAD ister R and continuing up to and including
REAL ADDRESS, but not TEST PRO- general register R, with general register 0 fol-
TECTION, returns in a general register the lowing general register 15. The trace table and
program-interruption code assigned to the the trace-entry formats are described in “Tracing”
exception. When access-register translation is on page 4-10.
Trap-Program Address: Bits 1-31 of bytes Trap Flags: Information identifying the
20-23 form the 31-bit primary virtual address of instruction(s) causing the trap operation is stored
the trap program. Bit 0 of bytes 20-23 is ignored. in byte positions 0-3. The detailed format of bytes
0-3 is as follows:
Bytes 0-11, 16-19, 24-27, and 32-63 of the trap
control block are reserved and should contain Flag Bits Meaning
zeros. Bytes 28-31 are available for use by pro- 0 TRAP was target of EXECUTE
gramming. 1 TRAP is TRAP4 (not TRAP2)
2-12 Reserved, zeros stored
Trap Save Area 13-14 Instruction-length code (ILC)
15-31 Reserved, zeros stored
The trap save area is 256 bytes aligned on a
doubleword boundary. Bit 0 of bytes 0-3 is set to one if TRAP was the
target of an EXECUTE instruction.
The trap operation stores information into the trap
save area as follows: Bit 1 of bytes 0-3 is set to one if TRAP is TRAP4
(not TRAP2).
Bits 2-12 and 15-31 are reserved and are stored The wait-state, problem-state, address-
as zeros. space-control, condition-code, program-mask, and
addressing-mode values specify the state of the
Second-Operand Address of TRAP4: For CPU before the TRAP instruction was executed.
TRAP4, the second-operand address, generated The instruction-address value is the updated
| under the control of the current addressing mode instruction address, which is the address of the
| and with a zero appended on the left, is stored in instruction following TRAP, or the address of the
byte positions 8-11. For TRAP2, all zeros are instruction following EXECUTE if TRAP was the
stored in those byte positions. target of EXECUTE.
Access Register 15: The contents of access General Registers 0-15: The contents of general
register 15 are stored in byte positions 12-15. registers 0-15 are stored in byte positions 32-95.
They are stored in ascending order of register
PSW Values: Certain information from the numbers, starting with register 0 and continuing up
current PSW is stored in byte positions 16-23. to and including register 15.
The PSW has the following format:
┌─┬─┬─────┬─┬─┬─┬─────┬─┬─┬─┬─┬───┬───┬──────┬───────────────┐
Bytes 24-31 are reserved, and zeros are stored in
│ │ │ │ │I│E│ │ │ │ │ │ │ │ Prog │ │ these byte positions. Bytes 96-255 remain
││R│ │T│O│X│ Key │1│M│W│P│A S│C C│ Mask │ │
└─┴─┴─────┴─┴─┴─┴─────┴─┴─┴─┴─┴───┴───┴──────┴───────────────┘ unchanged. Bytes 96-159 and 168-255 are
5 8 12 16 18 2 24 31 reserved. Bytes 160-167 are available for use by
┌─┬──────────────────────────────────────────────────────────┐ programming.
│ │ │
│A│ Instruction Address │
└─┴──────────────────────────────────────────────────────────┘ Special Conditions
32 63
┌──────────────────────────────────────────────────────────────────────────┐
│ 1.-6. Exceptions with the same priority as the priority of program- │
│ interruption conditions for the general case. │
│ │
│ 7.A Access exceptions for second instruction halfword (TRAP4 │
│ only). │
│ │
│ 7.B.1 Operation exception if the trap facility is not installed. │
│ │
│ 7.B.2.A Special-operation exception due to the CPU not being in the │
│ primary-space mode or access-register mode. │
│ │
│ 7.B.2.B.1 Addressing exception for access to dispatchable-unit control │
│ table. │
│ │
│ 7.B.2.B.2 Special-operation exception due to bit 31 in bytes 44-47 of │
│ dispatchable-unit control table being zero. │
│ │
│ 8.A Trace exceptions. │
│ │
│ 8.B.1 Access exceptions (fetch) for trap control block. │
│ │
│ 8.B.2 Access exceptions (store) for trap save area. │
└──────────────────────────────────────────────────────────────────────────┘
Figure 10-34. Priority of Execution: TRAP
The machine-check-handling mechanism provides ensure the integrity of system operation and to
extensive equipment-malfunction detection to permit automatic recovery from some malfunc-
Validating a checking block does not ensure that a When invalid CBC is detected in storage, a
valid CBC will be observed the next time the machine-check condition may occur; depending on
checking block is accessed. If the failure is solid, the circumstances, the machine-check condition
validation is effective only if the information placed may be system damage, instruction-processing
in the checking block is such that the failing bits damage, or system recovery. If the invalid CBC is
are set to the value to which they fail. If an detected as part of the execution of a channel
attempt is made to set the bits to the state oppo- program, the error is reported as an I/O-error con-
site to that in which they fail, then the validation dition. When a CCW, indirect-data-address word,
will not be effective. Thus, for a solid failure, vali- or data is prefetched from storage, is found to
dation is only useful to eliminate the error condi- have invalid CBC, but is not used in the channel
tion, even though the underlying failure remains, program, the condition is normally not reported as
thereby reducing the exposure to additional an I/O-error condition. The condition may or may
reports. The locations, however, cannot be used, not be reported as a machine-check-interruption
since invalid CBC will result from attempts to store condition. Invalid CBC detected during accesses
other values at the location. For an intermittent to storage for other than CPU-related accesses
failure, however, validation is useful to restore a may be reported as system recovery with storage
valid CBC such that a subsequent partial store error uncorrected indicated, since the primary
into the checking block will be permitted. (A error indication is reported by some other means.
partial store is a store into a checking block
without replacing the entire checking block.) When the storage checking block consists of mul-
tiple bytes and contains invalid CBC, special
When a checking block consists of multiple bytes storage-validation procedures are generally neces-
in storage, or multiple bits in CPU registers, the sary to restore or place new information in the
invalid CBC can be made valid only when all of checking block. Validation of storage is provided
the bytes or bits are replaced simultaneously. with the manual load-clear and system-reset-clear
operations and is also provided as a program
For each type of field in the system, certain function. Programmed storage validation is done
instructions are defined to validate the field. a block at a time, by executing the privileged
Depending on the model, additional instructions instruction TEST BLOCK. Manual storage vali-
may also perform validation; or, in some models, a dation by clear reset validates all blocks which are
register is automatically validated as part of the available in the configuration.
machine-check-interruption sequence after the ori-
ginal contents of the register are placed in the A checking block with invalid CBC is never vali-
appropriate save area. dated unless the entire contents of the checking
block are replaced. An attempt to store into a
When an error occurs in a checking block, the ori- checking block having invalid CBC, without
ginal information contained in the checking block replacing the entire checking block, leaves the
should be considered lost even after validation. data in the checking block (including the check
Automatic register validation leaves the contents bits) unchanged. Even when an instruction or a
1. The contents of the registers are saved in General registers are validated by BRANCH AND
assigned storage locations. Any register LINK (BAL, BALR), BRANCH AND SAVE (BAS,
which is in error is identified by a corre- BASR), LOAD (LR), and LOAD ADDRESS.
sponding validity bit of zero in the machine- LOAD (L) and LOAD MULTIPLE validate if the
check-interruption code. Malfunctions operand is on a word boundary, and LOAD
detected during register saving do not result in HALFWORD validates if the operand is on a
additional machine-check-interruption condi- halfword boundary.
tions; instead, the correctness of all the infor-
mation stored is indicated by the appropriate Floating-point registers are validated by LOAD
setting of the validity bits. (LDR) and, if the operand is on a doubleword
boundary, by LOAD (LD).
2. On some models, registers with invalid CBC
are then validated, their actual contents being
The floating-point-control register is validated by
unpredictable. On other models, programmed
LOAD FLOATING POINT CONTROL REGISTER.
validation is required.
The prefix register and the TOD clock are not Access registers are validated by LOAD ACCESS
stored during a machine-check interruption, have MULTIPLE. Only the even-odd access-register
no corresponding validity bit, and are not vali- pairs that are included in the set of access regis-
dated. ters specified for LOAD ACCESS MULTIPLE are
validated. Thus, when a single access register is
On those models in which registers are not auto- specified, or when a pair of access registers
matically validated as part of the machine-check starting with an odd-numbered register is speci-
interruption, a register with invalid CBC will not fied, no register is validated.
cause a machine-check-interruption condition
unless the contents of the register are actually Control registers may be validated either singly or
used. In these models, each register may consist in groups by using the instruction LOAD
of one or more checking blocks, but multiple regis- CONTROL.
ters are not included in a single checking block.
When only a portion of a register is accessed, The TOD programmable register, CPU timer, clock
invalid CBC in the unused portion of the same comparator, and prefix register are validated by
register may cause a machine-check-interruption SET CLOCK PROGRAMMABLE REGISTER, SET
condition. For example, invalid CBC in the right CPU TIMER, SET CLOCK COMPARATOR, and
half of a floating-point register may cause a SET PREFIX, respectively.
machine-check-interruption condition if a LOAD
(LE) operation attempts to replace the left half, or The TOD clock is validated by a SET CLOCK
short form, of the register. instruction that sets the clock.
Programming Note: Depending on the register
Invalid CBC associated with the prefix register and the model, the contents of a register may be
cannot safely be reported by the machine-check validated by the machine-check interruption, or the
If a machine check which is to be reported as a Every reasonable attempt is made to limit the side
system-recovery condition is detected during the effects of any machine check and the associated
execution of the interruption procedure due to a interruption. Normally, interruptions, as well as
previous machine-check condition, the system- the progress of I/O operations, remain unaffected.
recovery condition may be combined with the The malfunction, however, may affect these activ-
other conditions, discarded, or held pending. ities, and, if the currently active PSW has bit 13
set to one, the machine-check interruption will
An exigent machine-check condition can cause a indicate the total extent of the damage caused,
machine-check interruption only when PSW bit 13 and not just the damage which originated the con-
is one. When a nullifying exigent condition causes dition.
a machine-check interruption, the interruption is
taken at a normal point of interruption. When a
terminating exigent condition causes a machine-
Point of Interruption
check interruption, the interruption terminates the
The point in the processing which is indicated by
execution of the current instruction and may elimi-
the interruption and used as a reference point by
nate the program and supervisor-call interruptions,
the machine to determine and indicate the validity
if any, that would have occurred if execution had
of the status stored is referred to as the point of
continued. Proper execution of the interruption
interruption.
sequence, including the storing of the old PSW
and other information, depends on the nature of Because of the checkpoint capability in models
the malfunction. When an exigent machine-check with CPU retry, the interruption resulting from an
condition occurs during the execution of a exigent machine-check-interruption condition may
machine function, such as a CPU-timer update, indicate a point in the CPU processing sequence
the sequence is not necessarily completed. which is logically prior to the error. Additionally,
the model may have some choice as to which
If, during the execution of an interruption due to
point in the CPU processing sequence the inter-
one exigent machine-check condition, another
ruption is indicated, and, in some cases, the
exigent machine check is detected, the CPU
status which can be indicated as valid depends on
enters the check-stop state. If an exigent machine
the point chosen.
check is detected during an interruption due to a
repressible machine-check condition, system Only certain points in the processing may be used
damage is reported. as a point of interruption. For repressible
machine-check interruptions, the point of inter-
When PSW bit 13 is zero, an exigent machine-
ruption must be after one unit of operation is com-
check condition causes the CPU to enter the
pleted and any associated program or supervisor-
check-stop state.
call interruption is taken, and before the next unit
of operation is begun.
Machine-check-interruption conditions are handled
in the same manner regardless of whether the
Exigent machine-check conditions for instruction
wait-state bit in the PSW is one or zero: a
sequences are those in which damage has or
machine-check condition causes an interruption if
would have occurred to the instruction stream.
the CPU is enabled for that condition.
Thus, the damage can normally be associated
with a point part way though an instruction, and
Machine checks which occur while the rate control
this point is called the point of damage. In some
is set to the instruction-step position are handled
cases, there may be one or more instructions sep-
in the same manner as when the control is set to
arating the point of damage and the point of inter-
the process position; that is, recovery mechanisms
ruption, and the processing associated with one or
are active, and machine-check interruptions occur
more instructions may be damaged. When the
when allowed. Machine checks occurring during a
point of interruption is a point prior to the point of
manual operation may be indicated to the oper-
damage due to a nullifiable exigent machine-check
ator, may generate a system-recovery condition,
condition, the point of interruption can be only at
┌─┬─┬─┬─────────┬─────┬─┬─┬─┬─┬─┬───────────────┬───────────────┐
│I│A│D│ │ │X│A│ │C│C│ │ │
│E│R│A│ │ │F│P││T│C│ │ │
└─┴─┴─┴─────────┴─────┴─┴─┴─┴─┴─┴───────────────┴───────────────┘
32 4 43 46 48 56 63
Bits Name
Note: All other bits of the MCIC are unassigned and stored as zeros.
Figure 11-4. Machine-Check Interruption-Code Format
This bit may be set to one regardless of whether Depending on the model, recognition of an
the vector-control bit, bit 14 of control register 0, is ancillary-report condition may not be provided, or
one or zero. it may not be provided for all system malfunctions.
When ancillary-report recognition is not provided,
Bit 13 is not meaningful when vector-facility failure bit 44 is set to zero.
is reported.
┌─────────────────────────────────────┬───────┬─────────────────────┐
│ Machine-Check Condition │ │ │
├────┬────────────────────────────────┤ Sub- │ Action when CPU │
│MCIC│ │ Class │ Disabled │
│Bit │ Subclass │ Mask │ for Subclass │
├────┼────────────────────────────────┼───────┼─────────────────────┤
│ │ System damage │ - │ Check stop │
│ 1 │ Instruction-processing damage │ - │ Check stop │
│ 2 │ System recovery │ RM │ Y │
│ 4 │ Timing-facility damage │ EM │ P │
│ 5 │ External damage │ EM │ P │
│ 6 │ Vector-facility failure │ - │ P │
│ 7 │ Degradation │ DM │ P │
│ 8 │ Warning │ WM │ P │
│ 9 │ Channel report pending │ CM │ P │
│ 1 │ Service-processor damage │ - │ P │
│ 11 │ Channel-subsystem damage │ - │ P │
├────┴────────────────────────────────┴───────┴─────────────────────┤
│Explanation: │
│ │
│ - The condition does not have a subclass mask. │
│ │
│ P Indication is held pending. │
│ │
│ Y Indication may be held pending or may be discarded. │
│ │
│ CM Channel-report-pending subclass mask (bit 3 of CR14). │
│ │
│ DM Degradation subclass mask (bit 5 of CR14). │
│ │
│ EM External-damage subclass mask (bit 6 of CR14). │
│ │
│ RM Recovery subclass mask (bit 4 of CR14). │
│ │
│ WM Warning subclass mask (bit 7 of CR14). │
└───────────────────────────────────────────────────────────────────┘
Figure 11-6. Machine-Check-Condition Masking
┌────────────────────────────────────┬────────────┬─────────────┐
│ │ Control │State of Bit │
│ │Register 14 │ on Initial │
│ Bit Description │Bit Position│ CPU Reset │
├────────────────────────────────────┼────────────┼─────────────┤
│Channel-report-pending subclass mask│ 3 │ │
│Recovery subclass mask │ 4 │ │
│Degradation subclass mask │ 5 │ │
│External-damage subclass mask │ 6 │ 1 │
│Warning subclass mask │ 7 │ │
└────────────────────────────────────┴────────────┴─────────────┘
Figure 11-7. Machine-Check Control-Register Bits
The restart key is effective when the CPU is in the The store-status key is effective only when the
operating or stopped state. The key is not effec- CPU is in the stopped state.
tive when the CPU is in the check-stop state. It
depends on the model whether the restart key is Operation Note: The store-status operation may
effective when any CPU in the configuration is in be used in conjunction with a standalone dump
the load state. program for the analysis of major program mal-
functions. For such an operation, the following
sequence would be called for:
There need not be more than one of each of the In a system capable of reconfiguration, there must
following keys and controls in a multiprocessing be a separate set of keys, controls, and indicators
in each configuration.
Device Number
I/O Addressing
Four different types of I/O addressing are provided Each subchannel that has an I/O device assigned
by the channel subsystem for the necessary to it also contains a parameter called the device
addressing of the various components: channel- number. The device number is a 16-bit value that
path identifiers, subchannel numbers, device is assigned as one of the parameters of the sub-
numbers, and, though not visible to programs, channel at the time the device is assigned to the
addresses dependent on the channel-path type. | subchannel. The device number uniquely identi-
| fies a device to the program.
Channel-Path Identifier The device number provides a means to identify a
device, independent of any limitations imposed by
| The channel-path identifier (CHPID) is a system-
the system model, the configuration, or channel-
| unique eight-bit value assigned to each installed
path protocols. The device number is used in
| channel path of the system. A CHPID is used to
communications concerning the device that take
| address a channel path. A CHPID is specified by
place between the system and the system oper-
| the second-operand address of RESET CHANNEL
ator. For example, the device number is entered
| PATH and used to designate the channel path
by the system operator to designate the input
| that is to be reset. The channel paths by which a
device to be used for initial program loading.
device is accessible are identified in the
subchannel-information block (SCHIB), each by its Programming Note: The device number is
associated CHPID, when STORE SUBCHANNEL assigned at device-installation time and may have
is executed. The CHPID can also be used in any value. Device numbers may be assigned
operator messages when it is necessary to identify installation-unique values in an installation with
a particular channel path. A system model may multiple system installations in order to avoid
provide as many as 256 channel paths. The ambiguity, particularly where a device can be
maximum number of channel paths and the switched between two or more systems.
assignment of CHPIDs to channel paths depends
on the system model. Additionally, the user must observe any
restrictions on device-number assignment that
may be required by the control program, support
Subchannel Number programs, or the particular control unit or I/O
device.
| A subchannel number is a system-unique 16-bit
| value used to address a subchannel. This value
| is unique within a channel subsystem. The sub- Device Identifier
channel is addressed by eight I/O instructions:
CANCEL SUBCHANNEL, CLEAR SUBCHANNEL, A device identifier is an address, not apparent to
HALT SUBCHANNEL, MODIFY SUBCHANNEL, the program, that is used by the channel sub-
RESUME SUBCHANNEL, START SUBCHANNEL, system to communicate with I/O devices. The
STORE SUBCHANNEL, and TEST SUB- type of device identifier used depends on the spe-
CHANNEL. All I/O functions relative to a specific cific channel-path type and the protocols provided.
I/O device are specified by the program by desig- Each subchannel contains one or more device
| nating a subchannel assigned to the I/O device. identifiers.
When the primary interruption condition is recog- The suspend-and-resume function provides the
nized, the channel subsystem attempts to notify program with control over the execution of a
the program, by means of an interruption request, channel program. The initiation of the suspend
that a subchannel contains information describing function is controlled by the setting of the
the conclusion of an I/O operation at the sub- | suspend-control bit in the ORB. The suspend
channel. The information identifies the last CCW | function is signaled to the channel subsystem
used and may provide its residual byte count, thus | during channel-program execution when the
describing the extent of main storage used. Both | suspend-control bit in the ORB is one and the
| All the I/O instructions described here are pro- | identification word. The format of the subsystem-
vided for the control of channel-subsystem oper- identification word is as follows:
ations. The I/O instructions are listed in
Figure 14-1 on page 14-3. All of the I/O ┌────────────────┬────────────────┐
│ │ Subchannel │
instructions are privileged instructions. │1│ Number │
└────────────────┴────────────────┘
Several I/O instructions result in the channel sub- 16 31
system being signaled to perform functions asyn-
chronous to the execution of the instructions. The Bit positions 16-31 contain an unsigned binary
description of each instruction of this type contains integer designating the subchannel to be used for
a section, “Associated Functions,” that summa- the function specified by the instruction. Bit posi-
rizes the asynchronous functions. tions 0-15 specify the binary number one.
┌────────────────┬────┬────────────┐
Serialization
│ Op Code │ B │ D │
└────────────────┴────┴────────────┘ The execution of any I/O instruction causes serial-
16 2 31 ization and checkpoint synchronization to occur.
For a definition of the serialization of CPU oper-
The use of the second-operand address and ations, see “CPU Serialization” on page 5-91.
general registers 1 and 2 (as implied operands)
depends on the I/O instruction. Figure 14-1 on Operand Access
page 14-3 defines which operands are used to
execute each I/O instruction. In addition, detailed During the execution of an I/O instruction, the
information regarding operand usage appears in order in which fields of the operand and fields of
the description of each I/O instruction. the subchannel, if applicable, are accessed is
unpredictable. It is also unpredictable whether
All I/O instructions that reference a subchannel fetch accesses are made to fields of an operand
use the contents of general register 1 as an or the subchannel, as applicable, when those
implied operand. For these I/O instructions, fields are not needed to complete the execution of
general register 1 contains the subsystem- the I/O instruction. (See “Relation between
Operand Accesses” on page 5-90.)
If conditions allow, the channel-path-reset facility | RESET CHANNEL PATH can encounter the
is signaled to asynchronously perform the | program exceptions described or listed below.
channel-path-reset function on the designated
channel path. The channel-path-reset function is | Bit positions 0-23 of general register 1 must
summarized below in the section “Associated | contain zeros; otherwise, an operand exception is
Functions” and is described in detail in “Channel- | recognized.
Path Reset” on page 17-13.
Resulting Condition Code:
Condition code 0 is set to indicate that the 0 Function initiated
channel-path-reset facility has been signaled. 1 --
2 Busy
Associated Functions 3 Not operational
Subsequent to the execution of RESET CHANNEL Program Exceptions:
PATH, the channel-path-reset facility asynchro-
nously performs the channel-path-reset function. Operand
Certain indications are reset at all subchannels Privileged operation
that have access to the designated channel path,
and the reset signal is issued on that channel Programming Notes:
path. Any I/O functions in progress at the devices 1. To eliminate the possibility of a data-integrity
are reset, but only for the channel path on which exposure for devices that have the capability
the reset signal is received. An I/O operation or of generating unsolicited device-end status,
chain of I/O operations taking place in the multi- I/O operations in progress with such devices
path mode may be able to continue to be exe- on the channel path for which RESET
cuted on other channel paths in the multipath CHANNEL PATH is to be executed must be
The channel subsystem is signaled to perform the Condition code 1 is set, and no other action is
resume function at the designated subchannel. taken, when the subchannel is status pending.
General register 1 contains a subsystem- Condition code 2 is set, and no other action is
identification word that designates the subchannel taken, when the resume function is not applicable.
at which the resume function is to be performed. The resume function is not applicable when the
subchannel (1) has any function other than the
The subchannel is made resume pending. start function alone specified, (2) has no function
specified, (3) is resume pending, or (4) does not
Logically prior to the setting of condition code 0 have suspend control specified for the start func-
and only if the subchannel is currently in the sus- tion in progress.
pended state, path-not-operational conditions at
the subchannel, if any, are cleared. Condition code 3 is set, and no other action is
taken, when the subchannel is not operational for
The channel subsystem is signaled to asynchro- the resume function. A subchannel is not opera-
nously perform the resume function. The resume tional for the resume function if the subchannel is
function is summarized below in the section not provided in the channel subsystem, has no
“Associated Functions” and is described in detail valid device number assigned to it, or is not
in “Start Function and Resume Function” on enabled.
page 15-18.
| RESUME SUBCHANNEL can encounter the
Condition code 0 is set to indicate that the actions | program exceptions described or listed below.
described above have been taken.
| Bits 0-15 of the SID must contain 0001 hex; other-
Associated Functions | wise, an operand exception is recognized.
┌─┬────────────────────────────┐ Operand
││ Address-Limit Value │ Privileged operation
└─┴────────────────────────────┘
1 31
SET CHANNEL MONITOR
Associated Functions SCHM [S]
┌────────────────┬────────────────┐
The value that is used by the address- │ 'B23C' │////////////////│
└────────────────┴────────────────┘
limit-checking facility when determining whether to 16 31
permit or prohibit a data access is called the
address-limit value. The initial address-limit value
is zero. The initial address-limit value is used by Each of the measurement-block-update mode and
the address-limit-checking facility until the facility device-connect-time-measurement mode of the
recognizes a signal, caused by the execution of channel subsystem is made either active or inac-
SET ADDRESS LIMIT, to use a specified address. tive, depending on the values of the
The recognition of this specified address as the measurement-mode-control bits in general register
new address-limit value occurs asynchronously 1. If the measurement-mode-control bit for
with respect to the execution of SET ADDRESS measurement-block update is one, the
LIMIT. measurement-block origin and measurement-block
key are passed to the channel subsystem.
If address-limit checking is specified for a sub-
channel, then whether the specified address is General register 1 has the following format:
used by the address-limit-checking facility, when ┌────┬──────────────────────────┬─┬─┐
determining whether to permit or prohibit a data │MBK ││M│D│
access, depends on whether SET ADDRESS └────┴──────────────────────────┴─┴─┘
LIMIT was executed before, during, or after the 4 3 31
execution of START SUBCHANNEL for that sub-
channel. If SET ADDRESS LIMIT is executed Measurement-Block Key (MBK): Bit positions
before START SUBCHANNEL, the specified 0-3 of general register 1 contain the
address is used by the address-limit-checking measurement-block key. When bit 30 is one,
facility. If SET ADDRESS LIMIT is executed MBK specifies the access key that is to be used
during or after the execution of START SUB- by the channel subsystem when it accesses the
CHANNEL, it is unpredictable whether the speci- | measurement-block area and, when the
fied address is used by the address-limit-checking | extended-I/O-measurement-block facility is
facility for that particular start function. For a | installed, to access format-1 measurement blocks.
description of the manner in which address-limit Otherwise, MBK is ignored.
checking is performed, see “Address-Limit
Checking” on page 17-20. Measurement-Block-Update Control (M): Bit 30
of general register 1 is the measurement-
Special Conditions mode-control bit that controls the measurement-
block-update mode. When bit 30 of general reg-
SET ADDRESS LIMIT can encounter the program ister 1 is one and conditions allow, the
exceptions described or listed below. measurement-block-update facility is signaled to
asynchronously make the measurement-
The address in general register 1 must be desig- block-update mode active. In addition, the
nated on a 64K byte boundary, and the leftmost measurement-block-origin (MBO) address in
bit of general register 1 must be zero; otherwise, general register 2 and the measurement-block key
an operand exception is recognized. (MBK) in general register 1 are passed to the
| measurement-block-update facility. Furthermore,
Condition Code: The code remains unchanged. | when bit 30 is one, bit 0 of general register 2 must
| be zero. The measurement-block origin is used to
| determine the location of format-0 measurement
| blocks; the address of format-1 measurement
For a more detailed description of the When START SUBCHANNEL is executed, the
measurement-block-update mode, the format and subchannel is status pending with only secondary
Logically prior to the setting of condition code 0, Condition code 1 is set, and no other action is
path-not-operational conditions at the subchannel, taken, when the subchannel is status pending
if any, are cleared. when START SUBCHANNEL is executed. On
some models, condition code 1 is not set when
The channel subsystem is signaled to asynchro- the subchannel is status pending with only sec-
nously perform the start function. The start func- ondary status; instead, the status-pending condi-
tion is summarized below in the section “Associ- tion is discarded.
ated Functions” and is described in detail in “Start
Function and Resume Function” on page 15-18. Condition code 2 is set, and no other action is
taken, when a start, halt, or clear function is cur-
Condition code 0 is set to indicate that the actions rently in progress at the subchannel (see “Func-
described above have been taken. tion Control (FC)” on page 16-12).
Special Conditions
TEST PENDING INTERRUPTION
Condition code 3 is set, and no other action is TPI D(B) [S]
taken, when the designated subchannel is not ┌────────────────┬────┬────────────┐
operational for STORE SUBCHANNEL. A sub- │ 'B236' │ B │ D │
└────────────────┴────┴────────────┘
channel is not operational for STORE SUB- 16 2 31
CHANNEL if the subchannel is not provided in the
channel subsystem.
The I/O-interruption code for a pending I/O inter-
| STORE SUBCHANNEL can encounter the ruption at a subchannel is stored at the location
| program exceptions described or listed below. designated by the second-operand address, and
the pending I/O-interruption request is cleared.
| Bits 0-15 of the SID must contain 0001 hex; other-
| wise, an operand exception is recognized. The second-operand address, when nonzero, is
the logical address of the location where the two-
The second operand must be designated on a word I/O-interruption code, consisting of words 0
word boundary; otherwise, a specification excep- and 1, is to be stored. The second-operand
tion is recognized. address must be designated on a word boundary;
otherwise, a specification exception is recognized.
Resulting Condition Code:
If the second-operand address is zero, the three-
0 SCHIB stored
word I/O-interruption code, consisting of words
1 --
0-2, is stored at real locations 184-195. In this
2 --
case, low-address protection and key-controlled
3 Not operational
protection do not apply.
Program Exceptions:
In the access-register mode when the second-
Access (store, operand 2) operand address is zero, it is unpredictable
Operand whether access-register translation occurs for
Privileged operation access register B. If the translation occurs, the
Specification
If a pending I/O-interruption request is accepted, The remaining bit positions are reserved and
the I/O-interruption code is stored, the pending stored as zeros.
I/O-interruption request is cleared, and condition
code 1 is set. The I/O-interruption code that is Special Conditions
stored is the same as would be stored if an I/O
interruption had occurred. However, PSWs are TEST PENDING INTERRUPTION can encounter
not swapped as when an I/O-interruption occurs. the program exceptions described or listed below.
The I/O-interruption code that is stored during the The second operand must be designated on a
execution of the instruction is defined as follows: word boundary; otherwise, a specification excep-
tion is recognized.
┌────────────────────────────────┐
Word │ Subsystem-Identification Word │ The execution of TEST PENDING INTER-
├────────────────────────────────┤
1│ Interruption Parameter │ RUPTION is suppressed on all addressing and
├────────────────────────────────┤ protection exceptions.
2│Interruption-Identification Word│
└────────────────────────────────┘
31
Resulting Condition Code:
0 Interruption code not stored
Subsystem-Identification Word (SID): See 1 Interruption code stored
“I/O-Instruction Formats” in Chapter 14. 2 --
3 --
Interruption Parameter: Word 1 contains a four-
byte parameter that was specified by the program Program Exceptions:
and passed to the subchannel in word 0 of the Access (store, operand 2, second-operand
ORB or the PMCW. When a device presents alert address nonzero only)
status and the interruption parameter was not pre- Privileged operation
viously passed to the subchannel by an execution Specification
of START SUBCHANNEL or MODIFY SUB-
CHANNEL, this field contains zeros. Programming Notes:
For example, if the POM bit for every channel Performing the clear function at a subchannel
path available for selection is one and the clears any currently existing allegiance condition in
device appears not operational on all corre- the subchannel for all channel paths.
sponding channel paths while the channel
subsystem is attempting to initiate a start func- Performing the reset-channel-path function clears
tion at the device, the channel subsystem all currently existing allegiances for that channel
makes the subchannel status pending, with path in all subchannels.
deferred condition code 3 and with the N bit
stored as one. The PNOM in the SCHIB indi- When a channel path becomes not physically
cates the channel path or channel paths that available, all internal indications of prior allegiance
appeared not operational, for which the corre- conditions are cleared in all subchannels having
access to the designated channel path.
A subchannel has an active allegiance established A dedicated allegiance can become an active alle-
for a channel path no later than when active com- giance. While a dedicated allegiance exists, an
munication has been initiated on that channel path active allegiance can only occur for the same
with an I/O device. The subchannel can have an channel path.
active allegiance to only one channel path at a
time. While the subchannel has an active alle- A currently existing dedicated allegiance is cleared
giance for a channel path, the channel subsystem at any subchannel having access to a channel
path when the channel path becomes not phys-
1. No channel path was chosen. (See “Clear- The Attempt to Issue the Clear Signal Is Suc-
Function Path Management” on page 15-14.) cessful: When the channel subsystem deter-
2. The chosen channel path is no longer avail- mines that the attempt to issue the clear signal
able for selection. was successful, the subchannel is no longer clear
pending and is set status pending, and the per-
3. A channel-path-terminal condition exists for formance of the clear function is complete. When
the chosen channel path. the subchannel becomes status pending, the I/O
4. The chosen channel path is currently being operation, if any, with the associated device has
used to actively communicate with a different been terminated.
device. Programming Note: Subsequent to the perform-
5. The device to be signaled is attached to a ance of the clear function, any nonzero status,
type-1 control unit, and the subchannel for except control unit end alone, that is presented to
another device attached to the same control the channel subsystem by the device is passed to
unit has an allegiance to the same channel the program as unsolicited alert status. Unsolic-
path, unless the allegiance is a working alle- ited status consisting of control unit end alone or
giance and primary status has been accepted zero status is not presented to the program.
by that subchannel.
6. The device to be signaled is attached to a
type-3 control unit, and the subchannel for
Halt Function
another device attached to the same control Subsequent to the execution of HALT SUB-
unit has a dedicated allegiance to the same CHANNEL, the channel subsystem performs the
channel path. halt function. Performance of the halt function
consists of (1) performing a path-management
If any of the conditions above exist, the sub-
operation, (2) issuing the halt signal to the associ-
channel remains clear pending and is set status
ated device, and (3) causing the subchannel to be
pending, and the performance of the clear function
made status pending, indicating the completion of
is complete.
the halt function.
For item 4, for item 5 under the specified condi- 4. The associated subchannel is status pending
tions, and for item 6, the channel subsystem with other than intermediate status alone.
chooses a channel path from a set of channel 5. The device to be signaled is attached to a
paths. In these cases, the channel subsystem type-1 control unit, and the subchannel for
Synchronization Control (Y): When the Prefetch Control (P): Bit 9 of word 1 specifies
FICON-channel facility is installed, bit 7 of word 1 whether or not unlimited prefetching of CCWs is
specifies whether synchronization control is allowed for the channel program. When bit 9 is
required for the channel program. When bit 7 is one, unlimited prefetching of CCWs is allowed.
zero and the prefetch-control bit, bit 9 of word 1, is (Unlimited prefetching of data and IDAWs associ-
one, synchronization control is specified. When ated with the current and prefetched CCWs is
bit 7 is one and bit 9 is one, synchronization always allowed.) It is model dependent whether
control is not specified. prefetching is actually performed.
When synchronization control is specified, the When bit 9 of word 0 is zero, no prefetching is
channel subsystem forces command synchroniza- allowed, except in the case of data chaining on
tion with the addressed I/O device whenever the output, where the prefetching of one CCW
current command in execution describes an input describing a data area is allowed. When bit 9 of
operation and the next CCW to be fetched word 0 is zero, the synchronization-control bit, bit
describes an output operation. When this condi- 7 of word 1, is ignored.
tion is recognized, the channel subsystem signals
Additional controls may limit the scope of pre-
a synchronization request to the I/O device when
fetching.
the input command is transferred. The transfer of
the output command is held pending at the sub-
Initial-Status-Interruption Control (I): Bit 10 of
channel until normal ending status, signaling the
word 1 specifies whether or not the channel sub-
completion of the performance of the input opera-
system must verify to the program that the device
tion by the I/O device, is received. Upon receipt
has accepted the first command associated with a
of the ending status, the channel subsystem
When bit 8 of word 1 is one, then bit 24 of word 1, Channel-Subsystem (CSS) Priority: When the
when zero, specifies the incorrect-length-indication channel-subsystem-I/O-priority facility is installed
mode. When the subchannel is in this mode and bit 31 (X) of word 1 of the ORB is one, byte 0
when an immediate operation occurs (that is, of word 3 contains an unsigned binary integer,
when a device signals the channel-end condition called the channel-subsystem-priority number, that
during initiation of the command) and the current is assigned to the designated subchannel and
CCW contains a nonzero value in bit positions used to order the selection of subchannels when
16-31, indication of an incorrect-length condition is either a start function or a resume function is to be
recognized. Command chaining is suppressed initiated for one or more subchannels that are start
unless the SLI flag in the CCW is one and the pending or resume pending.
chain-data flag is zero.
The specified channel-subsystem-priority number
When bit 8 of word 1 is zero, the value of bit 24 is can be any number in the range of 0 to 255. The
ignored by the channel subsystem, and the sub- numbers 0 and 255 designate the lowest and
channel is in the incorrect-length-suppression highest priorities, respectively.
mode.
Depending on the model and the configuration:
ORB-Extension Control (X): When the 1. Fewer than 256 priority levels may be pro-
ORB-extension facility is installed, bit 31 of word 1 vided. For such models, the ORB-specified
specifies whether the ORB is extended. When bit priority number may be ignored, and an alter-
31 of word 1 is zero, the ORB consists of words native priority number may be implicitly
0-2, and words 3-7 are ignored. When bit 31 of assigned to the subchannel when the sub-
word 1 is one, the ORB consists of words 0-7. channel becomes start pending.
Words 0 and 1 are described above. Words 2-7
are described below. 2. When bit 31 (X) of word 1 of the ORB is zero,
an implicit priority number is assigned to the
Reserved: Bits 25-30 of word 1 are reserved for subchannel.
future use and must be set to zeros. Bit 31 of See “Channel-Subsystem-I/O-Priority Facility” on
word 1 must be zero if the ORB-extension facility page 17-25 for details about how the priority
is not installed. Otherwise, an operand exception number is assigned for both of these cases.
or program-check condition is recognized.
For models that provide the ORB-extension facility
Channel-Program Address: Bits 1-31 of word 2 but do not provide the
specify the absolute address of the first CCW in channel-subsystem-I/O-priority facility, byte 0 of
main storage. Bit 0 of word 2 must be zero; oth- word 3 of the ORB must contain zeros; otherwise,
erwise, either an operand exception or a program- either an operand exception or a program-check
check condition is recognized. If format-0 CCWs condition is recognized.
are specified by bit 8 of word 1, then bits 1-7 of
word 2 also must be zeros; otherwise, a program- Control-Unit (CU) Priority: When the
check condition is recognized. channel-subsystem-I/O-priority facility is installed
and bit 31 (X) of word 1 of the ORB is one, byte 2
The three rightmost bits of the channel-program of word 3 contains an unsigned binary integer,
address must be zeros, designating the CCW on a called the control-unit-priority number, that speci-
┌───────────┬────────────────────────────────────────────────────────────────────────────┐
│ │Action at the Subchannel upon Exhaustion of Count or Receipt of Channel End │
│ ├───────────────────────────────────────────┬────────────────────────────────┤
│ │ Immediate Operation │ Non-immediate Operation │
│ ├─────────────────────┬─────────────────────┼─────────────────────┬──────────┤
│Flags in │ Incorrect-Length- │ Incorrect-Length- │ │ │
│Current CCW│ Suppression Mode │ Indication Mode │ Count Exhausted │Count Not │
├───┬───┬───┼──────────┬──────────┼──────────┬──────────┼──────────┬──────────┤Exhausted │
│ │ │ │ CCW │ CCW │ CCW │ CCW │ CE Not │ CE │ and CE │
│CD │CC │SLI│ Count/
= │ Count= │ Count/ = │ Count= │ Received │ Received │ Received │
├───┼───┼───┼──────────┼──────────┼──────────┼──────────┼──────────┼──────────┼──────────┤
│ │ │ │ End, NIL │ End, NIL │ End, IL │ End, NIL │ Stop, IL │ End, NIL │ End, IL │
│ │ │ 1 │ End, NIL │ End, NIL │ End, NIL │ End, NIL │ Stop,NIL │ End, NIL │ End, NIL │
│ │ 1 │ │ CC │ CC │ End, IL │ CC │ Stop, IL │ CC │ End, IL │
│ │ 1 │ 1 │ CC │ CC │ CC │ CC │ Stop, CC │ CC │ CC │
│ │ │ │ │ │ │ │ │ │ │
│ 1 │ - │ - │ End, NIL │ PC │ End, IL │ PC │ CD │ │ End, IL │
├───┴───┴───┴──────────┴──────────┴──────────┴──────────┴──────────┴──────────┴──────────┤
│Explanation: │
│ │
│ - The selected bit is ignored and may be either zero or one. │
│ │
│ These situations cannot validly occur. When data chaining is specified, the new │
│ CCW takes control of the operation after transferring the last byte of data │
│ designated by the current CCW, but before the next request for data or status │
│ transfer from the device. The new CCW (which cannot contain a count of zero │
│ unless a program-check condition is also recognized) is in control of the │
│ operation. │
│ │
│ The count field must contain a nonzero value when format- CCWs are specified; │
│ otherwise, the operation is terminated with a program-check condition. │
│ │
│ CC Command chaining is performed by the channel subsystem upon receipt of device │
│ end. │
│ │
│ CD The chain-data flag causes the channel subsystem to immediately fetch a new CCW │
│ for the same operation. The operation continues unless the CCW thus fetched has │
│ a count field of zero, in which case the operation is terminated with a │
│ program-check condition. │
│ │
│ CE Channel end from the device that indicates end of block. │
│ │
│ End Operation is terminated. │
│ │
│ IL Incorrect length is indicated with the subsequent interruption condition │
│ generated at the subchannel. │
│ │
│ NIL Incorrect length is not indicated with the subsequent interruption condition │
│ generated at the subchannel. │
│ │
│ PC These situations cannot validly occur. The channel subsystem recognizes a │
│ program-check condition when a CCW is fetched that has the chain-data flag set to│
│ one and a count field of zero. │
│ │
│ Stop Device is signaled to terminate data transfer, but subchannel remains │
│ subchannel active until channel end is received. │
└────────────────────────────────────────────────────────────────────────────────────────┘
Figure 15-6. Subchannel Chaining Action
Programming Note: Command chaining makes The value of the PCI flag can be one either in the
it possible for the program to initiate transfer of first CCW designated for the current start or
multiple blocks of data by issuing a single START resume function or in a CCW fetched during
SUBCHANNEL instruction. It also permits a sub- chaining. If the PCI flag is one in a CCW that has
channel to be set for execution of other com- become current, the subchannel becomes status
mands, such as positioning the disk-access mech- pending with intermediate status, and an
anism, and for data-transfer operations without I/O-interruption request is generated. The point at
interference by the program at the end of each which the subchannel becomes status pending
operation. Command chaining, in conjunction with depends on the progress of the current start or
the status-modifier condition, permits the channel resume function as follows:
subsystem to modify the normal sequence of
operations in response to signals provided by the 1. If the PCI flag is one in the first CCW associ-
I/O device. ated with a start function or a resume function,
the subchannel becomes status pending with
intermediate status only after the command
Skipping has been accepted.
Skipping causes the suppression of main-storage 2. If the PCI flag is one in a CCW that has
references during an I/O operation. It is defined become current while data chaining, the sub-
only for read, read-backward, sense-ID, and sense channel becomes status pending with interme-
operations, and is controlled by the skip flag, diate status after all data designated by the
which can be specified individually for each CCW. preceding CCW has been transferred.
When the skip flag is one, skipping occurs; when 3. If the PCI flag is one in a CCW that has
it is zero, normal operation takes place. The become current while command chaining, the
setting of the skip flag is ignored in all other oper- subchannel becomes status pending with
ations. intermediate status as that CCW becomes
current.
c. When an IRB indicates measurement Figure 15-7. Command Codes and Flags
check along with zero device status, zero
subchannel status, and status pending All flags have individual significance, except that
with primary, secondary, and alert status, the CC and SLI flags are ignored when the CD
it may indicate that the measurement flag is set to one, and, for output forward oper-
check was detected during an attempt to ations the SK flag is ignored. The presence of the
place the subchannel into the suspended SLI flag is ignored for immediate operations
state. involving format-0 CCWs, in which case the
incorrect-length indication is suppressed regard-
3. If the suspended interruption is suppressed,
less of the setting of the flag. The incorrect-length
the N condition and DCTI values applicable to
indication may be suppressed for immediate oper-
the preceding subchannel-active period are
ations when executing a format-1 CCW,
not made available to the program. The exe-
depending on the incorrect-length-suppression
cution of RESUME SUBCHANNEL when the
mode. The PCI flag is ignored during initial
subchannel is in the suspended state causes
program loading. All flags, except the PCI flag,
path-not-operational conditions and the N con-
are ignored when the S flag is one.
The channel subsystem provides two methods to Bits 29-31 (format 0) or bits 61-63 (format 1) of a
modify the normal sequential execution of the CCW that specifies the transfer-in-channel
CCWs in a channel program. One is the transfer- command must be zeros, designating a CCW on a
in-channel (TIC) command (described in “Transfer doubleword boundary. Furthermore, a CCW spec-
in Channel”), which can be used to loop back to a ifying transfer in channel may not be fetched from
previously executed CCW, or to connect discontig- a location designated by an immediately preceding
uous segments of the channel program. The transfer in channel. When either of these errors is
other method, which uses the status-modifier detected or when an invalid address is designated
device-status bit (described in the publication in the transfer-in-channel command, the program-
ESA/390 Common I/O-Device Commands, check condition is generated. When a CCW that
SA22-7204), allows conditions at the device to specifies the transfer-in-channel command desig-
cause the channel to bypass the next CCW in the nates a CCW at a location protected against
channel program. fetching, the protection-check condition is gener-
ated. Detection of these errors during data
chaining causes the operation at the I/O device to
be terminated and an interruption condition to be
generated, while during command chaining it
causes only an interruption condition to be gener-
ated.
When an I/O operation or sequence of I/O oper- Normally an I/O operation is being performed until
ations initiated by the execution of START SUB- the device signals primary interruption status.
CHANNEL is ended, the channel subsystem and Primary interruption status can be signaled during
the device generate status conditions. The gener- initiation of an I/O operation, or later. An I/O oper-
ation of these conditions can be brought to the ation can be terminated by the channel subsystem
attention of the program by means of an I/O inter- performing a clear or halt function when it detects
ruption or by means of the execution of the TEST an equipment malfunction, a program check, a
PENDING INTERRUPTION instruction. (During chaining check, a protection check, or an
certain abnormal situations, these conditions can incorrect-length condition, or by performing a
be brought to the attention of the program by clear, halt, or channel-path-reset function as a
means of a machine-check interruption. See result of the execution of CLEAR SUBCHANNEL,
“Channel-Subsystem Recovery” on page 17-21 for HALT SUBCHANNEL, or RESET CHANNEL
details.) The status conditions, as well as an PATH, respectively.
address and a count indicating the extent of the
operation sequence, are presented to the program I/O interruptions provide a means for the CPU to
in the form of a subchannel-status word (SCSW). change its state in response to conditions that
The SCSW is stored in an interruption-response occur at I/O devices or subchannels. These con-
block (IRB) during the execution of TEST SUB- ditions can be caused by the program, by the
CHANNEL. channel subsystem, or by an external event at the
device.
┌────────────────────┬───────────────────────────────────────────────────────────────┐
│Status-Control Field│ Status-Control-Bit Combinations │
├────────────────────┼───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┤
│Alert │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ │ │ │ │ │ │ │ │
│Primary │ │ 1 │ 1 │ 1 │ 1 │ │ │ │ 1 │ 1 │ 1 │ 1 │ │ │ │ │
│Secondary │ │ │ 1 │ 1 │ │ 1 │ 1 │ │ │ 1 │ 1 │ │ 1 │ 1 │ │ │
│Intermediate │ │ │ │ 1 │ 1 │ │ 1 │ 1 │ │ │ 1 │ 1 │ │ 1 │ 1 │ │
│Status pending │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │ 1 │
├────────────────────┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┼───┤
│Resulting interrup- │ E │ S │ S │ S │ S │ S │ - │ S │ S │ S │ S │ S │ S │ - │ S │ S │
│ tion condition │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
├────────────────────┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┤
│Explanation: │
│ │
│ - Combination does not occur. │
│ E Unsolicited or solicited interruption condition. │
│ S Solicited interruption condition. │
│ Indicates the bit stored as zero. │
│ 1 Indicates the bit stored as one. │
└────────────────────────────────────────────────────────────────────────────────────┘
Figure 16-1. Interruption Condition for Status-Control-Bit Combinations
Subchannel-Status Word
Interruption-Response Block
The subchannel-status word (SCSW) provides to
The interruption-response block (IRB) is the the program indications describing the status of a
operand of TEST SUBCHANNEL. The two right- subchannel and its associated device. If perform-
most bits of the IRB address are zeros, desig- ance of a halt, resume, or start function has
nating the IRB on a word boundary. The IRB con- occurred, the SCSW may describe the conditions
tains three major fields: the subchannel-status under which the operation was concluded.
word, the extended-status word, and the
| extended-control word. When the The SCSW is stored when TEST SUBCHANNEL
| extended-I/O-measurement-word mode is enabled is executed and the designated subchannel is
| at the subchannel, the IRB contains a fourth major operational. The SCSW is placed in words 0-2 of
| field, the extended-measurement word. The the IRB that is designated as the TEST SUB-
format of the IRB is as follows: CHANNEL operand. When STORE SUB-
CHANNEL is executed, the SCSW is stored in
words 7-9 of the subchannel-information block
(described in “Subchannel-Information Block” on
page 15-1). Figure 16-2 on page 16-7 shows the
format of the SCSW and summarizes its contents.
Bits Name
Word
-3 Subchannel key
4 Suspend control (S)
5 ESW format (L)
6-7 Deferred condition code (CC)
8 Format (F)
9 Prefetch (P)
1 Initial-status interruption control (I)
11 Address-limit-checking control (A)
12 Suppress-suspended interruption (U)
13 Zero condition code (Z)
14 Extended control (E)
15 Path not operational (N)
16 Reserved
17-19 Function control (FC)
(bit 17, start function; bit 18, halt function;
bit 19, clear function)
2-26 Activity control (AC)
(bit 2, resume pending; bit 21, start pending;
bit 22, halt pending; bit 23, clear pending;
bit 24, subchannel active; bit 25, device active;
bit 26, suspended)
27-31 Status control (SC)
(bit 27, alert status; bit 28, intermediate status;
bit 29, primary status; bit 3, secondary status;
bit 31, status pending)
Word 1
-31 CCW address
Word 2
-7 Device status
(bit , attention; bit 1, status modifier;
bit 2, control unit end; bit 3, busy;
bit 4, channel end; bit 5, device end;
bit 6, unit check; bit 7, unit exception)
8-15 Subchannel status
(bit 8, program-controlled interruption; bit 9, incorrect length;
bit 1, program check; bit 11, protection check;
bit 12, channel-data check; bit 13, channel-control check;
bit 14, interface-control check; bit 15, chaining check)
16-31 Count
Figure 16-2. SCSW Format
The contents of the subchannel-status word tion pertaining to the last operation, (2) informa-
(SCSW) depend on the state of the subchannel tion unrelated to the performance of an operation,
when the SCSW is stored. Depending on the (3) zeros, or (4) meaningless values. The fol-
state of the subchannel and the device, the spe- lowing descriptions indicate when an SCSW field
cific fields of the SCSW may contain (1) informa- contains meaningful information.
The subchannel is no longer suspended when any Alert Status (Bit 27): When one (and when the
of the following occurs: status-pending bit is also one), bit 27 indicates an
1. As part of the resume function following the alert interruption condition exists. In such a case,
execution of RESUME SUBCHANNEL when the subchannel is said to be status pending with
the subchannel becomes subchannel- alert status. An alert interruption condition is
and-device active or device active only, or the recognized when alert status is present at the sub-
first command is accepted for channel-end channel. Alert status may be subchannel status
and device-end initial status, with or without or device status. Alert status is status generated
status modifier, and the CCW does not specify by either the channel subsystem or the device
command chaining. under any of the following conditions:
┌──────────────────────────────────────────────┬──────────────────────────────────────┐
│ Subchannel State │ CCW Address │
├──────────────────────────────────────────────┼──────────────────────────────────────┤
│Start pending (UUUU/AIPSX) │ Unpredictable │
│ │ │
│Start pending and device active (UUUU/AIPSX)│ Unpredictable │
│ │ │
│Subchannel-and-device active (UUUU/AIPSX) │ Unpredictable │
│ │ │
│Device active only (UUUU/AIPSX) │ Unpredictable │
│ │ │
│Suspended (YYYYY/AIPSX) │ See note 1 │
│ │ │
│Status pending (11/AIPSX) because of │ Channel-program address + 8 │
│unsolicited alert status from the device while│ │
│the subchannel was start pending │ │
│ │ │
│Status pending (Y111/AIPSX) because the │ Channel-program address + 8 │
│device appeared not operational on all paths │ │
│ │ │
│Status pending (111/AIPSX) because of │ Channel-program address + 8 │
│solicited alert status from the device while │ │
│the subchannel was start pending and device │ │
│active │ │
│ │ │
│Status pending (1111/AIPSX) because of │ See note 2 │
│solicited alert status generated by the │ │
│channel subsystem while the subchannel was │ │
│start pending or start pending and device │ │
│active │ │
│ │ │
│Status pending (11/AIPSX) for the program-│ CCW + 8 of the CCW that contained the│
│controlled-interruption condition while the │ last recognized PCI, or 8 higher than│
│subchannel was subchannel-and-device active │ a CCW that has subsequently become │
│ │ current │
│ │ │
│Status pending (11/AIPSX) for the initial- │ CCW + 8 of the CCW causing the │
│status-interruption condition while the │ intermediate interruption condition, │
│subchannel was subchannel-and-device active │ or a CCW that has subsequently │
│ │ become current │
│ │ │
│Status pending (1Y1Y1/AIPSX); termination │ │
│occurred because of program check caused by │ │
│one of the following conditions: │ │
│ │ │
│ Bit 24 of word 1 of the ORB set to one; │ Channel-program address + 8 │
│ incorrect-length-indication-suppression │ │
│ facility not installed │ │
│ │ │
│ Unused bits in ORB not set to zeros │ Channel-program address + 8 │
│ │ │
│ Invalid CCW-address specification in │ Address of TIC + 8 │
│ transfer in channel (TIC) │ │
│ │ │
│ Invalid CCW-address specification in the │ Channel-program address + 8 │
│ channel-program address in the ORB │ │
└──────────────────────────────────────────────┴──────────────────────────────────────┘
Figure 16-4 (Part 1 of 4). CCW Address as Function of Subchannel State
Invalid CCW-Address Specification: The 2. The ORB specifies format-2 IDAWs, and the
channel-program address (CPA) or the transfer- contents of the data-address field in the CCW
in-channel command does not designate the CCW do not designate the first IDAW on a
on a doubleword boundary, or bit 0 of the CPA or doubleword boundary; that is, bits 29-31
bit 32 of a format-1 CCW specifying the transfer- (format-0 CCW) or 61-63 (format-1 CCW) are
in-channel command is not zero. not zeros.
Invalid CCW Address: The channel subsystem Invalid IDAW Address: The channel subsystem
has attempted to fetch a CCW from a main- has attempted to fetch an IDAW from a main-
storage location that is not available. An invalid storage location that is not available. An invalid
CCW address can occur because the program IDAW address can occur because the program
has designated an invalid address in the channel- has designated an invalid address in a CCW that
program-address field of the ORB or in the specifies indirect data addressing or because the
transfer-in-channel command or because, on channel subsystem, on sequentially fetching
chaining, the channel subsystem attempts to fetch IDAWs, attempts to fetch from an unavailable
a CCW from an unavailable location. A main- location. A main-storage location is unavailable
storage location is unavailable when any of the when any of the following conditions is detected:
following conditions is detected: 1. The absolute IDAW address does not corre-
spond to a physical location.
times when a channel path cannot distin- Figure 16-6. Relationship between Subchannel-Logout
guish between code 010 or 011. Data and SCSW Bits
110 Reserved.
Extended-Report Word
111 Reserved. The extended-report word (ERW) provides infor-
Figure 16-6 defines the relationship between indi- mation to the program describing specific condi-
cations provided as subchannel-logout data and tions that may exist at the device, subchannel, or
the appropriate SCSW bits. channel subsystem. The ERW is stored whenever
the extended-status word is stored. When the
extended-status-word-format bit, bit 5 of word 0 of
the SCSW, and the extended-control bit, bit 14 of
word 0 of the SCSW, are both zeros, the ERW
contains all zeros. When the extended-
status-word-format bit or the extended-control bit
or both are ones, the ERW has the following
format:
┌───┬─┬─┬─┬─┬─┬─┬─┬──────┬─────┬───────────┐
││A│P│T│F│S│C│R│ SCNT │││
└───┴─┴─┴─┴─┴─┴─┴─┴──────┴─────┴───────────┘
3 8 1 16 21 31
Channel Paths: I/O-system reset causes a reset The initial value of the path-operational mask is all
signal to be sent on all configured channel paths ones.
and causes the channel subsystem to be placed
in the reset and initialized state, as described in The device-number-valid bit is one for all subchan-
the previous sections. As a result of these nels having an assigned I/O device.
actions, all communication between the channel
subsystem and its attached control units and The initial value of the model-dependent area of
devices is terminated and the components reset, the subchannel-information block is described in
and all configured channel paths are made the System Library publication for the system
quiescent or are deconfigured. model.
Subchannels: I/O-system reset causes all oper- The initial value of the subchannel-status word
ations on all subchannels to be concluded. Status and extended-status word is all zeros.
information, all interruption conditions (but not
pending interruptions), dedicated-allegiance condi- The initialized state of the subchannel is the state
tions, and internal indications regarding prior con- specified by the initial values for the subchannel
ditions and operations in all subchannels are parameters described above. The description of
reset, and all valid subchannels are placed in the the subchannel parameters can be found in
initialized state. “Subchannel-Information Block” on page 15-1,
“Subchannel-Status Word” on page 16-6, and
In the initialized state, the subchannel parameters “Extended-Status Word” on page 16-32.
of all valid subchannels are set to their initial
values. The initial values of the following sub- Channel-Path-Reset Facility: I/O-system reset
channel parameters are zeros: causes the channel-path-reset facility to be reset.
A channel-path-reset function initiated by RESET
Interruption parameter CHANNEL PATH, either pending or in progress, is
I/O-interruption-subclass code (ISC)
All other bit combinations in the error- Installed Parameters Modified: One or more
recovery-code field are reserved. parameters of the specified facility have been
changed.
The specific meaning of each error-recovery code
depends on the particular reporting-source code Reporting-Source ID (RSID): Bit positions 16-31
that accompanies it in a CRW. The error-recovery contain the reporting-source ID, which may,
codes are defined as follows: depending upon the condition that caused the
channel report and the reporting-source code,
Event-Information Pending: Event information for either further identify the affected channel-
the identified facility is available for retrieval by the subsystem facility or provide additional information
program. This CRW does not indicate the state of describing the condition that caused the channel
the identified facility. report. The RSID field has the following format as
a function of the bit settings of the reporting-
Available: The identified facility is in the same source code.
state that the program would expect if the CRW
had not been generated. Reporting-Source
Code Reporting-Source ID
Initialized: The identified facility is in the same 4 5 6 7 Bits 16-31
state that existed immediately following the 0 0 1 0 0000 0000 0000 0000
I/O-system reset that was part of the most recent 0 0 1 1 xxxx xxxx xxxx xxxx
system IPL. 0 1 0 0 0000 0000 yyyy yyyy
1 0 0 1 0000 0000 yyyy yyyy
Temporary Error: The identified facility is not 1 0 1 1 0000 0000 0000 0000
operating in a normal manner or has recognized Note:
the occurrence of an abnormal event. It is
xxxx xxxx xxxx xxxx Subchannel number
expected that subsequent actions either will
yyyy yyyy Channel-path ID
restore the facility to normal operation or will
(CHPID)
record the appropriate information describing the
abnormal event.
The fraction of an HFP number is treated as a 4. The dividend in the DIVIDE instruction has a
hexadecimal number because it is considered to zero fraction.
be multiplied by a number which is a power of 16. 5. The operand of the HALVE, LOAD FP
The name, fraction, indicates that the radix point is INTEGER, or SQUARE ROOT instruction has
assumed to be immediately to the left of the left- a zero fraction.
most fraction digit.
6. One or both operands of a multiplication oper-
When an HFP operation would cause the result ation has a zero fraction.
exponent to exceed 63, the characteristic wraps Item 2, above, applies to normalized and unnor-
around from 127 to 0, and an malized instructions.
HFP-exponent-overflow condition exists. The
result characteristic is then too small by 128. When a program interruption for HFP exponent
When an operation would cause the exponent to underflow occurs, a true zero is not forced;
be less than −64, the characteristic wraps around instead, the fraction and sign remain correct, and
from 0 to 127, and an HFP-exponent-underflow the characteristic is too large by 128. When a
Figure 18-1. Normalization and Zero Handling for Instructions with HFP Results
program interruption for HFP significance occurs, The sign of a sum, difference, product, quotient,
the fraction remains zero, the sign is positive, and square root, the result of CONVERT FROM
the characteristic remains correct. FIXED, or the result of LOAD FP INTEGER with a
zero fraction is positive. The sign for a zero frac-
The R fields may designate the additional floating- The fixed-point second operand is converted to
point registers only when the basic-floating-point- the HFP format, and the normalized result is
extensions facility is installed; otherwise, a specifi- placed at the first-operand location.
cation exception is recognized.
A nonzero result is normalized. A zero result is
Resulting Condition Code: made a positive true zero.
0 Operands equal The second operand is a 32-bit signed binary
1 First operand low integer that is located in the general register des-
2 First operand high ignated by R.
3 --
The result is normalized and rounded toward zero
Program Exceptions: (truncated) before it is placed at the first-operand
Access (fetch, operand 2 of CE and CD only) location.
Data with DXC 1, AFP register
Operation (for CXR, if the HFP-extensions For CXFR, the R field must designate a valid
facility is not installed) floating-point-register pair; otherwise, a specifica-
Specification tion exception is recognized.
The R fields may designate the additional floating- The second operand is placed at the first-operand
point registers only when the basic-floating-point- location, and its sign and magnitude are tested to
extensions facility is installed; otherwise, a specifi- determine the setting of the condition code. The
cation exception is recognized. condition code is set the same as for a compar-
ison of the second operand with zero.
Condition Code: The code remains unchanged.
For short and long operands, the second operand
Program Exceptions: is placed unchanged in the first-operand location.
Data with DXC 1, AFP register
For extended operands, the high-order sign and
HFP exponent underflow
the entire fraction of the source are placed
Specification
unchanged in the result, and the low-order sign is
set equal to the high-order sign. If the extended-
Programming Notes:
operand fraction is nonzero, the high-order char-
1. An example of the use of the HALVE instruc- acteristic is placed unchanged in the result high-
tion (HDR) is given in Appendix A. order characteristic, and the low-order character-
2. With short and long operands, the halve oper- istic is set to 14 less than the high-order charac-
ation is identical to a divide operation with the teristic, modulo 128. If the extended-operand frac-
number 2 as divisor. Similarly, the result of tion is zero, the result is made a true zero with the
HDR is identical to that of MD or MDR with same sign as the source (the high-order and low-
one-half as a multiplier, and the result of HER order sign bits of the result are the same as the
is identical to that of MEE or MEER with one- high-order sign bit of the source).
half as a multiplier.
For LTXR, the R fields must designate valid
floating-point-register pairs; otherwise, a specifica-
tion exception is recognized.
For LNXR, the R fields must designate valid For extended operands, the low-order sign is set
floating-point-register pairs; otherwise, a specifica- equal to the high-order sign. If the extended-
tion exception is recognized. operand fraction is nonzero, the high-order char-
acteristic is placed unchanged in the result high-
The R fields may designate the additional floating- order characteristic, and the low-order character-
point registers only when the basic-floating-point- istic is set to 14 less than the high-order charac-
extensions facility is installed; otherwise, a specifi- teristic, modulo 128. If the extended-operand frac-
cation exception is recognized. tion is zero, the result is made a positive true zero
(the high-order and low-order sign bits of the
Resulting Condition Code: result are set to zero).
0 Result is zero
For LPXR, the R fields must designate valid
1 Result is less than zero
floating-point-register pairs; otherwise, a specifica-
2 --
tion exception is recognized.
3 --
The R fields may designate the additional floating-
Program Exceptions:
point registers only when the basic-floating-point-
Data with DXC 1, AFP register extensions facility is installed; otherwise, a specifi-
Operation (LNXR if the HFP-extensions facility cation exception is recognized.
is not installed)
Specification Resulting Condition Code:
0 Result is zero
LOAD POSITIVE 1 --
2 Result is greater than zero
Mnemonic1 R,R [RR] 3 --
┌────────┬────┬────┐
│Op Code │ R │ R │ Program Exceptions:
└────────┴────┴────┘
8 12 15 Data with DXC 1, AFP register
Operation (LPXR if the HFP-extensions facility
Mnemonic1 Op Code Operands is not installed)
LPER '3' Short HFP
LPDR '2' Long HFP Specification
If either or both operand fractions are zero, the | Mnemonic2 Op Code Operands
result is made a positive true zero, and no HFP | MAE 'ED2E' Short HFP
| MAD 'ED3E' Long HFP
exponent overflow or HFP exponent underflow
occurs.
| MULTIPLY AND SUBTRACT
The sign of the product is the exclusive or of the
operand signs, except that the sign is always plus | Mnemonic1 R,R,R [RRF]
when the result is made a true zero. | ┌────────────────┬────┬────┬────┬────┐
| │ Op Code │ R │////│ R │ R │
The R field for MXD, MXDR, and MXR, and the | └────────────────┴────┴────┴────┴────┘
| 16 2 24 28 31
R field for MXR must designate valid floating-
point-register pairs. Otherwise, a specification | Mnemonic1 Op Code Operands
exception is recognized. | MSER 'B32F' Short HFP
| MSDR 'B33F' Long HFP
The R fields may designate the additional floating- | Mnemonic2 R,R,D(X,B) [RXF]
point registers only when the basic-floating-point-
extensions facility is installed; otherwise, a specifi- | ┌────────┬────┬────┬────┬─/──┬────┬────┬────────┐
cation exception is recognized. | │Op Code │ R │ X │ B │ D │ R │////│Op Code │
| └────────┴────┴────┴────┴─/──┴────┴────┴────────┘
| 8 12 16 2 32 36 4 47
Condition Code: The code remains unchanged.
| Mnemonic2 Op Code Operands
Program Exceptions: | MSE 'ED2F' Short HFP
| MSD 'ED3F' Long HFP
Access (fetch, operand 2 of MDE, MEE, MD,
and MXD only) | The third operand is multiplied by the second
Data with DXC 1, AFP register | operand, and then the first operand is added to or
HFP exponent overflow | subtracted from the product. The sum or differ-
HFP exponent underflow | ence is placed at the first-operand location. The
Operation (MEE and MEER if the | MULTIPLY AND ADD and MULTIPLY AND SUB-
HFP-extensions facility is not installed) | TRACT operations may be summarized as:
Specification
The normalized and rounded square root of the Condition Code: The code remains unchanged.
second operand is placed at the first-operand
location. Program Exceptions:
When the fraction of the second operand is zero, Access (fetch, operand 2 of SQE and SQD
the sign and characteristic of the second operand only)
are ignored, and the operation is completed by Data with DXC 1, AFP register
placing a positive true zero at the first-operand HFP square root
location. Operation (SQER and SQDR if the square-
root facility is not installed; SQE, SQD, and
If the second operand is less than zero, an SQXR if the HFP-extensions facility is not
HFP-square-root exception is recognized. installed)
Specification
If the second operand is normalized and greater
than zero, the characteristic, fraction, and sign of Programming Notes:
the result are produced as follows: 1. The use of the SQUARE ROOT instruction
The result characteristic is one-half of the sum with short operands (SQER) is illustrated by
of the operand characteristic and either 64, if the examples in the following table:
the operand characteristic is even, or 65, if it ┌─────────┬───────┬─────────┬─────────┐
is odd. │ Operand │Decimal│ Result │ Decimal │
│ (hex) │ Value │ (hex) │ Value │
If the operand characteristic is odd, the ├─────────┼───────┼─────────┼─────────┤
operand fraction is shifted right one digit posi- │42 19│25. │41 5│5. │
tion, the rightmost digit entering the guard-digit │4 4│ .25 │4 8│.5 │
position. │4 8│ .5 │4 B54F3│.771...│
│41 8│ 8. │41 2D413D│2.8284...│
An intermediate-result fraction is produced by └─────────┴───────┴─────────┴─────────┘
computing without rounding the square root of 2. The result fraction is correctly normalized
the operand fraction, after any right shift as without any further left or right shifts of the
described. The intermediate-result fraction intermediate-result fraction and without any
consists of the 29 most significant further exponent adjustment. Rounding
hexadecimal digits of the square-root result in cannot cause a carry out of the leftmost digit.
the extended format, 15 in the long format, or
seven in the short format, where all three 3. Although a characteristic greater than 127 or
formats include a guard digit on the right. less than zero may temporarily be generated
during the operation, the result characteristic
A one is added to the leftmost bit of the guard is always within the representable range, and
digit of the intermediate result, any carry is no HFP exponent overflow or underflow
propagated to the left, and the guard digit is occurs.
dropped to produce the result fraction.
Specifically, the smallest nonzero operand in
The result sign is made plus. the long format consists of a one bit, preceded
If the second operand is unnormalized and greater on the left by 63 zeros. This operand is an
than zero, the operand is first normalized. The unnormalized number with a value of 16-78,
operation then proceeds as for normalized oper- and its square root is 16-39. The normalized
ands. representation of this result has a character-
istic of 26 (decimal). Similarly, the square root
When a number or NaN in the BFP long format is Values of Nonzero Numbers
loaded into a floating-point register, it occupies the The values of nonzero numbers in the various
entire register. formats are shown in Figure 19-8.
format but does not include details. The BFP All finite nonzero numbers within the normalized
extended format meets these requirements, far range permitted by a given format have a unique
exceeding them in the area of precision. BFP representation. There are no unnormalized
numbers, which numbers might allow multiple
Classes of BFP Data representations for the same values, and there are
no unnormalized arithmetic operations. Tiny
There are six classes of BFP data, which include numbers of a magnitude below the minimum nor-
numeric and related nonnumeric entities. Each malized number in a given format are represented
data item consists of a sign, an exponent, and a as denormalized numbers, but those values are
significand. The exponent is biased such that all also represented uniquely. The implied unit bit of
biased exponents are nonnegative unsigned a normalized number is one, and that of a a
numbers and the minimum biased exponent is denormalized number or a zero is zero.
zero. The significand consists of an explicit frac-
The six classes of BFP data are summarized in
tion and an implicit unit bit to the left of the binary
Figure 19-9 on page 19-6.
point. The sign bit is zero for plus and one for
minus.
Programming Notes:
BFP Comparison
1. Rounding a finite result toward zero cannot Comparisons are always exact and cannot cause
give infinity. an IEEE-inexact condition.
2. Rounding a result toward +∞ can give +∞ but
Comparison ignores the sign of zero, that is, +0
not −∞.
equals −0.
3. Rounding a result toward −∞ can give −∞ but
not +∞. Infinities with like sign compare equal, that is, +∞
equals +∞, and −∞ equals −∞.
Normalization and A NaN compares as unordered with any other
Denormalization operand, whether a finite number, an infinity, or
another NaN, including itself.
Every arithmetic or conversion operation is consid-
ered to produce an intermediate result as if the Two sets of instructions are provided: COMPARE
precision and exponent range were unbounded, and COMPARE AND SIGNAL. In the absence of
unless the result is defined to be zero, infinity, or QNaNs, these instructions work the same. These
NaN. The final result is produced by normalizing instructions work differently only when both of the
and then rounding this intermediate result. When following are true:
there is exponent underflow, that is, the biased
Neither operand of the instruction is an SNaN
exponent of the normalized intermediate result is
less than one, then the intermediate result is At least one operand of the instruction is a
denormalized to produce the final result, as QNaN
described below.
In this case, COMPARE simply sets condition
code 3, but COMPARE AND SIGNAL recognizes
Denormalization consists in shifting the
the IEEE-invalid-operation condition. If any
significand, including the units bit, to the right
For arithmetic operations with finite or infinite If the integer quotient has a value that lies outside
numeric results, condition codes 0, 1, and 2 are the range of the operand format, a wrapped result
set to indicate that the result is a zero of either is provided.
sign, less than zero, or greater than zero, respec-
tively. The condition-code setting depends only In certain cases where the number of bits in the
on an inspection of the rounded result. For com- integer quotient exceeds or may exceed the
parison operations, condition codes 0, 1, and 2 maximum number of bits provided in the precision
indicate equal, low, or high, respectively. These of the operand format, partial results are
settings are the same as for the HFP instructions. produced, and more than one execution of the
instruction is required to obtain the final result; this
Condition code 3 can also be set. After an arith- may be done with a simple instruction loop.
metic operation, condition code 3 indicates a NaN
result of either sign. After a comparison, it indi- Partial results are produced when the precise quo-
cates that a NaN was involved in the comparison tient is not an integer and the two integers closest
(the unordered condition). See Figure 19-10. to this precise quotient cannot both be repres-
ented exactly in the precision of the quotient. This
situation exists when the precise quotient is
CC Arithmetic Comparison greater than 2P, where P is the precision of the
operand format, and the remainder is not zero.
0 ±0 Equal
1 <0 Low
When the remainder is zero, then the quotient is
2 >0 High an integer, and the number of bits required to rep-
3 ±NaN Unordered resent the quotient is never more than the preci-
sion of the target.
Figure 19-10. Condition Codes Programming Note: The remainder result of
DIVIDE TO INTEGER with a specified quotient
rounding mode of round to nearest corresponds to
the Remainder function in the IEEE standard.
This function is similar to the MOD function found
in some languages and to the mathematical
If the instruction performs a comparison and no sign that is the exclusive or of the dividend and
program interruption occurs, the comparison result divisor signs.
is unordered.
If the IEEE-division-by-zero mask bit in the FPC
If the instruction is one that produces a BFP register is one, the operation is suppressed, and
result, if no program interruption occurs, and if the condition is reported as a program interruption
none of the operands is a NaN, the result is the for a data exception with DXC 40 hex.
default QNaN. If one of the operands is a NaN,
that operand becomes the result unchanged, IEEE Overflow
except that an SNaN is first converted to the cor- An IEEE-overflow condition is recognized when
responding QNaN by setting the leftmost fraction the exponent of the rounded result of a BFP oper-
bit to one. ation would be greater than the maximum expo-
nent of the target format if the exponent range
If the IEEE-invalid-operation mask bit in the FPC were unbounded.
register is one, the operation is suppressed, and
the condition is reported as a program interruption If the IEEE-overflow mask bit in the FPC register
for a data exception with DXC 80 hex. is zero, the IEEE-overflow flag bit in the FPC reg-
ister is set to one. The result of the operation
IEEE Division-By-Zero depends on the sign of the intermediate result and
An IEEE-division-by-zero condition is recognized on the current rounding mode:
when in BFP division the divisor is zero and the
1. When rounding to nearest, the result is infinity
dividend is a finite nonzero number.
with the sign of the intermediate result.
If the IEEE-division-by-zero mask bit in the FPC 2. When rounding toward 0, the result is the
register is zero, the IEEE-division-by-zero flag bit largest finite number of the format, with the
in the FPC register is set to one. The operation is sign of the intermediate result.
completed using as the result an infinity with a
Figure 19-17 (Part 1 of 2). Action for R(v): Rounding and Range Function
Figure 19-17 (Part 2 of 2). Action for R(v): Rounding and Range Function
Data with DXC 2, BFP instruction Programming Note: The IEEE standard makes
Operation (if the BFP facility is not installed) it optional whether operations such as LOAD AND
TEST signal invalid operation when the operand is
an SNaN. TEST DATA CLASS may be used to
LOAD AND TEST test an operand if signaling is not desired.
Mnemonic R,R [RRE]
┌────────────────┬────────┬────┬────┐
LOAD COMPLEMENT
│ Op Code │////////│ R │ R │
└────────────────┴────────┴────┴────┘ Mnemonic R,R [RRE]
16 24 28 31
┌────────────────┬────────┬────┬────┐
Mnemonic Op Code Operands │ Op Code │////////│ R │ R │
LTEBR 'B32' Short BFP └────────────────┴────────┴────┴────┘
LTDBR 'B312' Long BFP 16 24 28 31
LTXBR 'B342' Extended BFP
Mnemonic Op Code Operands
LCEBR 'B33' Short BFP
The second operand is placed at the first-operand LCDBR 'B313' Long BFP
location, and its sign and magnitude are tested to LCXBR 'B343' Extended BFP
determine the setting of the condition code. The
condition code is set the same as for a compar- The second operand is placed at the first-operand
ison of the second operand with zero. location with the sign bit inverted.
The second operand is placed unchanged at the The sign bit is inverted even if the operand is
first-operand location. If the second operand is an zero. The rest of the second operand is placed
SNaN, an IEEE-invalid-operation condition is unchanged at the first-operand location. The sign
recognized; if there is no interruption, the result is is inverted for any operand, including a QNaN or
the corresponding QNaN. SNaN, without causing an arithmetic exception.
See Figure 19-21 on page 19-26 for a detailed For LCXBR, the R fields must designate valid
description of the results of this instruction. floating-point-register pairs; otherwise, a specifica-
tion exception is recognized.
For LTXBR, the R fields must designate valid
floating-point-register pairs; otherwise, a specifica- Resulting Condition Code:
tion exception is recognized. 0 Result is zero
1 Result is less than zero
Resulting Condition Code: 2 Result is greater than zero
0 Result is zero 3 Result is a NaN
1 Result is less than zero
2 Result is greater than zero IEEE Exception Conditions: None.
3 Result is a NaN
Program Exceptions:
IEEE Exception Conditions: Data with DXC 2, BFP instruction
Invalid operation Operation (if the BFP facility is not installed)
Specification (LCXBR only)
Programming Note: The IEEE standard makes
it optional whether operations such as LOAD
COMPLEMENT signal invalid operation when the
operand is an SNaN. LOAD AND TEST may be
The second operand is rounded to an integer The M field must designate a valid modifier, and,
value in the same floating-point format, and the for FIXBR, the R fields must designate valid
result is placed at the first-operand location. floating-point-register pairs. Otherwise, a specifi-
cation exception is recognized.
The second operand, if numeric, is rounded to an
integer value as specified by the modifier in the Condition Code: The code remains unchanged.
M field:
IEEE Exception Conditions:
M Rounding Method
Invalid operation
0 According to current rounding mode
Inexact
1 Biased round to nearest
4 Round to nearest Program Exceptions:
5 Round toward 0
6 Round toward +∞ Data with DXC 2, BFP instruction
7 Round toward −∞ Data with DXC for IEEE exception condition
Operation (if the BFP facility is not installed)
A modifier other than 0, 1, or 4-7 is invalid. Specification
IEEE Exception Conditions: None. See Figure 19-21 on page 19-26 for a detailed
description of the results of this instruction.
Program Exceptions:
Data with DXC 2, BFP instruction For LDXBR and LEXBR, the R and R fields
Operation (if the BFP facility is not installed) must designate valid floating-point-register pairs;
Specification (LPXBR only) otherwise, a specification exception is recognized.
Programming Note: The IEEE standard makes Condition Code: The code remains unchanged.
it optional whether operations such as LOAD
Programming Notes:
The product of the second operand (the multiplier)
1. The sign of the rounded result is the same as and the first operand (the multiplicand) is placed
the sign of the operand, even when the result at the first-operand location.
is zero.
The two BFP operands, if numeric and finite, are
2. The R field for LDXBR and LEXBR must
multiplied, forming an intermediate product. For
designate a valid floating-point-register pair
MDEB, MDEBR, MXDB, and MXDBR, the inter-
since in certain cases the result is in the
mediate product is converted to the longer target
extended format. In normal operation for
format; the result cannot overflow or underflow
LDXBR and LEXBR, the result format is long
and is exact. For MDB, MDBR, MEEB, MEEBR,
or short, respectively, and this result replaces
and MXBR, the result is rounded to the operand
the leftmost 32 bits or 64 bits of the target-
format according to the current rounding mode.
register pair. However, when an IEEE over-
For MEEB and MEEBR, the result, as for all short-
flow or an IEEE underflow occurs and the cor-
format results, replaces the leftmost 32 bits of the
responding mask bit is one, the operation is
target register, and the rightmost 32 bit positions
completed by placing a result in the extended
of the target register remain unchanged.
format at the target location. Thus, the
program must take into account the fact that The sign of the product, if the product is numeric,
these instructions sometimes update both reg- is the exclusive or of the operand signs. This
isters of the pair. includes the sign of a zero or infinite product.
Mnemonic1 R,R,R [RRF] When the operands are numeric and finite, the
third and second BFP operands are multiplied,
┌────────────────┬────┬────┬────┬────┐ forming an intermediate product, and the first
│ Op Code │ R │////│ R │ R │
└────────────────┴────┴────┴────┴────┘ operand is then added (or subtracted) algebra-
16 2 24 28 31 ically to (or from) the intermediate product, forming
an intermediate sum. The intermediate sum, if
Mnemonic1 Op Code Operands
MAEBR 'B3E' Short BFP nonzero, is normalized and rounded to the
MADBR 'B31E' Long BFP operand format according to the current rounding
mode and then placed at the first-operand
Mnemonic2 R,R,D(X,B) [RXF] location. The exponent and fraction of the inter-
┌────────┬────┬────┬────┬─/──┬────┬────┬────────┐ mediate product are maintained exactly; rounding
│Op Code │ R │ X │ B │ D │ R │////│Op Code │ and range checking occur only on the intermediate
└────────┴────┴────┴────┴─/──┴────┴────┴────────┘ sum.
8 12 16 2 32 36 4 47
Mnemonic2 Op Code Operands See Figure 19-27 on page 19-43 for a detailed
MAEB 'EDE' Short BFP description of the results of MULTIPLY AND ADD.
MADB 'ED1E' Long BFP
The results of MULTIPLY AND SUBTRACT are
the same, except that the first operand partic-
MULTIPLY AND SUBTRACT ipates in the operation with its sign bit inverted.
Data with DXC 2, BFP instruction Access (fetch, operand 2 of SQEB and SQDB
Operation (if the BFP facility is not installed) only)
Data with DXC 2, BFP instruction
Data with DXC for IEEE exception condition
SQUARE ROOT Operation (if the BFP facility is not installed)
Specification (SQXBR only)
Mnemonic1 R,R [RRE]
┌────────────────┬────────┬────┬────┐
│ Op Code │////////│ R │ R │ STORE FPC
└────────────────┴────────┴────┴────┘
16 24 28 31 STFPC D(B) [S]
┌───────────────────┬────┬──────────────┐
Mnemonic1 Op Code Operands │ 'B29C' │ B │ D │
SQEBR 'B314' Short BFP └───────────────────┴────┴──────────────┘
SQDBR 'B315' Long BFP 16 2 31
SQXBR 'B316' Extended BFP
The contents of the FPC (floating-point-control)
Mnemonic2 R,D(X,B) [RXE] register are placed in storage at the second-
┌────────┬────┬────┬────┬─/──┬────────┬────────┐ operand location.
│Op Code │ R │ X │ B │ D │////////│Op Code │
└────────┴────┴────┴────┴─/──┴────────┴────────┘ The operand is four bytes in length. All 32 bits of
8 12 16 2 32 4 47
the FPC register are stored.
Mnemonic2 Op Code Operands
SQEB 'ED14' Short BFP Condition Code: The code remains unchanged.
SQDB 'ED15' Long BFP
IEEE Exception Conditions: None.
The square root of the second operand is placed
at the first-operand location. Program Exceptions:
┌──────────────────────────────────────────────────────────────────────┐
│ 2-1 = 2 147 483 647 = 111 1111 1111 1111 1111 1111 1111 1111 │
│ 2 = 65 536 = 1 │
│ 2 = 1 = 1 │
│ = = │
│ -2 = -1 = 1 111 1111 1111 1111 1111 1111 1111 1111 │
│ -2 = -2 = 1 111 1111 1111 1111 1111 1111 1111 111 │
│ -2 = -65 536 = 1 111 1111 1111 1111 │
│ -2+1 = -2 147 483 647 = 1 1 │
│ -2 = -2 147 483 648 = 1 │
└──────────────────────────────────────────────────────────────────────┘
Figure A-1. 32-Bit Signed Binary Integers
┌─────────────────────────────────────────────────────────────────────┐
│ 2-1 = 4 294 967 295 = 1111 1111 1111 1111 1111 1111 1111 1111 │
│ 2 = 2 147 483 648 = 1 │
│ 2-1 = 2 147 483 647 = 111 1111 1111 1111 1111 1111 1111 1111 │
│ 2 = 65 536 = 1 │
│ 2 = 1 = 1 │
│ = = │
└─────────────────────────────────────────────────────────────────────┘
Figure A-2. 32-Bit Unsigned Binary Integers
┌──────────────────────────────────────────────────────────────────────────┐
│ 1. = +1/16x16 = 1 1 1 │
│ .5 = +8/16x16 = 1 1 │
│ 1/64 = +4/16x16- = 11 1111 1 │
│ . = + x16- = │
│ -15. = -15/16x16 = 1 1 1 1111 │
│ 5.4x1-$ +1/16x16- = 1 │
│ 7.2x1$ (1-16-)x16 = 111 1111 1111 1111 1111 1111 1111 1111 │
└──────────────────────────────────────────────────────────────────────────┘
Figure A-3. Normalized Short Hexadecimal-Floating-Point Numbers
3. The decimal fraction is converted to its The instruction-use examples are written princi-
hexadecimal representation. pally for assembler-language programmers, to be
.250 = .4@ used in conjunction with the appropriate
assembler-language publications.
4. The integral and fractional parts are combined
and expressed as a fraction times a power of Most examples present one particular instruction,
16 (exponent). both as it is written in an assembler-language
3B.4@ = .3B4@ x 16 statement and as it appears when assembled in
storage (machine format).
5. The characteristic is developed from the expo-
nent and converted to binary.
base + exponent = characteristic
Machine Format
64 + 2 = 66 = 11
All machine-format values are given in
6. The fraction is converted to binary and hexadecimal notation unless otherwise specified.
grouped hexadecimally. Storage addresses are also given in hexadecimal.
.3B4@ = .11 111 1 Hexadecimal operands are shown converted into
binary, decimal, or both if such conversion helps
7. The characteristic and the fraction are stored to clarify the example for the reader.
in the short format. The sign position contains
the sign of the fraction.
1. 4 1 D6 6 99 99 46 8A CE Machine Format
2. 4 1 D6 6 99 99 82 46 8A CE Op Code M X B D
3. 4 1 D6 86 99 99 46 8A CE ┌────────┬────┬────┬────┬────┐
4. 4 1 D6 86 99 99 82 46 8A CE │ 47 │ C │ B │ A │ 5│
5. 84 1 D6 6 99 99 46 8A CE └────────┴────┴────┴────┴────┘
6. 84 1 D6 6 99 99 82 46 8A CE
7. 84 1 D6 86 99 99 46 8A CE
8. 84 1 D6 86 99 99 82 46 8A CE Assembler Format
Op Code M,D(X,B)
───────────────────────
The results in the eight cases are as follows: BC 12,X'5'(11,1)
Assembler Format
sets condition code 1, indicating that the contents Op Code R,R
of field 1 are lower in value than the contents of ──────────────
field 2. CLR 4,7
Because the collating sequence of the EBCDIC sets condition code 1. Condition code 1 indicates
code is determined simply by a logical comparison that the first operand is lower than the second.
of the bits in the code, the CLC instruction can be
used to collate EBCDIC-coded fields. For If, instead, the signed-binary comparison instruc-
example, in EBCDIC, the above two data fields tion COMPARE (CR) had been executed, the con-
are: tents of register 4 would have been interpreted as
Field 1: JOHNSON,A.B. +1 and the contents of register 7 as -1. Thus, the
Field 2: JOHNSON,A.C. first operand would have been higher, so that con-
dition code 2 would have been set.
Condition code 1 indicates that JOHNSON,A.B.
should precede JOHNSON,A.C. for the fields to
be in alphabetic sequence. COMPARE LOGICAL
CHARACTERS UNDER MASK
CLI Example (CLM)
The COMPARE LOGICAL (CLI) instruction com-
pares a byte from the instruction stream with a The COMPARE LOGICAL CHARACTERS
byte from storage. For example, assume that: UNDER MASK (CLM) instruction provides a
Register 10 contains 00 00 17 00. means of comparing bytes selected from a
general register to a contiguous field of bytes in
Storage location 1703 contains 7E. storage. The M field of the CLM instruction is a
Execution of the instruction:
If this CLCL instruction is interrupted after 60 When condition code 1 or 2 is set, the addresses
bytes have compared equal, the operand lengths of the last bytes processed in the first and second
in registers 5 and 9 will have been decremented operands are placed in general registers R and
to 40 and 72, respectively. The operand R, respectively. These are the addresses of
addresses in registers 4 and 8 will have been unequal bytes in the two operands, or they are the
Following are examples of first and second oper- CC: ; (R): 1; (R): 2
ands beginning at decimal locations 1000 and
2000, respectively. The addresses in general reg-
CONVERT TO BINARY (CVB)
isters R and R are 1000 and 2000, respectively.
The ending character in general register 0 is 00 The CONVERT TO BINARY instruction converts
hex (as in the C programming language). The an eight-byte, packed-decimal number into a
values of the operand bytes are shown in hex, signed binary integer and loads the result into a
and the resulting condition code and final contents general register. After the conversion operation is
of general registers R and R are shown. completed, the number is in the proper form for
Example 1 use as an operand in signed binary arithmetic.
1 2 For example, assume:
C1 C2 C3 C1 C2 C3
Storage locations 7608-760F contain a
CC: ; (R): 1; (R): 2 decimal number in the packed format: 00 00
Example 2 00 00 00 25 59 4C (+25,594).
1 2
4 4 4 C1 4 4 4 C2 The contents of register 7 are not significant.
Register 13 contains 00 00 76 00.
CC: 1; (R): 13; (R): 23
The format of the conversion instruction is:
Example 3
1 2
4 4 4 C2 4 4 4 C1 Machine Format
Op Code R X B D
CC: 2; (R): 13; (R): 23 ┌────────┬────┬────┬────┬────┐
│ 4F │ 7 │ │ D │ 8│
Example 4 └────────┴────┴────┴────┴────┘
1 2
C1 C2 C3 C1 C2 C3 C4
Assembler Format
CC: 1; (R): 13; (R): 23 Op Code R,D(X,B)
─────────────────────
Example 5 CVB 7,8(,13)
1 2
C1 C2 C3 C4 C1 C2 C3
After the instruction is executed, register 7 con-
CC: 2; (R): 13; (R): 23 tains 00 00 63 FA.
Example 6
Assuming that the CPU-determined number of
bytes compared is 256: CONVERT TO DECIMAL (CVD)
1 1256 2 2256 The CONVERT TO DECIMAL instruction is the
4 .. 4 4 .. 4 opposite of the CONVERT TO BINARY instruc-
tion. CVD converts a signed binary integer in a
CC: 3; (R): 1256; (R): 2256
register to packed decimal and stores the eight-
Example 7 byte result. For example, assume:
1 2
4 4 4 4 4 4 4 Register 1 contains the signed binary integer:
00 00 0F 0F.
CC: 1; (R): 1; (R): 2
Register 13 contains 00 00 76 00.
The DIVIDE instruction divides the dividend in an When the Boolean operator EXCLUSIVE OR is
even-odd register pair by the divisor in a register applied to two bits, the result is one when either,
or in storage. Since the instruction assumes the but not both, of the two bits is one; otherwise, the
dividend to be 64 bits long, it is important first to result is zero. When two bytes are EXCLUSIVE
extend a 32-bit dividend on the left with bits equal ORed, each pair of bits is handled separately;
to the sign bit. For example, assume that: there is no connection from one bit position to
another. The following is an example of the
Storage locations 3550-3553 contain 00 00 08 EXCLUSIVE OR of two bytes:
DE = 22700 (the dividend).
First-operand byte: 11 11
Storage locations 3554-3557 contain 00 00 00 Second-operand byte: 11 11
32 = 500 (the divisor). ──────────────────────────────────
Result byte: 11 11
The initial contents of registers 6 and 7 are
not significant. XC Example
Register 8 contains 00 00 35 50. The EXCLUSIVE OR (XC) instruction can be used
to exchange the contents of two areas in storage
The following assembler-language statements load without the use of an intermediate storage area.
the registers properly and perform the divide oper- For example, assume two three-byte fields in
ation: storage:
┌─────────────┬────────────────────────────────┐ 359 35B
│ Statement │ Comments │ ┌──┬──┬──┐
├─────────────┼────────────────────────────────┤ Field 1 ││17│9│
│L 6,(,8)│ Places 8 DE into reg- │ └──┴──┴──┘
│ │ ister 6. │
│SRDA 6,32() │ Shifts 8 DE into reg- │ 36 362
│ │ ister 7. Register 6 is │ ┌──┬──┬──┐
│ │ filled with zeros (sign │ Field 2 ││14│1│
│ │ bits). │ └──┴──┴──┘
│D 6,4(,8)│ Performs the division. │
└─────────────┴────────────────────────────────┘ Execution of the instruction (assume that register
The machine format of the above DIVIDE instruc- 7 contains 00 00 03 58):
tion is:
Machine Format
When the mask field contains 1111, the ICM Op Code R X B D
instruction produces the same result as LOAD (L) ┌────────┬────┬────┬────┬────┐
(provided that the indexing capability of the RX │ 41 │ 1 │ │ │ 8│
format is not needed), except that ICM also sets └────────┴────┴────┴────┴────┘
the condition code. The condition-code setting is
useful when an all-zero field (condition code 0) or Assembler Format
a leftmost one bit (condition code 1) is used as a Op Code R,D(X,B)
flag. ─────────────────────
LA 1,248(,)
Machine Format
Op Code R X B D When this instruction is executed, the byte in
┌────────┬────┬────┬────┬────┐ storage is ORed with the immediate byte (the I
│ 4C │ B │ E │ F │ 2│ field of the instruction):
└────────┴────┴────┴────┴────┘
Location 4891: 1 1
Immediate byte: 1
Assembler Format ────────────────────────────
Op Code R,D(X,B) Result: 1 11
───────────────────── The resulting byte with bit 7 set to one is stored
MH 11,2(14,15)
back in location 4891. Condition code 1 is set.
Register Format
SHIFT LEFT SINGLE (SLA) Op Code R,M,S
─────────────────────────
The SHIFT LEFT SINGLE instruction is similar to STCM 8,B'111',FIELD3
SHIFT LEFT DOUBLE, except that it shifts only
the 31 numeric bits of a single register. There- Register 8: 12 34 56 78
fore, this instruction performs an algebraic left shift FIELD3 (before): not significant
of a 32-bit signed binary integer. FIELD3 (after): 34 56 78
As another example:
For example, if the contents of register 2 are:
7F A 72 = 1111111 11 1111 Machine Format
Op Code R M S
The instruction: ┌────────┬────┬────┬─────────┐
│ BE │ 9 │ 5 │ │
Machine Format └────────┴────┴────┴─────────┘
Op Code R B D
┌────────┬────┬────┬────┬────┐
│ 8B │ 2 │////│ │ 8│ Register Format
└────────┴────┴────┴────┴────┘ Op Code R,M,S
─────────────────────────
STCM 9,B'11',FIELD2
Assembler Format
Op Code R,D(B)
────────────────── Register 9: 1 23 45 67
SLA 2,8() FIELD2 (before): not significant
FIELD2 (after): 23 67
used to scan a data field for characters with a Note: If the character codes in the statement
special meaning. To indicate which characters being translated occupy a range smaller than 00
have a special meaning, a table similar to the one through FF@, a table of fewer than 256 bytes can
used for the TRANSLATE instruction is set up, be used.
except that zeros in the table indicate characters Figure A-4. Translate and Test Table
without any special meaning and nonzero values
indicate characters with a special meaning. The table entries for the alphameric characters in
EBCDIC are 00; thus, the letter A (code C1) corre-
Figure A-4 has been set up to distinguish alpha- sponds to byte location 20C1, which contains 00.
meric characters (A to Z and 0 to 9) from blanks,
certain special symbols, and all other characters The 15 special symbols have nonzero entries from
which are considered invalid. EBCDIC coding is 04@ to 3C@ in increments of 4. Thus, the blank
assumed. The 256-byte table is assumed stored (code 40) has the entry 04@, the period (code 4B)
at locations 2000-20FF. has the entry 08@, and so on.
Before decimal data in the packed format can be alters the pattern field as follows:
used in a printed report, digits and signs must be
┌───────┬─────┬────────────┬────────┬─────────────┐
converted to printable characters. Moreover, │ │ │Significance│ │ │
punctuation marks, such as commas and decimal │ │ │ Indicator │ │ │
points, may have to be inserted in appropriate │ │ │ (Before/ │ │ Location │
│Pattern│Digit│ After) │ Rule │ 1-1C │
places. The highly flexible EDIT instruction per- ├───────┼─────┼────────────┼────────┼─────────────┤
forms these functions in a single instruction exe- │ b │ │ off/off │leave(1)│bdd,d(d.ddbCR│
cution. │ d │ │ off/off │fill │bbd,d(d.ddbCR│
│ d │ 2 │ off/on(2) │digit │bb2,d(d.ddbCR│
│ , │ │ on/on │leave │same │
This example shows step-by-step one way that │ d │ 5 │ on/on │digit │bb2,5(d.ddbCR│
the EDIT instruction can be used. The field to be │ ( │ 7 │ on/on │digit │bb2,57d.ddbCR│
edited (the source) is four bytes long; it is edited │ d │ 4 │ on/on │digit │bb2,574.ddbCR│
│ . │ │ on/on │leave │same │
against a pattern 13 bytes long. The following │ d │ 2 │ on/on │digit │bb2,574.2dbCR│
symbols are used: │ d │ 6+ │ on/off(3) │digit │bb2,574.26bCR│
│ b │ │ off/off │fill │same │
┌──────────────────────┬───────────────────────┐ │ C │ │ off/off │fill │bb2,574.26bbR│
│ Symbol │ Meaning │ │ R │ │ off/off │fill │bb2,574.26bbb│
├──────────────────────┼───────────────────────┤ ├───────┴─────┴────────────┴────────┴─────────────┤
│ b (Hexadecimal 4) │ Blank character │ │Notes: │
│ ( (Hexadecimal 21) │ Significance starter │ │ │
│ d (Hexadecimal 2) │ Digit selector │ │1. This character is the fill byte. │
└──────────────────────┴───────────────────────┘ │ │
│2. First nonzero decimal source digit turns on │
Assume that register 12 contains: │ significance indicator. │
│ │
1 │3. Plus sign in the four rightmost bits of the │
│ byte turns off significance indicator. │
└─────────────────────────────────────────────────┘
Condition code 1 is set (number less than zero). This pattern field prints as:
$.26 CR
EDIT AND MARK (EDMK) Condition code 1 is set because the number is
less than zero.
The EDIT AND MARK instruction may be used, in
addition to the functions of EDIT, to insert a cur-
rency symbol, such as a dollar sign, at the appro- MULTIPLY DECIMAL (MP)
priate position in the edited result. Assume the
same source in storage locations 1200-1203, the Assume that the signed, packed-decimal number
same pattern in locations 1000-100C, and the in storage locations 1202-1204 (the multiplicand)
same contents of general register 12 as for the is to be multiplied by the signed, packed-decimal
EDIT instruction above. The previous contents of number in locations 500-501 (the multiplier).
general register 1 (GR1) are not significant; a 122 124
LOAD ADDRESS instruction is used to set up the ┌──┬──┬──┐
Multiplicand │38│46│D│
└──┴──┴──┘
Machine Format
Assembler Format Op Code L I S B D
Op Code D(L,B),D(L,B) ┌────────┬────┬────┬────┬────┬────┐
──────────────────────────── │ F │ 4 │ ││ │3F │
MP X'1'(5,4),(2,6) └────────┴────┴────┴────┴────┴─┬┬─┘
┌─┘│
is executed, storage locations 1300-1304 contain │ │
┌─┴┐┌┴─┐
the product: 01 23 45 66 0C.
111111
└──┬─┘
SHIFT AND ROUND DECIMAL │
│
(SRP) 6-bit two's
complement
The SHIFT AND ROUND DECIMAL (SRP) for -1
instruction can be used for shifting decimal
numbers in storage to the left or right. When a Assembler Format
number is shifted right, rounding can also be Op Code S(L),S,I
done. ────────────────────────
SRP FIELD2(5),64-1,
Decimal Left Shift
In this example, the contents of storage location FIELD 2 (before): 1 23 45 67 8C
FIELD1 are shifted three places to the left, effec-
tively multiplying the contents of FIELD1 by 1000. FIELD 2 (after): 12 34 56 7C
FIELD1 is six bytes long. The following instruction
performs the operation:
COMPARE (CD, CDR, CE, CER) However, when two normalized HFP numbers are
compared, the relationship between numbers that
Assume that FPR4 contains 43 00 00 00 00 00 00 compare equal is unique: each digit in one
00 (zero), and FPR6 contains 35 12 34 56 78 9A number must be the same as the corresponding
BC DE (a positive number). The contents of the digit in the other number.
two registers are to be compared using a long-
precision COMPARE instruction.
DIVIDE (DD, DDR, DE, DER)
Machine Format
Op Code R R Assume that the first operand (the dividend) is in
┌────────┬────┬────┐ FPR2 and the second operand (the divisor) in
│ 29 │ 4 │ 6 │ FPR0. If the operands are in the short-precision
└────────┴────┴────┘ format, the resulting quotient is returned to FPR2
by the instruction:
Assembler Format
Op Code R,R Machine Format
────────────── Op Code R R
CDR 4,6 ┌────────┬────┬────┐
│ 3D │ 2 │ │
└────────┴────┴────┘
The number with the smaller characteristic, which
is in register FPR6, is right-shifted 43 - 35 hex
Assembler Format
(67 - 53 decimal) or 14 digit positions, so that the
Op Code R,R
two characteristics agree. The shifted number is ──────────────
43 00 00 00 00 00 00 00, with a guard digit of DER 2,
one. Therefore, when the two numbers are com-
pared, condition code 1 is set, indicating that
Several examples of short-precision HFP division,
operand 1 in FPR4 is less than operand 2 in
with the dividend in FPR2 and the divisor in FPR0,
FPR6.
are shown below. For case A, the result, which
replaces the dividend, is obtained in the following
If the example is changed to a second operand
steps.
with a characteristic of 34 instead of 35, so that
The PERFORM LOCKED OPERATION instruction The enqueueing of N can be done by means of
can be used in a multiprogramming or multiproc- the following steps:
essing environment to perform compare, load, 1. Obtain consistent values of S, H, and C,
compare-and-swap, and store operations on two meaning obtain S and obtain the H and C that
or more discontiguous locations that can be words are consistent with that value of S.
or doublewords. The operations are performed as
an atomic set of operations under the control of a 2. Store H in N.F.
lock that is held only for the duration of the exe- 3. By means of PLO.csdst (PERFORM LOCKED
cution of a single PERFORM LOCKED OPERA- OPERATION performing compare and swap
TION instruction, as opposed to across the exe- and double store), with S as the swap variable
cution of multiple instructions. Since lock con- and H and C as the store variables, add one
tention is resolved by the CPU and is very brief, to S, set H to A(N), and add one to C, pro-
the program need not include a method for vided that S still has the value obtained in
dealing with the case when the lock to be used is step 1. If S has already been changed, go
held by a program being executed by another back to step 1.
CPU. Also, there need be no concern that the
program may be interrupted while it holds a lock, Consistent values of S, H, and C cannot neces-
since PERFORM LOCKED OPERATION will com- sarily be obtained simply by using three LOAD
plete its operation and release its lock before an instructions because a PERFORM LOCKED
interruption can occur. OPERATION instruction being executed by
another CPU may have completed an update of S
PERFORM LOCKED OPERATION can be thought but not yet of H or C. In this case, the three
of as performing concurrent interlocked updates of LOAD instructions will obtain the new S but the
multiple operands. However, the instruction does old H or C. However, as will be described, it may
not actually perform any interlocked update, and a be possible to use three LOAD instructions.
serially reusable resource cannot be updated pre-
dictably through the use of both PERFORM If S is obtained while holding the lock, meaning by
LOCKED OPERATION and conditional-swapping means of PERFORM LOCKED OPERATION, then
instructions (CS and CDS). H and C can be obtained by LOAD instructions
since no other CPU can subsequently change H
Following is an example of how PERFORM or C without changing S, as observed when the
LOCKED OPERATION can be used to add an lock is held.
element at the beginning of a queue.
The parameter list used by the PLO.csdst is as
Assume the following variables associated with follows, assuming the access-register mode is not
the queue: S, which is a sequence number that is used:
┌────────────────────────────────────┬─────┬────────────────────────────────────────────────┬────┬───────┐
│ │Mne- │ │Op │ Page │
│ Name │monic│ Characteristics │Code│ No. │
├────────────────────────────────────┼─────┼─────────┬───────┬─────────────────┬──────┬─────┼────┼───────┤
│ADD │AR │RR C │ │ IF │ R │ │1A │7-12 │
│ADD │A │RX C │ A │ IF │ R │ B│5A │7-12 │
│ADD (extended BFP) │AXBR │RRE C BF│ SP│Db Xi Xo Xu Xx│ │ │B34A│19-18 │
│ADD (long BFP) │ADBR │RRE C BF│ │Db Xi Xo Xu Xx│ │ │B31A│19-18 │
│ADD (long BFP) │ADB │RXE C BF│ A │Db Xi Xo Xu Xx│ │ B│ED1A│19-18 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│ADD (short BFP) │AEBR │RRE C BF│ │Db Xi Xo Xu Xx│ │ │B3A│19-18 │
│ADD (short BFP) │AEB │RXE C BF│ A │Db Xi Xo Xu Xx│ │ B│EDA│19-18 │
│ADD DECIMAL │AP │SS C │ A │Dd DF │ ST│B B│FA │8-6 │
│ADD HALFWORD │AH │RX C │ A │ IF │ R │ B│4A │7-12 │
│ADD HALFWORD IMMEDIATE │AHI │RI C IR│ │ IF │ R │ │A7A │7-12 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│ADD LOGICAL │ALR │RR C │ │ │ R │ │1E │7-13 │
│ADD LOGICAL │AL │RX C │ A │ │ R │ B│5E │7-13 │
| │ADD LOGICAL WITH CARRY │ALCR │RRE C N3│ │ │ R │ │B998│7-13 │
| │ADD LOGICAL WITH CARRY │ALC │RXE C N3│ A │ │ R │ B│E398│7-13 │
│ADD NORMALIZED (extended HFP) │AXR │RR C │ SP│Da EU EO LS │ │ │36 │18-8 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│ADD NORMALIZED (long HFP) │ADR │RR C │ SP│Da EU EO LS │ │ │2A │18-8 │
│ADD NORMALIZED (long HFP) │AD │RX C │ A SP│Da EU EO LS │ │ B│6A │18-8 │
│ADD NORMALIZED (short HFP) │AER │RR C │ SP│Da EU EO LS │ │ │3A │18-8 │
│ADD NORMALIZED (short HFP) │AE │RX C │ A SP│Da EU EO LS │ │ B│7A │18-8 │
│ADD UNNORMALIZED (long HFP) │AWR │RR C │ SP│Da EO LS │ │ │2E │18-1 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│ADD UNNORMALIZED (long HFP) │AW │RX C │ A SP│Da EO LS │ │ B│6E │18-1 │
│ADD UNNORMALIZED (short HFP) │AUR │RR C │ SP│Da EO LS │ │ │3E │18-1 │
│ADD UNNORMALIZED (short HFP) │AU │RX C │ A SP│Da EO LS │ │ B│7E │18-1 │
│AND │NR │RR C │ │ │ R │ │14 │7-13 │
│AND │N │RX C │ A │ │ R │ B│54 │7-13 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│AND (character) │NC │SS C │ A │ │ ST│B B│D4 │7-13 │
│AND (immediate) │NI │SI C │ A │ │ ST│B │94 │7-13 │
│BRANCH AND LINK │BALR │RR │ │ T │B R │ │5 │7-14 │
│BRANCH AND LINK │BAL │RX │ │ │B R │ │45 │7-14 │
│BRANCH AND SAVE │BASR │RR │ │ T │B R │ │D │7-15 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│BRANCH AND SAVE │BAS │RX │ │ │B R │ │4D │7-15 │
│BRANCH AND SAVE AND SET MODE │BASSM│RR │ │ T │B R │ │C │7-16 │
│BRANCH AND SET AUTHORITY │BSA │RRE BS│Q A │SO T │B R │ │B25A│1-7 │
│BRANCH AND SET MODE │BSM │RR │ │ │B R │ │B │7-16 │
│BRANCH AND STACK │BAKR │RRE │ A │SF T │B ST│ │B24│1-1 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│BRANCH IN SUBSPACE GROUP │BSG │RRE SG│ A │SO T │B R │ R│B258│1-13 │
│BRANCH ON CONDITION │BCR │RR │ │ ¢ │B │ │7 │7-17 │
│BRANCH ON CONDITION │BC │RX │ │ │B │ │47 │7-17 │
│BRANCH ON COUNT │BCTR │RR │ │ │B R │ │6 │7-18 │
│BRANCH ON COUNT │BCT │RX │ │ │B R │ │46 │7-18 │
├────────────────────────────────────┼─────┼─────────┼───────┼─────────────────┼──────┼─────┼────┼───────┤
│BRANCH ON INDEX HIGH │BXH │RS │ │ │B R │ │86 │7-18 │
│BRANCH ON INDEX LOW OR EQUAL │BXLE │RS │ │ │B R │ │87 │7-18 │
│BRANCH RELATIVE AND SAVE │BRAS │RI IR│ │ │B R │ │A75 │7-19 │
│BRANCH RELATIVE AND SAVE LONG │BRASL│RIL N3│ │ │B R │ │C5 │7-19 │
│BRANCH RELATIVE ON CONDITION │BRC │RI IR│ │ │B │ │A74 │7-2 │
└────────────────────────────────────┴─────┴─────────┴───────┴─────────────────┴──────┴─────┴────┴───────┘
Figure B-1 (Part 1 of 10). Instructions Arranged by Name
┌────────────────────────────┬───────────────────────────────────────────────────────────────┐
│ │ Condition Code │
│ ├───────────────┬───────────────┬───────────────┬───────────────┤
│ Instruction │ │ 1 │ 2 │ 3 │
├────────────────────────────┼───────────────┼───────────────┼───────────────┼───────────────┤
│ADD (gen) │Zero │< zero │> zero │Overflow │
│ADD (BFP) │Zero │< zero │> zero │NaN │
│ADD DECIMAL │Zero │< zero │> zero │Overflow │
│ADD HALFWORD │Zero │< zero │> zero │Overflow │
│ADD HALFWORD IMMEDIATE │Zero │< zero │> zero │Overflow │
├────────────────────────────┼───────────────┼───────────────┼───────────────┼───────────────┤
│ADD LOGICAL │Zero, │Not zero, │Zero, │Not zero, │
│ │ no carry │ no carry │ carry │ carry │
│ADD LOGICAL WITH CARRY │Zero, │Not zero, │Zero, │Not zero, │
│ │ no carry │ no carry │ carry │ carry │
│ADD NORMALIZED │Zero │< zero │> zero │-- │
│ADD UNNORMALIZED │Zero │< zero │> zero │-- │
│AND │Zero │Not zero │-- │-- │
├────────────────────────────┼───────────────┼───────────────┼───────────────┼───────────────┤
│CANCEL SUBCHANNEL │Function │-- │-- │Not operational│
│ │ initiated │ │ │ │
│CHECKSUM │Checksum │-- │-- │CPU-determined │
│ │ complete │ │ │ completion │
| │CIPHER MESSAGE │Normal │-- │-- │Partial │
| │ │ completion │ │ │ completion │
| │CIPHER MESSAGE WITH CHAINING│Normal │-- │-- │Partial │
| │ │ completion │ │ │ completion │
│CLEAR SUBCHANNEL │Function │-- │-- │Not operational│
│ │ initiated │ │ │ │
├────────────────────────────┼───────────────┼───────────────┼───────────────┼───────────────┤
│COMPARE (gen, HFP) │Equal │Low │High │-- │
│COMPARE (BFP) │Equal │Low │High │Unordered │
│COMPARE AND FORM CODEWORD │Equal │OCB=: low │OCB=: high │-- │
│ │ │OCB=1: high │OCB=1: low │ │
│COMPARE AND SIGNAL │Equal │Low │High │Unordered │
│COMPARE AND SWAP │Equal │Not equal │-- │-- │
└────────────────────────────┴───────────────┴───────────────┴───────────────┴───────────────┘
Figure C-1 (Part 1 of 6). Summary of Condition-Code Settings
┌────────────────────────────────────────────────────────────────────────────────────────────┐
│Explanation: │
│ │
│ > zero Result greater than zero. │
│ < zero Result less than zero. │
│ =< 256 Equal to, or less than, 256. │
│ > 256 Greater than 256. │
│ gen General instruction. │
│ BFP Binary-floating-point instruction. │
│ High First operand high. │
│ HFP Hexadecimal-floating-point instruction. │
│ Low First operand low. │
│ Length Length of first operand. │
│ NaN Not-a-number. │
│ OCB Operand-control bit. │
└────────────────────────────────────────────────────────────────────────────────────────────┘
Figure C-1 (Part 6 of 6). Summary of Condition-Code Settings