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AD574A
AD574A
–2– REV. B
AD574A
AD574AS AD574AT AD574AU
Model Min Typ Max Min Typ Max Min Typ Max Units
RESOLUTION 12 12 12 Bits
LINEARITY ERROR @ +25°C ±1 ± 1/2 ± 1/2 LSB
TMIN to TMAX ±1 ±1 ±1 LSB
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
TMIN to TMAX 11 12 12 Bits
UNIPOLAR OFFSET (Adjustable to Zero) ±2 ±1 ±1 LSB
BIPOLAR OFFSET (Adjustable to Zero) ±4 ±4 ±2 LSB
FULL-SCALE CALIBRATION ERROR
(With Fixed 50 Ω Resistor from REF OUT to REF IN)
(Adjustable to Zero) 0.25 0.25 0.125 % of FS
TEMPERATURE RANGE –55 +125 –55 +125 –55 +125 °C
TEMPERATURE COEFFICIENTS
(Using Internal Reference)
(TMIN to TMAX)
Unipolar Offset ± 2 (5) ± 1 (2.5) ± 1 (2.5) LSB (ppm/°C)
Bipolar Offset ± 4 (10) ± 2 (5) ± 1 (2.5) LSB (ppm/°C)
Full-Scale Calibration ± 20 (50) ± 10 (25) ± 5 (12.5) LSB (ppm/°C)
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
VCC = 15 V ± 1.5 V or 12 V ± 0.6 V ±2 ±1 ±1 LSB
VLOGIC = 5 V ± 0.5 V ± 1/2 ± 1/2 ± 1/2 LSB
VEE = –15 V ± 1.5 V or –12 V ± 0.6 V ±2 ±1 ±1 LSB
ANALOG INPUT
Input Ranges
Bipolar –5 +5 –5 +5 –5 +5 Volts
–10 +10 –10 +10 –10 +10 Volts
Unipolar 0 +10 0 +10 0 +10 Volts
0 +20 0 +20 0 +20 Volts
Input Impedance
10 Volt Span 3 5 7 3 5 7 3 5 7 kΩ
20 Volt Span 6 10 14 6 10 14 6 10 14 kΩ
DIGITAL CHARACTERISTICS 1 (TMIN–TMAX)
Inputs2 (CE, CS, R/C, A0)
Logic “1” Voltage +2.0 +5.5 +2.0 +5.5 +2.0 +5.5 Volts
Logic “0” Voltage –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 Volts
Current –20 +20 –20 +20 –20 +20 µA
Capacitance 5 5 5 pF
Output (DB11–DB0, STS)
Logic “1” Voltage (I SOURCE ≤ 500 µA) +2.4 +2.4 +2.4 Volts
Logic “0” Voltage (I SINK ≤ 1.6 mA) +0.4 +0.4 +0.4 Volts
Leakage (DB11–DB0, High-Z State) –20 +20 –20 +20 –20 +20 µA
Capacitance 5 5 5 pF
POWER SUPPLIES
Operating Range
VLOGIC +4.5 +5.5 +4.5 +5.5 +4.5 +5.5 Volts
VCC +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 Volts
VEE –11.4 –16.5 –11.4 –16.5 –11.4 –16.5 Volts
Operating Current
ILOGIC 30 40 30 40 30 40 mA
ICC 2 5 2 5 2 5 mA
IEE 18 30 18 30 18 30 mA
POWER DISSIPATION 390 725 390 725 390 725 mW
INTERNAL REFERENCE VOLTAGE 9.98 10.0 10.02 9.98 10.0 10.02 9.99 10.0 10.01 Volts
Output Current (Available for External Loads) 3 1.5 1.5 1.5 mA
(External Load Should not Change During Conversion)
PACKAGE OPTION4
Ceramic (D-28) AD574ASD AD574ATD AD574AUD
NOTES
1
Detailed Timing Specifications appear in the Timing Section.
2
12/8 Input is not TTL-compatible and must be hard wired to V LOGIC or Digital Common.
3
The reference should be buffered for operation on ± 12 V supplies.
4
D = Ceramic DIP.
Specifications subject to change without notice.
REV. B –3–
AD574A
+5V SUPPLY STATUS
VLOGIC 1 28
STS
DATA MODE SELECT MSB DB11
2 27
12/8 N MSB
CHIP SELECT CONTROL I
3 B 26 DB10
CS 3
BYTE ADDRESS/ B
SHORT CYCLE 4 L 25 DB9
S E
AO T
READ/CONVERT 5 CLOCK SAR 12 A A 24 DB8
R/C T
CHIP ENABLE 6 E 23 DB7
3k N
CE I
O
+12/+15V SUPPLY 7 U B 22 DB6 DIGITAL
VCC B
COMP 12 T
L DATA
+10V REFERENCE 8 10V P 21 DB5
IDAC U E OUTPUTS
REF OUT REF
IDAC = T B
ANALOG COMMON 9 20 DB4
AC 4 x N x IREF B
REFERENCE INPUT 10 U N
F 19 DB3
REF IN 19.95k IREF 8k I
F B
-12/-15V SUPPLY 11 E B 18 DB2
VEE R
9.95k L
BIPOLAR OFFSET 12 S E 17 DB1
BIP OFF
5k DAC N VEE C
10V SPAN INPUT DB0
10VIN 13 LSB 16 LSB
5k
20V SPAN INPUT 14
AD574A 12 15 DIGITAL COMMON
20VIN DC
ORDERING GUIDE
Resolution Max
Temperature Linearity Error No Missing Codes Full Scale
Model1 Range Max (TMIN to TMAX) (TMIN to TMAX) T.C. (ppm/°C)
AD574AJ(X) 0°C to +70°C ± 1 LSB 11 Bits 50.0
AD574AK(X) 0°C to +70°C ± 1/2 LSB 12 Bits 27.0
AD574AL(X) 0°C to +70°C ± 1/2 LSB 12 Bits 10.0
AD574AS(X)2 –55°C to +125°C ± 1 LSB 11 Bits 50.0
AD574AT(X)2 –55°C to +125°C ± 1 LSB 12 Bits 25.0
AD574AU(X)2 –55°C to +125°C ± 1 LSB 12 Bits 12.5
NOTES
1
X = Package designator. Available packages are: D (D-28) for all grades. E (E-28A) for J and K grades and /883B processed S, T
and U grades. N (N-28) for J, K, and L grades. P (P-28A) for PLCC in J, K grades. Example: AD574AKN is K grade in plastic DIP.
2
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military Products
Databook.
–4– REV. B
AD574A
THE AD574A OFFERS GUARANTEED MAXIMUM LINEARITY ERROR OVER THE FULL OPERATING
TEMPERATURE RANGE
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
REV. B –5–
AD574A
CIRCUIT OPERATION DRIVING THE AD574 ANALOG INPUT
The AD574A is a complete 12-bit A/D converter which requires The internal circuitry of the AD574 dictates that its analog
no external components to provide the complete successive- input be driven by a low source impedance. Voltage changes at
approximation analog-to-digital conversion function. A block the current summing node of the internal comparator result in
diagram of the AD574A is shown in Figure 1. abrupt modulations of the current at the analog input. For accu-
rate 12-bit conversions the driving source must be capable of
+5V SUPPLY STATUS
holding a constant output voltage under these dynamically
1 28
VLOGIC STS
DB11
changing load conditions.
DATA MODE SELECT 2 MSB 27
12/8 N MSB
CHIP SELECT 3 CONTROL I 26 DB10
CS B FEEDBACK TO AMPLIFIER
3 B
BYTE ADDRESS/
SHORT CYCLE 4 L 25 DB9 V+
S E
AO T
READ/CONVERT 5 CLOCK SAR 12 A A 24 DB8
R/C T
CHIP ENABLE 6 E 23 DB7
3k N
CE I
O AD574A
+12/+15V SUPPLY 7 U B 22 DB6 DIGITAL
VCC B CURRENT
COMP 12 T
L DATA LIMITING
+10V REFERENCE 8 10V P 21 DB5
IDAC U E OUTPUTS RESISTORS
REF OUT REF RIN IIN
IDAC = T B CURRENT
ANALOG COMMON 9 20 DB4 OUTPUT
AC 4 x N x IREF B iDIFF iTEST DAC
IIN IS MODULATED BY
REFERENCE INPUT 10 U N
F 19 DB3 CHANGES IN TEST CURRENT. COMPARATOR
REF IN 19.95k IREF 8k I AMPLIFIER PULSE LOAD
F B
-12/-15V SUPPLY 11 E 18 DB2 RESPONSE LIMITED BY
VEE B
R L V–
OPEN LOOP OUTPUT IMPEDANCE.
BIPOLAR OFFSET 9.95k S
12 E 17 DB1
BIP OFF ANALOG COMMON SAR
5k DAC N VEE C
10V SPAN INPUT DB0
10VIN 13 LSB 16 LSB
5k
20V SPAN INPUT 14
20VIN AD574A 12 15
DIGITAL COMMON
DC
Figure 2. Op Amp – AD574A Interface
The output impedance of an op amp has an open-loop value
Figure 1. Block Diagram of AD574A 12-Bit A-to-D Converter which, in a closed loop, is divided by the loop gain available at
When the control section is commanded to initiate a conversion the frequency of interest. The amplifier should have acceptable
(as described later), it enables the clock and resets the successive- loop gain at 500 kHz for use with the AD574A. To check
approximation register (SAR) to all zeros. Once a conversion whether the output properties of a signal source are suitable,
cycle has begun, it cannot be stopped or restarted and data is monitor the AD574’s input with an oscilloscope while a conver-
not available from the output buffers. The SAR, timed by the sion is in progress. Each of the 12 disturbances should subside
clock, will sequence through the conversion cycle and return an in 1 µs or less.
end-of-convert flag to the control section. The control section For applications involving the use of a sample-and-hold ampli-
will then disable the clock, bring the output status flag low, and fier, the AD585 is recommended. The AD711 or AD544 op
enable control functions to allow data read functions by external amps are recommended for dc applications.
command.
During the conversion cycle, the internal 12-bit current output SAMPLE-AND-HOLD AMPLIFIERS
DAC is sequenced by the SAR from the most significant bit Although the conversion time of the AD574A is a maximum of
(MSB) to least significant bit (LSB) to provide an output cur- 35 µs, to achieve accurate 12-bit conversions of frequencies
rent which accurately balances the input signal current through greater than a few Hz requires the use of a sample-and-hold
the 5 kΩ (or 10 kΩ) input resistor. The comparator determines amplifier (SHA). If the voltage of the analog input signal driving
whether the addition of each successively-weighted bit current the AD574A changes by more than 1/2 LSB over the time
causes the DAC current sum to be greater or less than the input interval needed to make a conversion, then the input requires a
current; if the sum is less, the bit is left on; if more, the bit is SHA.
turned off. After testing all the bits, the SAR contains a 12-bit The AD585 is a high linearity SHA capable of directly driving
binary code which accurately represents the input signal to the analog input of the AD574A. The AD585’s fast acquisition
within ± 1/2 LSB. time, low aperture and low aperture jitter are ideally suited for
The temperature-compensated buried Zener reference provides high-speed data acquisition systems. Consider the AD574A
the primary voltage reference to the DAC and guarantees excel- converter with a 35 µs conversion time and an input signal of
lent stability with both time and temperature. The reference is 10 V p-p: the maximum frequency which may be applied to
trimmed to 10.00 volts ± 0.2%; it can supply up to 1.5 mA to an achieve rated accuracy is 1.5 Hz. However, with the addition of
external load in addition to the requirements of the reference in- an AD585, as shown in Figure 3, the maximum frequency
put resistor (0.5 mA) and bipolar offset resistor (1 mA) when increases to 26 kHz.
the AD574A is powered from ± 15 V supplies. If the AD574A is The AD585’s low output impedance, fast-loop response, and
used with ± 12 V supplies, or if external current must be sup- low droop maintain 12-bits of accuracy under the changing load
plied over the full temperature range, an external buffer ampli- conditions that occur during a conversion, making it suitable for
fier is recommended. Any external load on the AD574A use in high accuracy conversion systems. Many other SHAs
reference must remain constant during conversion. The cannot achieve 12-bits of accuracy and can thus compromise a
thin-film application resistors are trimmed to match the system. The AD585 is recommended for AD574A applications
full-scale output current of the DAC. There are two 5 kΩ input requiring a sample and hold.
scaling resistors to allow either a 10 volt or 20 volt span. The An alternate approach is to use the AD1674, which combines
10 kΩ bipolar offset resistor is grounded for unipolar operation the ADC and SHA on one chip, with a total throughput time of
and connected to the 10 volt reference for bipolar operation. 10 µs.
–6– REV. B
AD574A
+VS +15V page. Analog input connections and calibration are easily ac-
TO A1 +
C1
+ +5V complished; the unipolar operating mode is shown in Figure 4.
+ C3
A
VREF –VS C2
–15V
AGND TO A1
2 12/8
STS 28
11 1 2 6 7
+VS 3 CS
8 OFFSET
R2 R1 HIGH 27
100k 4 AO BIT 24
14 13 12 11 10 9 8 100Ω 12-BIT
10 3-STATE –12V/–15V +12V/+15V
10k 10k GAIN 5 R/C
DATA MIDDLE 23
13 A2 27 BITS 20
6 CE
100pF +15V R4 AD574A
100k GAIN AD574A
R1
16 LOW 19
A1 100k 12 100k
OFFSET 10 REF IN BITS 16
AD585 9 R2
R3
–15V 100Ω 3
100Ω 8 REF OUT
1 2 3 4 5 6 7
4 100Ω
12 BIP OFF
15
ANALOG –VS A 28 5
INPUT
0V TO +10V 0 TO +10V +5V 1
STATUS 13 10VIN
CONVERT 7404 OR EQ. ANALOG +15V 7
INPUTS
NOTE 14 20VIN 11
–15V
µ TANTALUM, BYPASSED BY
1. C1, C2, C3 ARE 47mF 0 TO +20V
µ CERAMIC. LOCATE AT ASSOCIATED A2 PINS.
0.1mF
9 ANA COM DIG COM 15
REV. B –7–
AD574A
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to START CONVERT
give the last transition (1111 1111 1110 to 1111 1111 1111).
tions are sufficient, one or both of the trimmers shown can be VALUE OF A0
AT LAST CONVERT
replaced by a 50 Ω ± 1% fixed resistor. Bipolar calibration is A0 COMMAND
similar to unipolar calibration. First, a signal 1/2 LSB above READ EOC8 FROM
negative full scale (–4.9988 V for the ± 5 V range) is applied and EOC12 NOTE 1
2 12/8 NOTE 1: WHEN START CONVERT GOES LOW, THE EOC (END OF CONVERSION) SIGNALS GO LOW.
STS 28 EOC8 RETURNS HIGH AFTER AN 8-BIT CONVERSION CYCLE IS COMPLETE, AND EOC12
3 CS RETURNS HIGH WHEN ALL 12-BITS HAVE BEEN CONVERTED. THE EOC SIGNALS PREVENT
27
HIGH DATA FROM BEING READ DURING CONVERSIONS.
4 AO BIT 24
5 R/C NOTE 2: 12/8 IS NOT A TTL-COMPATABLE INPUT AND SHOULD ALWAYS BE WIRED DIRECTLY TO
MIDDLE 23
BITS 20
VLOGIC OR DIGITAL COMMON.
6 CE
R2 AD574A
LOW 19
GAIN
100Ω
10 REF IN BITS 16 Figure 6. AD574A Control Logic
8 REF OUT
An output signal, STS, indicates the status of the converter.
OFFSET
R1
12 BIP OFF
STS goes high at the beginning of a conversion and returns low
100Ω
65V
13 10VIN
+5V 1 when the conversion cycle is complete.
ANALOG +15V 7
INPUTS
610V
14 20VIN
–15V 11 Table I. AD574A Truth Table
9 ANA COM DIG COM 15
CE CS R/C 12/8 AO Operation
0 X X X X None
Figure 5. Bipolar Input Connections X 1 X X X None
CONTROL LOGIC 1 0 0 X 0 Initiate 12-Bit Conversion
The AD574A contains on-chip logic to provide conversion ini- 1 0 0 X 1 Initiate 8-Bit Conversion
tiation and data read operations from signals commonly avail- 1 0 1 Pin 1 X Enable 12-Bit Parallel Output
able in microprocessor systems. Figure 6 shows the internal
logic circuitry of the AD574A. 1 0 1 Pin 15 0 Enable 8 Most Significant Bits
1 0 1 Pin 15 1 Enable 4 LSBs + 4 Trailing Zeroes
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both TIMING
asserted determines whether a data read (R/C = 1) or a convert The AD574A is easily interfaced to a wide variety of micropro-
(R/C = 0) is in progress. The register control inputs AO and cessors and other digital systems. The following discussion of
12/8 control conversion length and data format. The AO line is the timing requirements of the AD574A control signals should
usually tied to the least significant bit of the address bus. If a provide the system designer with useful insight into the opera-
conversion is started with AO low, a full 12-bit conversion cycle tion of the device.
is initiated. If AO is high during a convert start, a shorter 8-bit
conversion cycle results. During data read operations, AO deter- Table II. Convert Start Timing—Full Control Mode
mines whether the three-state buffers containing the 8 MSBs of
the conversion result (AO = 0) or the 4 LSBs (AO = 1) are Symbol Parameter Min Typ Max Units
enabled. The 12/8 pin determines whether the output data is
to be organized as two 8-bit words (12/8 tied to DIGITAL tDSC STS Delay from CE 400 ns
COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The tHEC CE Pulse Width 300 ns
12/8 pin is not TTL-compatible and must be hard-wired to tSSC CS to CE Setup 300 ns
either VLOGIC or DIGITAL COMMON. In the 8-bit mode, the tHSC CS Low During CE High 200 ns
byte addressed when AO is high contains the 4 LSBs from the tSRC R/C to CE Setup 250 ns
conversion followed by four trailing zeroes. This organization tHRC R/C Low During CE High 200 ns
allows the data lines to be overlapped for direct interface to tSAC AO to CE Setup 0 ns
8-bit buses without the need for external three-state buffers. tHAC AO Valid During CE High 300 ns
tC Conversion Time
It is not recommended that AO change state during a data read
8-Bit Cycle 10 24 µs
operation. Asymmetrical enable and disable times of the
12-Bit Cycle 15 35 µs
three-state buffers could cause internal bus contention resulting
in potential damage to the AD574A.
–8– REV. B
AD574A
Figure 7 shows a complete timing diagram for the AD574A con- Table III. Read Timing—Full Control Mode
vert start operation. R/C should be low before both CE and CS
are asserted; if R/C is high, a read operation will momentarily Symbol Parameter Min Typ Max Units
occur, possibly resulting in system bus contention. Either CE or tDD1 Access Time (from CE) 200 ns
CS may be used to initiate a conversion; however, use of CE is tHD Data Valid After CE Low 25 ns
recommended since it includes one less propagation delay than tHL2 Output Float Delay 100 ns
CS and is the faster input. In Figure 7, CE is used to initiate the tSSR CS to CE Setup 150 ns
conversion. tSRR R/C to CE Setup 0 ns
tSAR AO to CE Setup 150 ns
tHSR CS Valid After CE Low 50 ns
tHRR R/C High After CE Low 0 ns
tHAR AO Valid After CE Low 50 ns
NOTES
1
tDD is measured with the load circuit of Figure 9 and defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 10.
“STAND-ALONE” OPERATION
The AD574A can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
In this mode, CE and 12/8 are wired high, CS and AO are wired
low, and conversion is controlled by R/C. The three-state buff-
Figure 8. Read Cycle Timing ers are enabled when R/C is high and a conversion starts when
R/C goes low. This allows two possible control signals—a high
In the 8-bit bus interface mode (12/8 input wired to DIGITAL pulse or a low pulse. Operation with a low pulse is shown in
COMMON), the address bit, AO, must be stable at least 150 ns Figure 11. In this case, the outputs are forced into the high
prior to CE going high and must remain stable during the entire impedance state in response to the falling edge of R/C and return
read cycle. If AO is allowed to change, damage to the AD574A
output buffers may result.
–10– REV. B
AD574A
Note: Due to the large number of options that may be installed
in the PC, the I/O bus loading should be limited to one Schottky
TTL load. Therefore, a buffer/driver should be used when inter-
facing more than two AD574As to the I/O bus.
8086 Interface
The data mode select pin (12/8) of the AD574A should be con-
nected to VLOGIC to provide a 12-bit data output. To prevent
possible bus contention, a demultiplexed and buffered address/
data bus is recommended. In the cases where the 8-bit short
conversion cycle is not used, A0 should be tied to digital com-
mon. Figure 18 shows a typical 8086 configuration.
IBM PC Interface
The AD574A appears in Figure 17 interfaced to the 4 MHz
8088 processor of an IBM PC. Since the device resides in I/O Figure 18. 8086—AD574A with Buffered Bus lnterface
space, its address is decoded from only the lower ten address For clock speeds greater than 4 MHz wait state insertion similar
lines and must be gated with AEN (active low) to mask out in- to Figure 16 is recommended to ensure sufficient CE and R/C
ternal DMA cycles which use the same I/O address space. This pulse duration.
active low signal is applied to CS. IOR and IOW are used to
initiate the conversion and read, and are gated together to drive The AD574A can also be interfaced in a stand-alone mode (see
the chip enable, CE. Because the data bus width is limited to Figure 13). A low going pulse derived from the 8086’s WR sig-
8 bits, the AD574A data resides in two adjacent addresses nal logically ORed with a low address decode starts the conver-
selected by A0. sion. At the end of the conversion, STS clocks the data into the
three-state latches.
68000 Interface
The AD574, when configured in the stand-alone mode, will eas-
ily interface to the 4 MHz version of the 68000 microprocessor.
The 68000 R/W signal combined with a low address decode ini-
tiates conversion. The UDS or LDS signal, with the decoded
address, generates the DTACK input to the processor, latching
in the AD574A’s data. Figure 19 illustrates this configuration.
REV. B –11–