Professional Documents
Culture Documents
Analog Electronics PDF
Analog Electronics PDF
ANALOG ELECTRONICS
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 4 The amplifier shown below has a voltage gain of - 2.5 , an input resistance of
10 kW, and a lower 3-dB cut-off frequency of 20 Hz. Which one of the following
statements is TRUE when the emitter resistance RE is doubled ?
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
(A) 24 V (B) 28 V
(C) 30 V (D) 32 V
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 11 In the ideal op-amp circuit given in the adjoining figure, the value of R f is varied
from 1 kW to 100 kW. The gain G = bV0 l will
Vi
Q. 12 The matched transistors Q1 and Q2 shown in the adjoining figure have b = 100.
Assuming the base-emitter voltages to be 0.7 V, the collector-emitter voltage V2
of the transistors Q2 is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 13 An active filter is shown in the adjoining figure. The dc gain and the 3 dB cut-off
frequency of the filter respectively, are, nearly
Q. 14 The input impedances seen looking into the terminals V1 and V2 with respect to
ground, respectively are
(A) 47 kW 43 kW (B) 47 kW and 47 kW
(C) 47 kW and 51 kW (D) 517 kW and 517 kW
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 17 In the circuit shown, the Zener diode has ideal characteristics and a breakdown
voltage of 3.2 V. The output voltage V0 for an input voltage Vi =+ 1V is closed to
Q. 18 The input resistance of the circuit shown in the figure assuming an ideal op-amp,
is
Q. 19 In the circuit shown in the figure, the switch S has been in Position 1 for a long
time. It is then moved to Position 2. Assume the Zener diodes to be idea. The
time delay between the switch moving to position 2 and the transition in the
output voltage V0 is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 21 The circuit is used at a sampling rate of 1 kHz, with an A/D converter having a
conversion time of 200 ms. The op-amp has an input bias current of 10 nA. The
maximum hold error is
(A) 1 mV (B) 2 mV
(C) 5 mV (D) 10 mV
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 25 In the circuit shown below, the ideality factor h of the diode is unity and the
voltage drop across it is 0.7 V. The dynamic resistance of the diode at room
temperature is approximately
(A) 15 W (B) 25 W
(C) 50 W (D) 700 W
Q. 27 A differential amplifier shown below has a differential mode gain of 100 and a
CMRR of 40 dB. If V1 = 0.55 and V2 = 0.45 V, the output V0 is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 29 In the op-amp circuit shown below is that of Vin is gradually increased from - 10
V to + 10 V. Assuming that the output voltage Vout saturates at - 10 V and + 10
V, Vout will change from
(A) - 10V to + 10V when Vin =- 1V (B) - 10V to + 10V when Vin =+ 1V
(C) + 10V to - 10V when Vin =- 1V (D) + 10 V to - 10 V when Vin =+ 1 V
(A) - 10 V (B) - 5 V
(C) + 5 V (D) + 10 V
Q. 31 In the amplifier circuit shown below, assume VBE = 0.7 V and the b of the transistor
and the values of C1 and C2 are extremely high. If the amplifier is designed such
that at the quiescent point its VCE = VCC , When VCC is the power supply voltage,
2
its small signal voltage gain Vout will be
Vin
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 32 When the light falls on the photodiode shown in the following circuit, the reverse
saturation current of the photodiode changes form 100 mA to 200 mA .
Assuming the op-amp to be ideal, the output voltage, Vout of the circuit.
(A) does not change (B) changes from 1 V to 2 V
(C) changes from 2 V to 1 V (D) changes from - 1V to - 2 V
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 34 Consider the linear circuit with and ideal op-amp shown in the figure below.
The Z-parameters of the two port feedback network are Z11 = Z22 = 11kW and
Z12 = Z21 = 1kW . The gain of the amplifier is
(A) + 110 (B) + 11
(C) - 1 (D) - 120
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 38 The three transistors in the circuit shown below are identical, with
VBE = 0.7 V and b = 100 .
The voltage Vc is
(A) 0.2 V (B) 2 V
(C) 7.4 V (D) 10 V
Q. 39 The input signal shown in the figure below is fed to a Schmitt trigger. The signal
has a square wave amplitude of 6 V p-p. It is corrupted by an additive by an
additive high frequency noise of amplitude 8V p-p.
Which one of the following is an appropriate choice for the upper and lower trip
points of the Schmitt trigger to recover a square wave of the same frequency from
the corrupted input signal Vi ?
(A) !8.0 V (B) !2.0 V
(C) !0.5 V (D) 0 V
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 41 In the circuit shown below the switch (S) is closed whenever the input voltage (
Vin ) is positive and open otherwise.
The circuit is a
(A) Low pass filter (B) Level shifter
(C) Modulator (D) Precision rectifier
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Assume that the op-amps are idea and have !12 V power supply. If the input
is a !5V 50 Hz square wave of duty cycle 50%, the condition that results in a
triangular wave of peak to peak amplitude 5 V and frequency 50 Hz at the output
is
(A) RC = 1 (B) R = 1
C
(C) R = 5 (D) C = 5
C R
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 46 If the value of the resistance R in the following figure is increased by 50%, then
voltage gain of the amplifier shown in the figure will change by.
(A) 50 % (B) 5%
(C) - 50 % (D) Negligible amount
Q. 47 When the switch S2 is closed the gain of the programmable gain amplifier shown
in the following figure is
Q. 48 In the circuit shown in the following figure, the op-amp has input bias current
Ib < 10 nA , and input offset voltage Vio < 1. The maximum dc error in the output
voltage is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 49 The potential difference between the input terminals of an op amp may be treated
to be nearly zero, if
(A) the two supply voltages are balanced
(B) The output voltage is not saturated
(C) the op-amp is used in a circuit having negative feedback
(D) there is a dc bias path between each of the input terminals and the circuit
ground
Q. 50 A dual op-amp instrumentation amplifier is shown below. The expression for the
output of the amplifier is given by.
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 52 The biasing circuit of a silicon transistor is shown below. If b = 80, then what is
VCE for the transistor ?
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 54 If the circuit has the input lower trip point (LTP) = 0 V, then value of R1 is
R2
given as.
(A) 0.223 (B) 2.67
(C) 4.67 (D) 3
Q. 56 The peak value of the output voltage V0 across the capacitor shown in the figure
for a 2230:9 transformer and a 230 V, 50 Hz, input assuming 0.7 V diode drop
and an ideal transformer, is
Q. 57 In the circuit shown in the given figure the input voltage Vin (t) is given by 2
sin (100pt). For RL in the range 0.5 kW to 1.5 kW to 1.5 kW, the current through
RL is.
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 59 In the circuit shown in the figure the input voltage Vi is a symmetrical saw-tooth
wave of average value zero, positive slope and peak-to-peak value 20 V. The
average value of the output, assuming an ideal operational amplifier with peak-
to-peak symmetrical swing of 30 V, is
(A) 5 V (B) 10 V
(C) - 5 V (D) 7.5 V
(A) bV - V0 l (B) V0
V V
(C) bV - V0 l (D) V
V0 V0
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 62 For the circuit shown in the figure, IDSQ (in mA) and VGSQ (in V) are related
through 2 IDSQ = (4 + VGSQ) 2 .
The following data is given :
VDD = 15 V, R1 = 1.0 MW, R2 = 6.5 MW, RD = 2.0 kW, RS = 1.0 kW,
IDSS = 8 mA. The value of IDSQ, assuming the gate current is negligible, is
approximately equal to.
Q. 63 In the circuit shown in the figure, assuming ideal diose characteristics with zero
forward resistance and 0.7 V forward drop, the average value of V0 when the input
waveform is as shown, is
Q. 64 For the RC circuit shown in the figure, the condition for obtaining an attenuation,
Vout Vin , of 1/3 at a frequency w rad/s is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 65 In the circuit, in order to get V0 in the range of 0-30 V, the range of Vin is
(A) 0-30 V (B) 0.20 V
(C) 0-15 V (D) 1.10 V
(A) v0 (t) = vi (t), for all vi (t) (B) v0 (t) = vi (t), for vi (t) vR
= 0, otherwise
(C) v0 (t) = vi (t), for vi (t), for vi (t) < vR (D) v0 (t) = vi (t), for vi (t) > vR
= vR, otherwise = vR, otherwise
Q. 68 The output of the op-amp in the circuit of Fig. is
(A) 0 V (B) - 3 V
(C) + 1.5 V (D) + 3 V
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
(A) - 30 (B) - 10
(C) + 40 (D) + 60
(A) - 5 V (B) - 3 V
(C) + 3 V (D) + 5 V
(A) 8 (B) 4
(C) - 4 (D) 3RL
R
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
(A) R2 Vd (B) R2 Vd
R R1
(C) R2 V (D) R2 V
R1 d R (1 + d)
Q. 74 V1 and V2 are the input voltages of an instrumentation amplifier. The output of the
instrumentation amplifier is found to be 100 (V1 - V2) +10 - 4 (V1 + V2). The gain
and the common mode rejection ratio (CMRR) of the instrumentation amplifier
respectively are
(A) (50, 60 dB) (B) (50 120 dB)
(C) (100, 60 dB) (D) (100, 120 dB)
(A) Band-pass filter with lower cut-off wl = 1 and higher cut off w = 1
H
R1 C1 R2 C2
(B) Band-reject filter with lower cut-off w1 = 1 and higher cut off wH = 1
R1 C1 R2 C2
(C) Band-pass filter with lower cut-off wl = 1 and higher cut off wH = 1
R2 C2 R1 C1
(D) Band-reject filter with lower cut-off wl = 1 and higher cut off
R2 C2
wH = 1
R1 C1
Q. 76 For the circuit shown in Fig. the diode D is ideal. The power dissipated by the
300 W resistor is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 77 Fig (a) shows a Schwitt trigger circuit and Fig (b) the corresponding hysteresis
characteristics. The values of VTL and VTH are
Q. 78 An integrator circuit is shown in Fig. The op-amp is of type 741 and has an input
offset current ios of 1 mA and R is 1 MW. If the input Vi is a 1 kHz square wave of
1 V peak to peak, the output V0 , under steady state condition, will be.
Q. 79 The output of an op-amp whose input is a 2.5 MHz square wave is shown in Fig.
The slew rate of the op-amp is
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 80 The op-amp and the 1 mA current source in the circuit of Fig. are ideal. The
output of the op-amp is
Q. 81 A forward-biased silicon diode when carry negligible current, has a voltage drop
of 0.64 V. When the current is 1 A it dissipates 1 W. The ON-resistance of the
diode is
(A) 0.36 W (B) 0.64 W
(C) 0.72 W (D) 1.0 W
Q. 83 The op-amp used in the inverting amplifier shown in Fig. has an equivalent input
offset voltage Vios of 5 mV. The output offset voltage is.
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 84 In the circuit shown in Fig. the op-amps used are ideal. The output V0 is
Q. 86 The circuit shown in Fig. is that of a waveform generator. Assuming ideal devices
and !12 V supply, the output V0 is a
Q. 87 The 5 V Zener diode in figure is ideal and the ammeter (A), of full-scale 1 mA,
has an internal resistance of 100W. The circuit shown, with terminal 1 positive,
functions as a
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
Q. 88 A unity gain buffer amplifier has a bandwidth of 1 MHz . The output voltage of
the amplifier for an input of 2 V sinusoid of frequency 1 MHz will be
(A) 2 V (B) 2 2 V
(C) 2 V (D) 4 V
2 2
Q. 89 An amplifier of gain 10, with a gain-bandwidth product of 1 MHz and slew rate
of 0.1 V/ms is fed with a 10 kHz symmetrical square wave of ! 1 V amplitude. Its
output will be
(A) ! 10 V amplitude square wave (B) ! 2.5 V amplitude square wave
(C) ! 10 V amplitude triangular wave (D) ! 2.5 V amplitude triangular wave
Q. 90 A sample and hold circuit has two buffers, one at the input and the other at the
output. The primary requirements for the buffers are
(A) The input buffer should have high slew rate and the output buffer should
have low bias current
(B) the input buffer should have low bias current and the output buffer should
have high slew rate
(C) both the buffers should have low bias currents
(D) both the buffers should have high slew rate
Q. 91 A twisted pair of wires is used for connecting the signal source with the
instrumentation amplifier, as it helps reducing
(A) the effect of external interference
(B) the error due to bias currents in the amplifier
(C) the loading of the source by the amplifier
(D) the common mode voltage
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
(A) 0 mV (B) 2 mV
(C) 11 mV (D) 22 mV
Q. 94 An op-amp with a slew rate of 1 mVs has been used to build an amplifier of gain
+ 10 . If the input to the amplifier is a sinusoidal voltage with peak amplitude of
1 V , the maximum allowable frequency of the input signal for undistorted output
is
(A) 830 Hz (B) 15.92 kHz
(C) 31.84 kHz (D) 1.0 MHz
Q. 95 For a sinusoidal input of 50 V amplitude, the circuit shown in figure can be used
as
Q. 96 In the DC millivoltmeter circuit shown in figure, the input voltage for full scale
deflection is
(A) 10 V (B) 1 V
(C) 100 mV (D) 10 mV
**********
mywbut.com
GATE SOLVED PAPER - IN ANALOG ELECTRONICS
ANSWER KEY
ANALOG ELECTRONICS
1 2 3 4 5 6 7 8 9 10
(D) (D) (B) (A) (C) (C) (C) (A) (B) (A)
11 12 13 14 15 16 17 18 19 20
(A) (B) (D) (C) (B) (A) (B) (A) (B) (D)
21 22 23 24 25 26 27 28 29 30
(C) (A) (C) (C) (B) (A) (B) (D) (D) (B)
31 32 33 34 35 36 37 38 39 40
(C) (B) (A) (D) (D) (A) (B) (C) (B) (C)
41 42 43 44 45 46 47 48 49 50
(D) (B) (B) (C) (B) (D) (B) (D) (C) (A)
51 52 53 54 55 56 57 58 59 60
(A) (B) (C) (C) (C) (B) (A) (A) (D) (C)
61 62 63 64 65 66 67 68 69 70
(B) (D) (B) (D) (D) (C) (D) (A) (B) (B)
71 72 73 74 75 76 77 78 79 80
(A) (A) (B) (D) (A) (C) (D) (D) (D) (B)
81 82 83 84 85 86 87 88 89 90
(A) (B) (C) (B) (D) (C) (C) (C) (D) (A)
91 92 93 94 95 96 97
(A) (C) (B) (B) (B) (D) (A)
mywbut.com