This document contains a table summarizing configuration variables for an Avenger chip. It lists the name, description, default value, constraints, and whether randomization is required for each variable. The variables control features like interrupt enables, masks, and test mux controls. Randomizing the values aims to achieve uniform distributions during testing to thoroughly evaluate the chip's behavior.
(Huebner International Series On Risk, Insurance and Economic Security) Klugman, S.a.-Bayesian Statistics in Actuarial Science - With Emphasis On Credibility. 15-Kluwer Academic Publishers (1992)
This document contains a table summarizing configuration variables for an Avenger chip. It lists the name, description, default value, constraints, and whether randomization is required for each variable. The variables control features like interrupt enables, masks, and test mux controls. Randomizing the values aims to achieve uniform distributions during testing to thoroughly evaluate the chip's behavior.
This document contains a table summarizing configuration variables for an Avenger chip. It lists the name, description, default value, constraints, and whether randomization is required for each variable. The variables control features like interrupt enables, masks, and test mux controls. Randomizing the values aims to achieve uniform distributions during testing to thoroughly evaluate the chip's behavior.
This document contains a table summarizing configuration variables for an Avenger chip. It lists the name, description, default value, constraints, and whether randomization is required for each variable. The variables control features like interrupt enables, masks, and test mux controls. Randomizing the values aims to achieve uniform distributions during testing to thoroughly evaluate the chip's behavior.
Register Config variable Description Defaul Max Constraint Comments Randomiz
Name Name t value weight & (based on ation
/ reset distribution Avenger1) required value (for Avenger2) (Y/N) IntEnable ~ ~ By default we have set all bit its depends on the interrupt status IntEnable serdesctl_IntEn serdesctl_IntEn 0 {1:=99,0:=1} Y IntEnable PswCntrl_h_IntEn PswCntrl_h_IntEn 0 {1:=99,0:=1} Y IntEnable PswCntrl_l_IntEn PswCntrl_l_IntEn 0 {1:=99,0:=1} Y IntEnable Reserved1 Reserved 0 {1:=99,0:=1} Y IntEnable ProtCntrl_IntEn ProtCntrl_IntEn 0 {1:=99,0:=1} Y IntEnable M0toSysDoorBell_In M0toSysDoorBell_Int 0 {1:=99,0:=1} Y tEn En IntEnable Phy_IntEn Phy_IntEn 0 {1:=99,0:=1} Y IntEnable AXI2APB_IntEn AXI2APB_IntEn 0 Y IntEnable1 ~ ~ {1:=99,0:=1} IntEnable1 serdesctl_IntEn Each bit in this 0 {1:=99,0:=1} Y register is the enable for the corresponding bit in the IntStatus1 register. If set to 1 IntEnable1 Phy_IntEn Each bit in this 0 {1:=99,0:=1} Y register is the enable for the corresponding bit in the IntStatus1 register. If set to 1 IntCritMask ~ ~ We need Random to randomize this values or all set uniform distributio n? IntCritMask PswCntrl_h_IntCrit PswCntrl_h_IntCrit 0 Y IntCritMask PswCntrl_l_IntCrit PswCntrl_l_IntCrit 0 Y IntCritMask Reserved1 Reserved 0 Y IntCritMask serdesctl_IntCrit serdesctl_IntCrit 0 Y IntCritMask ProtCntrl_IntCrit ProtCntrl_IntCrit 0 Y IntCritMask M0toSysDoorBell_In M0toSysDoorBell_Int 0 Y tCrit Crit IntCritMask Reserved2 Reserved 0 Y IntCritMask AXI2APB_IntCrit AXI2APB_IntCrit 0 Y IntHighMask ~ ~ We need Random to randomize this values or all set uniform distributio n? IntHighMask PswCntrl_h_IntHigh PswCntrl_h_IntHigh 0 Y IntHighMask PswCntrl_l_IntHigh PswCntrl_l_IntHigh 0 Y IntHighMask Reserved1 Reserved 0 Y IntHighMask serdesctl_IntHigh serdesctl_IntHigh 0 Y IntHighMask ProtCntrl_IntHigh ProtCntrl_IntHigh 0 Y IntHighMask M0toSysDoorBell_In M0toSysDoorBell_Int 0 Y tHigh High IntHighMask Reserved2 Reserved 0 Y IntHighMask AXI2APB_IntHigh AXI2APB_IntHigh 0 Y IntLowMask ~ ~ We need Random to randomize this values or all set uniform distributio n? IntLowMask PswCntrl_h_IntLow PswCntrl_h_IntLow 0 Y IntLowMask PswCntrl_l_IntLow PswCntrl_l_IntLow 0 Y IntLowMask M0toSysDoorBell_In M0toSysDoorBell_Int 0 Y tLow Low IntLowMask serdesctl_IntLow serdesctl_IntLow 0 Y IntLowMask ProtCntrl_IntLow ProtCntrl_IntLow 0 Y IntLowMask Reserved1 Reserved 0 Y IntLowMask Reserved2 Reserved 0 Y IntLowMask AXI2APB_IntLow AXI2APB_IntLow 0 Y IntM0Mask ~ ~ We need Random to randomize this values or all set uniform distributio n? IntM0Mask PswCntrl_h_IntM0 PswCntrl_h_IntM0 0 Y IntM0Mask PswCntrl_l_IntM0 PswCntrl_l_IntM0 0 Y IntM0Mask Reserved1 Reserved 0 Y IntM0Mask serdesctl_IntM0 serdesctl_IntM0 0 Y IntM0Mask ProtCntrl_IntM0 ProtCntrl_IntM0 0 Y IntM0Mask Reserved2 Reserved 0 Y IntM0Mask AXI2APB_IntM0 AXI2APB_IntM0 0 Y TMuxCtrl ~ ~ Uniform randomiza tion of testmux due normal function wont effect TMuxCtrl Lane_7 Lane 7 7 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_6 Lane 6 6 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_5 Lane 5 5 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_4 Lane 4 4 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_3 Lane 3 3 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_2 Lane 2 2 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_1 Lane 1 1 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxCtrl Lane_0 Lane 0 0 {3’h0:=25,3’h1:=25, Y 3’h2:=25,3’h3:=25} TMuxByteSel0_ ~ ~ lo TMuxByteSel0_ Lane_3 The values in this 0 {[8’h0:8’hF]:=50, Y lo register select the [8’hF:8’hFF]:=50} CSW_CIB test mux 0 input for each byte lane: See the respective block descriptions for lower level testmux programming. 00 = Signature 01 = TMuxOutAPB0 02 = TMuxOutAPB1 03 = TMuxOutTrimode 04 = TMuxOutPhy0 05 = TMuxOutPhy1 06 = TMuxOutPhy2 07 = TMuxOutPhy3 08 = TMuxOutPhy4 09 = TMuxOutPhy5 0a = TMuxOutPhy6 0b = TMuxOutPhy7 0c = TMuxOutPhy8 0d = TMuxOutPhy9 0e = TMuxOutPhy10 0f = TMuxOutPhy11 10 = TMuxOutPhy12 11 = TMuxOutPhy13 12= TMuxOutPhy14 13 = TMuxOutPhy15 14 = AXS0_TmuxTP0 15 = AXS0_TmuxTP1 16 = AXS0_TmuxTP2 17 = AXS0_TmuxTP3 18 = {2{TmuxInput_regist er}} TMuxByteSel0_ Lane_2 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel0_ Lane_1 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel0_ Lane_0 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel0_ ~ ~ hi TMuxByteSel0_ Lane_7 The values in this 0 {[8’h0:8’hF]:=50, Y hi register select the [8’hF:8’hFF]:=50} CSW_CIB test mux 0 input for each byte lane: See the respective block descriptions for lower level testmux programming. 00 = Signature 01 = TMuxOutAPB0 02 = TMuxOutAPB1 03 = TMuxOutTrimode 04 = TMuxOutPhy0 05 = TMuxOutPhy1 06 = TMuxOutPhy2 07 = TMuxOutPhy3 08 = TMuxOutPhy4 09 = TMuxOutPhy5 0a = TMuxOutPhy6 0b = TMuxOutPhy7 0c = TMuxOutPhy8 0d = TMuxOutPhy9 0e = TMuxOutPhy10 0f = TMuxOutPhy11 10 = TMuxOutPhy12 11 = TMuxOutPhy13 12= TMuxOutPhy14 13 = TMuxOutPhy15 14 = AXS0_TmuxTP0 15 = AXS0_TmuxTP1 16 = AXS0_TmuxTP2 17 = AXS0_TmuxTP3 18 = {2{TmuxInput_regist er}} TMuxByteSel0_ Lane_6 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TMuxByteSel0_ Lane_5 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TMuxByteSel0_ Lane_4 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TrimodeTMuxC ~ ~ trl TrimodeTMuxC Lane_7 Lane 7 7 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_6 Lane 6 6 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_5 Lane 5 5 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_4 Lane 4 4 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_3 Lane 3 3 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_2 Lane 2 2 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_1 Lane 1 1 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxC Lane_0 Lane 0 0 {3’h0:=25,3’h1:=25, Y trl 3’h2:=25,3’h3:=25} TrimodeTMuxB ~ ~ yteSel TrimodeTMuxB Lane_7 The values in this 0 {3’h0:=25,3’h1:=25, Y yteSel register select the 3’h2:=25,3’h3:=25} TrimodeSerdes testmux input for each byte lane: See the respective block descriptions for lower level testmux programming. The blocks are selected as follows: 4'h0 - Signature 4'h1 - TMuxOutAVSerDes 4'h2 - {2{o_ccr_ext_prb_ou t}} TrimodeTMuxB Lane_6 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_5 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_4 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_3 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_2 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_1 See description for 0 {3’h0:=25,3’h1:=25, Y yteSel Lane 7 above 3’h2:=25,3’h3:=25} TrimodeTMuxB Lane_0 See description for 0 yteSel Lane 7 above CIBCtrl ~ ~ CIBCtrl APB1RdParDis Set to disable AXI 0 {1:=50,0:=50} We can Y RPARVALID randomize indication for APB1 this parity valid CIBCtrl APB0RdParDis Set to disable AXI 0 {1:=50,0:=50} Y RPARVALID indication for APB0 {1:=50,0:=50} {1:=50 {1:=50,0:=50} ,0:=50 } CIBCtrl SasClkEn These bits control 0 Do we N the ClkGate for each need to SAS Channel (SasPhy randomize & SAS serdesctl). this Setting a bit enables sasclken is the SasClk for the necessary respective channel. to register write Broadcast_Cont APB_PSel_mask These bits control 0 +plusarg N rol which channels are written during a register write broadcast operation. Setting a bit enables the PSel for the respective channel. M0_Channel_M ~ ~ ask M0_Channel_M M0_1_Channel_Ma These bits control 0 Only need to toggle y ask sk which channel each bit, not check specific interrupts all possible values. are routed to M0_1 M0_Channel_M M0_0_Channel_Ma These bits control 0000F Always set to y ask sk which channel FFF inverse of above specific interrupts register. are routed to M0_0 TMuxByteSel1_ ~ ~ Separate lo tmux test TMuxByteSel1_ Lane_3 The values in this 0 {[8’h0:8’hF]:=50, Y lo register select the [8’hF:8’hFF]:=50} CSW_CIB test mux 1 input for each byte lane: See the respective block descriptions for lower level testmux programming. 00 = Signature 01 = TMuxOutAPB0 02 = TMuxOutAPB1 03 = TMuxOutTrimode 04 = TMuxOutPhy0 05 = TMuxOutPhy1 06 = TMuxOutPhy2 07 = TMuxOutPhy3 08 = TMuxOutPhy4 09 = TMuxOutPhy5 0a = TMuxOutPhy6 0b = TMuxOutPhy7 0c = TMuxOutPhy8 0d = TMuxOutPhy9 0e = TMuxOutPhy10 0f = TMuxOutPhy11 10 = TMuxOutPhy12 11 = TMuxOutPhy13 12= TMuxOutPhy14 13 = TMuxOutPhy15 14 = AXS0_TmuxTP0 15 = AXS0_TmuxTP1 16 = AXS0_TmuxTP2 17 = AXS0_TmuxTP3 18 = {2{TmuxInput_regist er}} TMuxByteSel1_ Lane_2 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel1_ Lane_1 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel1_ Lane_0 See description for 0 {[8’h0:8’hF]:=50, Y lo Lane 3 above [8’hF:8’hFF]:=50} TMuxByteSel1_ ~ ~ hi TMuxByteSel1_ Lane_7 The values in this 0 {[8’h0:8’hF]:=50, Y hi register select the [8’hF:8’hFF]:=50} CSW_CIB test mux 1 input for each byte lane: See the respective block descriptions for lower level testmux programming. 00 = Signature 01 = TMuxOutAPB0 02 = TMuxOutAPB1 03 = TMuxOutTrimode 04 = TMuxOutPhy0 05 = TMuxOutPhy1 06 = TMuxOutPhy2 07 = TMuxOutPhy3 08 = TMuxOutPhy4 09 = TMuxOutPhy5 0a = TMuxOutPhy6 0b = TMuxOutPhy7 0c = TMuxOutPhy8 0d = TMuxOutPhy9 0e = TMuxOutPhy10 0f = TMuxOutPhy11 10 = TMuxOutPhy12 11 = TMuxOutPhy13 12= TMuxOutPhy14 13 = TMuxOutPhy15 14 = AXS0_TmuxTP0 15 = AXS0_TmuxTP1 16 = AXS0_TmuxTP2 17 = AXS0_TmuxTP3 18 = {2{TmuxInput_regist er}} TMuxByteSel1_ Lane_6 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TMuxByteSel1_ Lane_5 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TMuxByteSel1_ Lane_4 See description for 0 {[8’h0:8’hF]:=50, Y hi Lane 7 above [8’hF:8’hFF]:=50} TmuxInput ~ ~ TmuxInput TmuxInput These bits are routed 0 Exact value Y to the TMux as unimportant; just TmuxInput_register check for toggle on every bit.
(Huebner International Series On Risk, Insurance and Economic Security) Klugman, S.a.-Bayesian Statistics in Actuarial Science - With Emphasis On Credibility. 15-Kluwer Academic Publishers (1992)