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Noise Analysis in Switched Capacitor Amplifier Based Sensors

Conference Paper · September 2017

DOI: 10.1109/NGCAS.2017.64

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 2017 First New Generation of CAS

Noise Analysis in Switched Capacitor Amplifier

Based Sensors
Mohammad Ali Vosoughi1 , Hamdi Torun 2 , and Gunhan Dundar2
1
Department of Electrical Engineering, University of South Florida
2
Department of Electrical and Electronics Engineering, Bogazici University

Abstract—Noise analysis of switched capacitor amplifier-based S 2s

sensor interface circuit has been presented in this paper. It is
shown that the main noise of the circuit has been generated by
the amplifier. Even though specification of the switches effects
the efficiency of the circuit, their influence on the output referred
noise is trivial and can be ignored. The circuit has been simulated
with ELDO in UMC 130nm technology. Approximate expressions C 1s C 2s V o1
for the output referred thermal noises are derived and the IB
accuracy of the noise modeling is verified by the simulations. V1 −

Index Terms—Switched-Capacitor, Sensor Interface, Capaci- +

tive Sensor, kT/C noise.
C 1r C 2r V o2
S1
I. I NTRODUCTION
Discrete time sensing techniques offer numerous advantages
over their continuous time (CT) counterparts especially for
power consumption of the circuit; however, their noise perfor- S 2r
mance is worse than CT sensor interface circuits [1]. Switched
Fig. 1: Swiched capacitor interface circuit.
capacitor (SC) circuits are viable choice for many applica-
tions due to their advantages in CMOS integration. Thermal
noise represents a major limitation on the performance of
most electronic precision circuits. It is specifically crucial Phase 1
in switched capacitor circuits, such as the SC filters, sigma- Phase 2
1,2
delta converters, SC amplifiers and SC precision circuits. In
the switching mixed-signal CMOS integrated circuits, due 1,0
to aliasing the power spectral density of the thermal noise
increases. Numerical analysis of noise in SC is sophisticated 0,8
Clock (V)

and exhausting. In addition, electronic design software such

0,6
as Eldo Mentor are unable to simulate the switching noise.
Schreier et.al. have provided a guideline on how to model 0,4
the thermal noise in SC circuits [2]. Also they have described
a practical procedure in the same paper for design based 0,2

on the estimated noise. To authors knowledge, there is no 0,0

work analyzing the thermal noise in the switched capacitor 120 140 160 180 200 220 240

amplifier-based interface circuit. Also, Schreier et.al. do not Time (us)

consider the intensified effect of amplifier noise on the output

referred noise.
The modeling of the investigated SC interface circuit has
been presented in II. In section III the noise of the circuit has
been modeled for different phases. Total noise and optimal
operating point has been analyzed in section IV. Finally,
simulation results has been presented in section V followed
by the conclusion.
II. O PERATION OF THE CIRCUIT
Figure 1 shows the configuration of the circuit. In Figure 2
Fig. 2: Non-overlapping clocks.
the clocks for the Φ1 and Φ2 has been shown.
During Φ1 (Φ1 = 1) both C1s and C1r capacitors are
charged through IB to Qs = C1s (V1 − Vi− ) and Qr =
C1r (V1 − Vi+ ). Assuming C2r = C2s = C2 , C1r = Cr and
C1s = Cs , in the second phase, the charge is transferred to
C2 and generates a voltage [3]

978-1-5090-6447-2/17 $31.00 © 2017 IEEE 221

249
DOI 10.1109/NGCAS.2017.64
 Cs (V1 − Vi− ) Cr (V1 − Vi+ ) Vdd
Vo+ = , Vo− = (1a)
C2 C2
M13 M5 M6

Qs − Q r (Cs − Cr )(V1 − Vi )
ΔVout = Vo+ − Vo− = =
C2 C2
(1b)
By assuming ΔC = Cs − Cr and Vin = (V1 − Vi ) we may Vin+ M1 M2 Vin- M7 M8
rewrite (1) in the following form:
Vin
ΔVout = ΔC (2) Vo+ Vo-
C2
Equation (2) implies that the output voltage linearly varies
with the capacitance of the sensor. In the next section, noise
M9 M10
analysis of the circuit will be discussed.
III. M ODELING
The main noise sources are flicker and thermal noises of
the amplifier and thermal noises of the switches. Flicker noise M3 M4 M11 M12
depends on the surface of the CMOS transistor and can be
reduced by larger input stages [2], [4]. In addition, due to low
Vss
frequency behavior of the flicker noise and for high precision
Fig. 3: Folded Cascode OTA with PMOS input stage. For simplification CMFB
circuits, the techniques such as correlated double sampling is not shown.
or chopper stabilization [4] could be used. Therefore, thermal
noise due to opamp and kT /C noise from switched-capacitors
are the major sources of the noise in these circuits. The noise this ratio is not as small as the calculated ratio. Assuming
gm3/gm1  0.5 equivalent power spectral density (PSD) of
in each phase is the sum of the switching noise in that phase
and the noise folded from the previous phase. The noise value input referred thermal noise of OTA becomes:
should be separately calculated for each phase. 2 16kT
V̄neq,op,in  . (5)
Folded cascode operational transconductance amplifier 3gm1
(OTA) with PMOS input stage is used as shown in Figure 3 [5]. 2
Assuming V̄noise,in is one arbitrary input referred noise
2
Input referred noise of M1 is equal to V̄n1 = 4kT (2/(3gm1 )). and opamp is compensated properly in the frequency range
¯2
The thermal noise of M3 is In3 = ( /3)kT gm3 . Therefore,
8
of interest (loopgain ≥ 1), the closed-loop transfer function
the noise due to M3 referred to the input of the OTA can be can be approximated by the one pole expression:
2
written as V̄n3 = 8kT gm3/(3gm1
2
) . Similarly, the contribution of
2 Vout G0
M12 to the noise at the input stage is V̄n10 = 4kT gm12/(3gm12
). H(s) = = , (6)
Since M10 is degenerated, its corresponding noise contribution Vin+ 1 + sτ
is reduced and could be neglected. Similar noise values come where G0 is determined by the FB factor of the stage and
from M2,4,11 . Adding noises due to M1,3,12 , the equivalent by the dc gain of the opamp stage A0 , and τ is settling time
input referred thermal noise of the op amp at each of the input constant. Assuming A0 >> 1/β , G0 is equal to:
nodes is derived as: 1 1 C1
G0 =  =1+ , (7)
2 8 kT gm3 + gm12 β + A10 β C2
V̄neq,op,in = (1 + )nf , (3)
3 gm1 gm1 and τ is given by C0/(βgm1 ) , where C0 = CL + C1 C2/(C1 + C2 )
where noise factor nf depends on architecture.The current for folded cascode structure. The PSD of the input white noise
passing through M3 is 20% less than M12 , implying gm12 = is shaped by the first order low-pass behavior of equation
1.25gm3 . Substituting these results in (3) we derive a simpler (6) and it is transferred to the output node. The mean square
expression: (MS) value of the noise at the output could be calculated by
8 kT gm3 + 1.25gm3 integrating the shaped PSD of the noise over all the frequency
2
V̄neq,op,in = (1 + )nf range from zero to infinity:
3 gm1 gm1  ∞
(4)   2
=
8 kT
(1 + 2.25
gm3
)nf .
2
V̄noise,out = 2
V̄neq,op,in H(j2πf )2 df = 16kT nf G0
3 gm1 gm1 0 3gm1 4τ
(8)
(4) implies that if M1 is much larger than M3 then gm3/gm1 The output of unity-gain FB could be achieved simply by
will be minimized and therefore noise of the OTA will be setting β = 1(C1 = 0) in (8):
reduced. However, in reality even with the large input stage,
2 4kT nf
V̄noise,out = (9)
3gm1 τ

250
222
 Fig. 4: Noise model circuit when Φ1 is high.

τ is related to configuration of the circuit in each phase1 .

Fig. 5: Noise model circuit when Φ2 is high.
The approach above could be generalized and extended to
switching noise. When thermal noise with a white spectrum
Sv (f ) is processed through a first order low pass filter (LPF),
Therefore, the total noise during the phase I is :
the result is not white noise any more and its PSD has a
f3dB = 1/2πτ and a MS value: 2 4kT nf Cs Cr
V̄n,tot1 = ( + 2)
3(1 + gm1 Ron ) C22 C2
2 G20 Sv √ √ (14)
V̄noise = (10) kT Cs Cr 2
4τ + 1 | − |
1 + gm1 Ron C2 C2
Figure 4 depicts the circuit noise model during phase I.
Input referred noise power due to the switch S1 is equal to During phase II, S1 is open and S2s and S2r are conducting,
4kT Ron . Time constant of Cs during phase I is τ = (1/gm1 + as shown in Figure 5.
Ron )Cs and similarly for Cr . Due to low-pass behavior of The noise due to switches S2s and S2r can be mod-
transfer function of the opamp, the white noise is shaped by eled as current sources entering the input whose value is
f3dB = 1/(2πτ ). Using the brick-wall filter approximation, I¯nR
2
on
= 4kT /Ron . The equivalent impedance at the input node
the integrated noise from frequencies zero to infinity due to is approximately 1/gm1 ; therefore, equivalent input referred
switch S1 can be derived: noise due to switching in phase II is 4kT /gm1 2
Ron . The time
constant of Cs and Cr during phase II is τ = Cs/gm1 and a
√√ similar term exists for Cr . As result, the noise due to switches
2 kT Cs Cr 2
V̄sw,p1 = | − | (11) in this phase can be obtained as:
(1 + gm11Ron ) C2 C2
2 kT 1 1
Equation (11) implies that the noise due to phase I is canceled V̄sw,p2 = ( + ) (15)
gm1 Ron Cs Cr
out completely if capacitor values are symmetric at both
sides(i.e. Cs = Cr ). For asymmetric values of capacitors, noise consequently, output referred noise of the opamp during phase
voltages are subtracted, since the noises are correlated for both II, whose noise is transferred to C2 in next phase, can be
halves. obtained as:
For the thermal noise of the opamp, since noise sources 2 4kT nf Cs Cr
V̄op,p2 = ( 2 + 2) (16)
are uncorrelated, they appear independently at the differential 3 C2 C2
output. Using (5), output referred noise of the opamp during
Therefore, the total noise during phase II is:
phase I is given by:
2 4kT nf Cs + Cr kT 1 1
4kT nf 1 1 V̄n,tot2 = ( )+ ( + ) (17)
2
V̄op,p1 = ( + ) (12) 3 C22 gm1 Ron Cs Cr
3(1 + gm1 Ron ) Cs Cr
IV. T OTAL N OISE AND O PTIMAL O PERATING P OINT
During phase I, the charge noise on Cr and Cs transfers to the
two C2 capacitors; however, during phase II, both ends of C2 Total noise is equal to the sum of noises in phase I and
are short circuited and no charge noise appears on C2 which II. Summing expressions (14) and (17), the total uncorrelated
can be derived as: noise of the interface circuit can be derived as:
4kT nf Cs Cr 2 4kT (Cs + Cr )nf 4kT nf Cs + C r
2
V̄op,p1 = ( + 2) (13) V̄n,tot = + ( )
3(1 + gm1 Ron ) C22 C2 3C22 3(1 + gm1 Ron ) C22
√ √
kT Cs Cr 2 kT 1 1
+ | − | + ( + )
1 For assumption β ∼ 1 minimum noise can be achieved. β is always
= 1 + gm11Ron C2 C2 gm1 Ron Cs Cr
greater than 1 based on FB path gain.
(18)

251
223
 Assuming Cs = Cr = C1 and defining x = gm1 Ron , the Thermal of switches
Thermal of OTA
structure will be an amplifier with gain C1 /C2 and equation 10n
Flicker+Thermal of all devices
(18) can be simplified as:
1n
2 2kT 4 4 1 8kT C1
V̄n,tot = ( + + )+ (19)
C1 3 1 + x x 3(1 + x) C22

PSD (sq(V)/Hz)
( V / Hz )
100p

(19) implies that noise is reduced for large x. The interesting

2
result is that for SC amplifier, most of the noise is due to 10p
opamp and its effect is more significant if the noise factor is
added. By taking smaller switches and increasing tail current 1p
of the opamp, the optimized operation point can be realized.
Another advantage for the smaller switches is due to their 100f
smaller capacitance. Small capacitance of the switches require
10k 100k
less power to be driven by the clocks and improves the Frequency (Hertz)
efficiency of the circuit. However, the voltage drop over the
larger resistance of transistors is another problem, independent Fig. 6
of noise issue.
Fig. 7: Flicker and Thermal of all components, Only Thermal and Only
V. S IMULATION R ESULTS Switches’ Thermal . Integrated noise for SC-emulated resistor (fully switched
capacitor) is 56.56nV . Cs = 300f
For simulation, U M C130nm technology with ELDO is
used. To minimize the effect of harmonics on the extracted
noise voltage, IB has been set to 25nA. The size of NMOS Flicker Noise
switches is such that Ron = 8kΩ and gm1 = 2.4mS. This will Thermal Switches
Thermal OTA
minimize output referred noise through maximizing gm1 Ron . 84,24%
Capacitors are C2 = Cr = 300f F . Calculated and simulated
values for different Cs are shown in Table I. Integrated noise
over all frequencies gives the total noise of the circuit.
Figure 6 shows the PSD of output noise for three cases:
noiseless OTA and flicker noise turned off, thermal noise of
the opamp is added to the simulation, and flicker noise is also 8,64%
7,12%
added. Effect of different noises coming from switches and
OTA has been shown in Figure 8. Therefore, the main source Fig. 8: Different sources of the output referred noise in psudo-differential
design with Cs = 200f F
of noise OTA by 84.24% of overall noise.
Cs Noise Type Noise Source Simulations Calculated
100f Thermal Switches 4.65nV 2 5.34nV 2 switching circuit. The capacitance of the switch directly effects
100f Thermal Switches,OTA 46.31nV 2 39.57nV 2 the dynamic power consumption. To wrap-up, the design of the
100f Thermal,Flicker Switches,OTA 52.33nV 2 NA SC amplifier and amplifier-based interface circuit starts with
200f Thermal Switches 3.79nV 2 2.26nV 2
design of a low noise OTA and ends with the optimization of
200f Thermal Switches,OTA 48.62nV 2 45.08nV 2
200f Thermal,Flicker Switches,OTA 53.22nV 2 NA the switches.
300f Thermal Switches 3.53nV 2 1.44nV 2
300f Thermal Switches,OTA 52.35nV 2 52.80nV 2 R EFERENCES
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sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS
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722-730, 2004
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