January.

2012

MIP521AMS
Application Note

Power & Optical Devices Business Unit, Semiconductor Business Group

Industrial Devices Company, Panasonic Corporation

－P1－
Contents & 1-(1) Determination of power supply spec January. 2012

≪Contents≫
(1) Clarification of power supply spec (Input voltage range, Output voltage, Output current etc,,,)
(2) Confirmation of MIP521A’s and your power supply’s specification ・・・・・・・・・・・・・・・・・・・・・・・・・・P3
(3) Transformer design ・・・・・・・・・・・・・・・・・・・・・・・・・・P4
(4) Design of circuit diagram and circuit constant ・・・・・・・・・・・・・・・・・・・・・・・・・・P5
(5) Over Load Protection (OLP) ・・・・・・・・・・・・・・・・・・・・・・・・・・P11
(6) PCB pattern design ・・・・・・・・・・・・・・・・・・・・・・・・・・P12
(7) Picking up problems and Evaluation boards according to the check list ・・・・・・・・・・・・・・・・・・・・・・・・・・P15

1- (1) Clarification of power supply spec

OVP ： Latch off
Input voltage range (AC/ DC)： (V) OLP ： Timer intermittent oscillation
Output voltage / Current OTP ： Latch off
(No.1) Voltage (Accuracy)： (± )(V) / Current： (A)
(No.2) Voltage (Accuracy)： (± )(V) / Current： (A)
(No.3) Voltage (Accuracy)： (± )(V) / Current： (A)
(No.4) Voltage (Accuracy)： (± )(V) / Current： (A) In case of multiple output,
(No.5) Voltage (Accuracy)： (± )(V) / Current： (A) Please Input these parameter.

－P2－
1- (2) Confirmation of MIP521A’s specification and a standard circuit January. 2012

MIP521AMS’s specification and feature

Product Output power (Open frame) Feature

Package
name AC85-264V AC176‐264V VDSS ILIMIT Ron fosc
MIP521A - 10W - 19W 800V 0.50A 9.5ohm 65kHz DIP7-A1

Circuit example of MIP521A CY

2200pF
250VAC
C201
CSB RSB D201 2200u
CIN 2200p 100k
450V (SBD) 25V
1KV 2W 60V, 5A Low ESR 5.0V/ 2.0A
LINE 33uF

FIN +
+
250VAC
1A

NTRL VR CX LIN
470V 275V 19mH Rout1 RETURN
DSB
0.1u 1A DIN (FRD) DVCC 10k
600V Rs Rb
700V 300V 1k 1.8k
1A 1.0A 0.3A

T301 PC1 Rout2

+ CVCC 0
22u
D VCC 50V
CKR
0.1uF RKR
VIN 39k

IC1 RFB
MIP521A FB 3.3k

S VDD ROL ICreg

10k TA76431S
Rref
PC1 10k
CVDD COL
0.1u 0.22u

－P3－
1- (3) Transformer design January. 2012

MIP521A Transformer design

About transformer design of MIP521A, please refer to 'PWM transformer calculation sheet' which we prepared.
We would like you to refer to that sheet at the calculation of transformer’s parameters. And I would like to ask you to confirm the following points
about the transformer design for MIP521A.
(A) Keep drain current peak (IDP) lower than 90% of minimum of ILIMIT. Æ Because output voltage gets down, if IDP reach to ILIMIT.
(B) Set DUTY<50% and KRP>0.5 on at continuous mode. (KRP is explained in the calculation sheet)
(C) We recommend VCC voltage set value (VB in transformer calculation sheet) is 15V.
Æ You should set VCC voltage to be kept over VCC(OFF) at light load or sudden load change from minimum to short.
(Additional notes)
During intermittent oscillation at light-load operation, if the bias winding voltage is too low such that it cannot maintain the bias winding rectified voltage
(VCC voltage), VCC voltage will drop below VCC (OFF). In this scenario, Drain terminal will start to supply current to VCC terminal and the internal circuit,
hence, causing the standby power consumption to increase. Therefore it is required to design the bias winding voltage such that even at light load; the bias
winding voltage is able to maintain VCC voltage. For MIP521A, VCC (OFF) is designed at 10.5V and hence, please take note of the design value of bias
winding voltage for the transformer of this product.
On the other hand, please take note that if the setting of the bias winding voltage is too high, VCC(OV) latch may be activated.

≪ About Winding Structure ≫ P

V
About MIP521AMS, you should care about the arrangement of V S S
the bias winding, because if VCC voltage reaches VCC(OV), S P V
over voltage protection is operated. We recommend the S S
following three ways as standard winding structures. P P P
(1) (2) (3)

Structure Explanation Structure of feature

(1) P-S-V Bias winding (V) regulation is good, and it is the simplest, general structure. Cost cut / The transformer can be miniaturized.
If we compose primary winding (P), secondary winding (S) like sandwich structure,
The combination of P winding and S winding is improved.
In this way, leakage inductance will be small. It has effect to decrease drain voltage ringing Improve efficiency /
(2) P-S-P-S-V
and improve efficiency. Decrease drain voltage ringing
However, because this combination of S winding and V winding is worse than (3),
V winding regulation tends to worse than (3).
By composing sandwich structure V winding and S winding , the combination of V winding
and S winding is good. So, V winding voltage regulation will be good. Bias winding regulation is good.
(3) P-S-V-S-P
And this structure can reduce drain voltage ringing and improve efficiency better than (1).
(However, (2)’s efficiency is better than (3).)

－P4－
1- (4) Design of circuit diagram and circuit constant January. 2012

Design flow of circuit constant determination

Item Design parameter Reference

1) Input (Filter / Rectifier) Filter and input capacitor P6

2) Drain voltage clamp circuit The clamp circuit parts that suppress drain voltage up to that rating P7
3) The circuit around VCC, FB, VDD The parts around MIP521A P8
4) Output rectification and smooth circuit Output rectification parts P9
5) Output filter Output filter which decrease output ripple P9
6) Secondary feedback circuit Output voltage detection parts and parts included in that circuit P10

CY
2200pF
250VAC
Cout
(1) CIN
CSB
2200p
RSB
100k
Dout
(SBD)
2200u Lfil
10mH (5)
450V 16V
1KV 2W 60V, 5A Low ESR 5.0V/ 2.0A
LINE 33uF

FIN
250VAC
+ (2) + + Cfil
470uF
1A 10V

NTRL VR CX LIN
470V 275V 19mH Rout1 RETURN
DSB
0.1u 1A DIN 10k
600V
(FRD)
700V
DVCC
300V (4) Rs
1k
Rb
1.8k
1A 1.0A 0.3A

T301 PC1 Rout2

+ CVCC 0
22u
D VCC 50V
CKR
0.1uF RKR
VIN 39k

IC1 RFB
MIP521A FB 3.3k

S VDD ROL ICreg

10k TA76431S
Rref
PC1 10k
COL
(6)
CVDD
0.1u 0.22u
(3)

－P5－
1- (4) Design of circuit diagram and circuit constant January. 2012

1) Input (Filter / Rectifier)

≪Filter circuit≫
The following shows example of input filter. These input filters are mainly inserted to improve AC line conduction noise up to 1MHz. π type filter is
for low output power, LC type filter is for high output power because π type filter can reduce common mode noise at only low output power.

Recommended output power range ：Up to 8W DIN

LINE F1 CIN1 + CIN2 +
This filter is generally used up to 5W. Because MIP521A has a function of jitter,
πtype we can often use it up to 8W output. LIN
Filter Large LIN and inserting one more inductor on + line could make the filter’s NTRL
effect better. And sometimes it has a profound effect with adding coil in the + line
between CIN1 and CIN2. LIN current rating > input power (W)／input voltage (VAC)／power factor
LIN L recommended value ： 220uH～1000uH
DIN
Recommended output power range ：Higher than 5W
LINE F1 CX CIN +
This is a basic composition of input filter for switching power supplies.
X capacitor CX is effective for normal mode noise and line filter LIN2 is LIN2
LC Filter effective for common mode noise. NTRL
The effect of the filters increases by large inductance value of LIN2
and large capacitance value of CX. LIN2 current rating > input power (W)／input voltage (VAC)／power factor
LIN2 L recommended value ： 10mH～30mH

≪Input smooth part≫

Estimation of capacitor value Check point
Minimum input voltage= AC100V type ⇒Po[W] * 2～3(uF )
Input smooth capacitor When CIN is small, please confirm ON-DUTY does not
Minimum input voltage= AC200V type ⇒Po[W] * 1 ～2(uF )
extend to 50%, because smaller CIN make DC input voltage
CIN Or, you can set that value if you have no problem at lower.
transformer calculation sheet.
【Example of used parts】
Recommended part up to 8W output(Estimation) Our selection of DIN is changed by output power, rating
Bridge diode
：600V/ 0.8A (SIZB60 : Shindengen) current and PKG. You should confirm there is no problem at
DIN Recommended part Over 8W output(Estimation) the temperature of DIN.
：600V/ 1.0A (SINB60 : Shindengen)

－P6－
1- (4) Design of circuit diagram and circuit constant January. 2012

2) Drain voltage clamp circuit (A)

The clamp circuit of drain voltage is the circuit which can suppress the spike voltage (A). Voltage
This spike occurs on IPD turning off. This spike voltage can be changed by CSB or that between
Drain voltage
current flows to ZDSB. After that, that current flows through RSB or ZDSB to DC input. CBS
That current makes loss at that time.
You should adjust this circuit to suppress that spike up to the rating of drain voltage.
DC input
This spike voltage is generated by the leakage inductance of the transformer. voltage

DCR snubber circuit Zener clamp circuit No clamp circuit (Snubber-less)

【Mechanism】 CSB gets charged from the spike voltage.
After that, CSB is discharged by RSB until the next spike
voltage. Thus, the energy is clamped.
Energy consumption by RSB is the loss of this circuit.
Features ・ This circuit causes energy loss. Especially this loss is
noted at light load
・Low cost.
・Better EMI noise (Reduce turn off noise)
【Mechanism】 Zener diode ZDSB clamps the spike voltage.
Clamped voltage is determined by Vz of ZDSB,
and it is “ Vin(DC) + Vz ”.
・Spike voltage does not reach the clamping voltage at light load, so
no energy loss is generated at light load. This circuit can be used
when you need low power consumption at light load.
・The variation of VCC gets larger than DCR snubber.
【Mechanism】 No drain voltage clamping.
・Only power supply with small output & low input
voltage (AC100V) can be applied.
・Because no energy loss by clamp circuit, this circuit
can improve the efficiency at all the load ranges.
・The variation of VCC becomes larger than DCR
snubber.
・Worse EMI noise

RSB: Smaller value has higher clamping capability with
Constant higher energy loss.
value setting CSB: Larger capacitance improve the capability of
clamping when CSB is less than specific value.
ZDSB：P6KE series (Fairchild, Fuji) is recommended. When the ringing just after turn-off becomes higher than
※Power clamper with ZDSB & DSB (FRD/ZD in one package, Shin 700V or lower than 0V, you should reduce the leakage
Dengen) can be also used. inductance or add the clamp circuit.

DC input RSB CSB DC input DC input

ZDSB

Breakdown Voltage:
Circuit over 700V is DSB DSB
configuration recommended
Current rating: D D D
200V/ over RSB(Ω)
(For example 1.0A)
S S S

－P7－
1- (4) Design of circuit diagram and circuit constant January. 2012

3) The circuit around VCC, FB and VDD

Following table shows the explanation of each parts. * About ‘Over Load Protection’ and COL, please refer P11.

Function Method of selection

Reverse voltage VR should be lower than that rating. You could refer to 『VR_D bias MAX』 on the
DVCC transformer calculation sheet. 【Recommended value：200V/ 0.2A】
Rectification and smooth for bias
winding voltage At start-up, light load, sudden load change from minimum to maximum, VCC voltage doesn’t get to
CVCC VCC(OFF). 【Recommended initial value：50V/ 10uF】
It determinates the delay time at over load protection. At start-up, normal operation, sudden load
The delay time of over load protect change from minimum to maximum, VFB should be under VFB(OLP).
COL
operation 【Recommended initial value： over 6V / 0.22uF】

Improve response speed that COL At start-up, sudden load change, VFB should be under VFB(OLP).
ROL
make slower. 【Recommended value：10kohm】

CFB To stabilize FB pin current and wave Stability of operation is no problem at all load condition. 【Recommended value：nothing】

RFB form Stability of operation is no problem at all load condition. 【Recommended value ： 3.3kohm】

To stabilize VDD pin voltage and to

CVDD Stability of operation is no problem at all load condition. 【Recommended value：0.1uF】
maintain pin voltage.

DVCC
[TOPIC ] Waveform stability and response of feedback
ROL, RFB affect operation stability and feedback response. But we don’t recommend you would change
+ those values to improve stability or response. About CFB, you can refer to P10 for stability and response.
D VCC Additionally, CFB sometimes affects intermittent oscillation waveform.
CVCC
T1 Stability [Better ] Stability [Worse ]
MIP521A FB
RFB Response [Slow ] Response [Fast ]
ROL
PC1 1 CFB Large Small
S VDD
CFB 2 ROL Small Large

CVDD
COL 3 RFB Large Small

－P8－
1- (4) Design of circuit diagram and circuit constant January. 2012

4) Output rectification and smooth circuit, 5) Output filter DOUT Lfil

These circuits composes output voltage. + COUT + Cfil

output
Finally, you should confirm the voltage rating of each parts, those temperature
and output voltage ripple by measurement.

Function Method of selection

In generally, SBD(whose voltage rating is 60V) is used at AC100V input type or around 5V output voltage,
FRD(whose voltage rating is 200V) is used.
DOUT
The voltage rating > 『VR_DsecMAX』 in transformer calculation sheet. You could chose DOUT whose current
rating is 3 times of output current at first, and you should deicide that rating by the temperature evaluation, finally.
The Capacitor whose capacitance is about [Output current (A) * 1000uF] could be selected at first.
You should select COUT whose voltage rating is higher than output voltage.
When you confirm that value in detail at designing, you should consider capacitor’s life time and decide capacitor
value by following calculation.
ΔT= ΔTo×( IRIPPLE/ IRIPPLEo)^2
Rectification and smooth of L= Lr × 2^{(To-Ta )/ 10 } × 2^{(ΔTo-ΔT)/ 2 }
secondary winding voltage L must become more than necessary longevity.
ΔTo：Allowable temperature rise of capacitor (from capacitor data sheet)
COUT IRIPPLEo： Allowable ripple current of capacitor (from capacitor data sheet)
IRIPPLE： Current of output ripple (from transformer data sheet)
L ：Estimated life expectancy (hours) in use.
Lr ：In the category upper bound temperature, regulated longevity at the ratings ripple current overlay.(hours)
(from capacitor date sheet)
To ：Category upper bound temperature (deg) of product (from capacitor data sheet)
Ta ：Ambient temperature (deg) in use.
ΔT ：temperature self rise (deg) by impressing ripple current.
Finally, you should deicide that rating by the temperature evaluation.

Lfil Removal filter for output 【Recommended initial value】 Current rating > Output current, L value =10uH
voltage ripple
(If you can arrow ripple voltage,
Cfil 【Recommended initial value】 Voltage rating > Output voltage, Capacitor value= around 20% of COUT
you don’t need this circuit.)

－P9－
1- (4) Design of circuit diagram and circuit constant January. 2012

6) Secondary feedback part

DOUT VOUT
Following table shows the explanation of each parts.
Lfil
+ COUT1 + Cfil
Function Method of selection
The response might be improved on Rs Rb RETURN
reducing it, and the stability might be ROUT
Rs Current control for phot diode improved on enlarging it. PC1
【Recommended value】 1kohm
Rb provide the current IC2 need. CKR RKR
When Rb is too small, power
consumption gets worse at light load.
When Rb is too large, output voltage
Rb Power supply for IC2 regulation is bad.
IC2
【Recommended value】 1.8kohm Rref
(The value can be enlarged when the
output voltage is high.)
The response might be improved on
reducing it, and the stability might be [TOPIC ] Waveform stability and response of feedback
CKR improved on enlarging it. Rs, RKR and CKR can affect operation stability and feedback
【Recommended value】 0.1uF response. If you have the problem about stability or response, you
Parts of feedback adjustment should change Rs, RKR, CFB and CKR.
The response might be improved on
enlarging it, and the stability might be Stability [Better ] Stability [Worse ]
RKR improved on reducing it.
Response [Slow ] Response [Fast ]
【Recommended value】 39kohm
1 Rs Large Small
ROUT ROUT and Rref set output voltage.
You should decide these values, 2 RKR Small Large
Output voltage detect according to a shunt regulator's VR
resistance 3 CFB Large Small
Rref and a following formula.
VOUT×Rref／(ROUT＋Rref)= VR 4 CKR Large Small

－P10－
1- (5) Over Load Protection (OLP) January. 2012

DVCC
Over Load Protection of MIP521A
+
D VCC
CVCC
When output current gets larger, Drain current peak (IDP) gets higher.
T1
1) When IDP reaches to ILIMIT, MIP521A cannot increases output power MIP521A
FB RFB
1) VO gets
and output voltage (VO ) gets down. 3) IFBch down.
ROL
2) When VO gets down, the shunt regulator’s and PC1’s current gets to ZERO. ÆCOL PC1
S VDD
CFB
3) IFBch charges COL, because the minimum of FB current (IFB) is IFBch.
COL
4) And then, when FB voltage (VFB ) gets higher to VFB(OLP), MIP521A CVDD

starts over load protection [Timer intermittent oscillation ].

4) VFB 2) PC1’s current
ÆVFB(OLP) Æ ZERO
In detail, could you refer to “IC explanation material”, please? “START OLP!”

* Start up (AC input turning on ) [ Operation of start up ]

At Start up, VO is zero at first. So, OLP might be activated. VO isn’t correct, VO
if OLP gets activated.
So, You should be careful of it.

VFB(OLP)
¾ You should check VFB doesn’t get up to VFB(OLP) at starting up.
VFB
¾ You should make COL larger, if VFB get up to VFB(OLP).
( Large COL makes VFB rising time slower.)

NG case OK case
OLP gets Start up is
activated. Completed.

－P11－
 1- (6) PCB pattern design January. 2012

PCB layout is one of the most of important points that affects the characteristic of power supply. In particular, that < Explanation of Mark >
decides the stability of operation, EMI, the tolerance of surge. (A)：For improvement of EMI
(B)：For improving the stability of output line
If PCB layout has some problem, we often cannot improve EMC very much by addition of prevention components. (C)：For improving the stability of IPD’s operation
Because Ideal design of PCB makes those effect of EMC prevention the largest, could you design ideal PCB layout (D)：For easing the design of PCB layout
according to following recommended layout and our explanation. (E)：For improvement to the tolerance of EMS
Finally, we prepared the check list of PCV layout. You can check your design by that. (F)：For improving the thermal design
Could you refer to next page in detail, please?

[Recommended layout ] (3) Power loop should be

(4) The parts to prevent surge to AC
input (for example, Y-capacitor,
as short as possible. (A) Varistor, etc) should be located on
Package: DIP7 the pattern from AC input to IPD.(E)
(5) The pattern which is connected
to Y-capacitor should be as short
and wide as possible. (A,E)
Y capacitor
View from component mounted side
(15) Design is considered that the noise of relays at
AC line or lamp don’t affect the operation of IPD.

+
Input capacitor (6) The clamp circuit of
Input Drain terminal should be (13) Secondary rectification
located in power loop and loop should be as short as
JP near the transformer. (A) possible.(A)
-
Transformer

(10) GND of bias

windings rectification (14) Secondary rectification
FB S D loop is separated from loop is separated from
GND of IPD control Pattern after smoothing
(1) Pattern of power loop is separated circuit.(A,C) capacitor. (A,B,D,F)
from pattern before the input IPD
capacitor.(A,D,E,F) (11) Pattern of bias
VIN VDD VCC windings rectification
(2) AC line( in particular, before input loop should be wide and
filter) should not be located near short.(A)
power loop. (A)
Output rectification [Pattern ]
(7) GND of power loop is separated Capacitor
from GND of IPD control circuit.(C) Safety Aqua: Primary
Green: Secondary
distance
(8) The ceramic capacitor between Shadow: GND of
VDD and S must be located near each
Opto
- + control circuit
terminal.(C,E) [Components ]
isolator
Black line: Axial
(16) The length of pattern between (9) The pattern connected to FB
FB and a resistor should be as terminal shouldn’t be near bias Gray line: SMD
short as possible.(C) windings rectification loop or power
loop.(C) (12) Power loop and bias windings rectification loop shouldn’t be
near IPD’s control terminals (VCC, SO, LS, VDD, FB) and the
pattern connected to those terminals. (C)
Output

－P12－
 1- (6) PCB pattern design January. 2012

No. Attention Explanation

The patterns should be separated and made narrow where pattern is connected to the input capacitor, in order to avoid
Pattern of power loop is separated from Pattern before the
1 “Noise at power loop reaching to pattern before the input capacitor“, “Serge and Noise at AC input line reaching to power loop
input capacitor.
and IPD”, “Heat of IPD reaching to the input capacitor”.
AC line (in particular, before input filter) should not be Because Noise at power loop is prevented from reaching to AC line before input filter. If that noise reach to AC line before
2
located near power loop. input filter, input filter (X-capacitor and line filter etc.) will have no effect.
Because high frequency and large current flows through power loop, this loop should be short and the area in that loop
3 Power loop should be as short as possible.
should be small in order to prevent Noise at this loop.
The parts to prevent surge to AC input (for example, Y-
Because that location make those parts (for example, Y-capacitor, Varistor, etc) absorb easily the surge which is entered at
4 capacitor, Varistor, etc) should be located on the pattern
AC input line, before that surge reach to IPD. You should put those on position where that serge current flows.
from AC input to IPD.
The pattern which is connected to Y-capacitor should be as That pattern should be as short and wide as possible in order to noise from primary side to secondary side. This makes
5
short and wide as possible. impedance to Y-capacitor small and effect to suppress primary side noise.
The clamp circuit of Drain terminal should be located in The pattern from the parts of that clamp circuit should be as short as possible, because high frequency and large current
6
power loop and near the transformer. which could source of noise flows on that pattern.
Because GND of power loop is unstable, GND of power loop and GND of IPD control circuit should be separated each other.
GND of power loop is separated from GND of IPD control
7 Also they are connected at just position of IPD’s source terminal. We recommend you don’t connected the parts related to
circuit.
IPD’s control circuit to GND of power loop and make GND of IPD control circuit larger.
The ceramic capacitor between VDD and S must be That makes VDD voltage more stable. Also that makes the stability of operation and the tolerance of surge better.
8
located near each terminal. So, this is very important.
“FB” is the terminal to control the peak of current and it is very sensitive. So that shouldn’t be near bias windings rectification
The pattern connected to FB terminal shouldn’t be near
9 loop or power loop. It is good that the pattern of VCC or GND is located between the pattern of FB terminal and bias windings
bias windings rectification loop or power loop.
rectification loop. Also it is recommended that the pattern between FB terminal and a resistor.
GND of bias windings rectification loop is separated from Because GND of bias windings rectification loop is not stable, GND of IPD control circuit should be separated from that. Also
10
GND of IPD control circuit. we recommend you don’t connected all parts related to IPD’s control circuit to that loop.
Pattern of bias windings rectification loop should be wide About rectification diode of bias winding, the pattern of anode should be short and wide. And that loop to include bias winding,
11
and short. rectification diode and smoothing capacitor should be short, and another part shouldn’t be connected to this loop.
Power loop and bias windings rectification loop shouldn’t
Power loop and bias windings rectification loop is noisy, because those loops have high frequency and large change of
12 be near IPD’s control terminals (VCC, VDD, FB) and the
voltage and current. Terminals shouldn’t be closed to those loops in order not to be affected by those noise.
pattern connected to those terminals.
Because high frequency and large current flows through that loop, that loop should be short and the area in that loop should
13 Secondary rectification loop should be as short as possible.
be small in order to prevent Noise at this loop.
The patterns should be separated and made narrow where pattern is connected to the smoothing capacitor, in order to avoid
Secondary rectification loop is separated from Pattern after
14 “Noise at secondary rectification loop reaching to pattern before the input capacitor”, “Serge and Noise at AC input line
smoothing capacitor.
reaching to power loop and IPD”, “Heat of rectification diode reaching to the input capacitor”.
We would like to ask you to consider to prevent the noise of relays at AC line or lamp from reaching to IPD. For example,
Design is considered that the noise of relays at AC line or
15 could you consider that “the source and the conduction route of noise shouldn’t be near IPD” or “dealing with that source , for
lamp don’t affect the operation of IPD.
example, putting a capacitor” or “putting Y-capacitor on the conduction route of that noise”.
The length of pattern between FB and a resistor should be FB terminal is very sensitive for noise. So we would like to suggest you could make that pattern as short as possible, as that
16
as short as possible. pattern is difficult to catch noise.

－P13－
1- (6) PCB pattern design January. 2012

Check list of PCB layout Priority : 1 = Most critical 2 = Very important 3 = As good as possible

No. Check item Check Priority

1 Pattern of power loop is separated from Pattern before the input capacitor. 2
2 AC line( in particular, before input filter) should not be located near power loop. 2
3 Power loop should be as short as possible. 3

4 The parts to prevent surge to AC input (for example, Y-capacitor, Varistor, etc) should be located on the pattern
1
from AC input to IPD.
5 The pattern which is connected to Y-capacitor should be as short and wide as possible. 2
6 The clamp circuit of Drain terminal should be located in power loop and near the transformer. 3
7 GND of power loop is separated from GND of IPD control circuit. 1
8 The ceramic capacitor between VDD and S must be located near each terminal. 1
9 The pattern connected to FB terminal shouldn’t be near bias windings rectification loop or power loop. 1
10 GND of bias windings rectification loop is separated from GND of IPD control circuit. 3
11 Pattern of bias windings rectification loop should be wide and short. 3
Power loop and bias windings rectification loop shouldn’t be near IPD’s control terminals (VCC, VDD, FB) and the
12 2
pattern connected to those terminals.
13 Secondary rectification loop should be as short as possible. 3
14 Secondary rectification loop is separated from Pattern after smoothing capacitor. 2
15 Design is considered that the noise of relays at AC line or lamp don’t affect the operation of IPD. 1
16 The length of pattern between FB and a resistor should be as short as possible. 3

－P14－
 1- (7) Check list of evaluation board January. 2012

To find problems, we prepared the check list. After your trial, we would like to ask you to evaluate your board according to this check list.
And, you should correct the circuit, if you find NG items.

Check list for MIP521A application

Customer　： IPD　： ILIMIT_min = 450mA
End Set　： Input voltage SPEC　：　AC VD_max = 800V
Output SPEC　　： MAXDCmin = 50%

Check condition
Check Items Judgement standard (Target_including margin） OK/NG Remarks
Input voltage Output power
1.START UP
VDSmax < VD_max (800V)
1 VDS does not exceed Absolute maximum rating. HIGHEST MAX OK/NG
recommended value is less than 720V.
2 Transformer is not saturated. No saturation at maximum IDS ALL MAX OK/NG
3 VFB rising doesn't make Over Load Protection activated. VFBmax < VFB(OLP)_min (3.6V) LOWEST MAX OK/NG

2.NORMAL OPERATION
1 Abnormal oscillation doesn't occur. ALL ALL OK/NG
2 Maximum output power can be generated. IDp < ILIMIT_min*0.9 LOWEST MAX OK/NG
3 OVP isn't activated at maximum output power. VCCmax < VCC(OV)_min (28V) ALL MAX OK/NG
4 VCC is not too low at minimum output power. VCCmin > VCC(OFF)_max (11.0V) ALL MIN OK/NG
5 Continuous mode is not excessive. 0.6< KRP LOWEST MAX OK/NG
6 Duty cycle is not higher than 50%. On Duty < 50% LOWEST MAX OK/NG
VDSmax < VD_max (800V)
7 VDS does not exceed Absolute maximum rating. HIGHEST MAX OK/NG
recommended value is less than 720V.
VDSmin > 0V
8 The bottom of VDS ringing is higher than 0V. LOWEST Discontinuous mode OK/NG
recommended value is more than 20V
VDS does not drop below 0V due to ringing immediately VDSmin > 0V
9 LOWEST MAX OK/NG
after turning on. recommended value is more than 20V
Voltage ratings of Secondary diode Snubber diode, Bias winding
10 HIGHEST MAX OK/NG
diode are enough.
11 Voltage rating of Snubber capacitor is enough. HIGHEST MAX OK/NG

3.Others
Ceramic capacitor between VDD and S terminal is connected
1 OK/NG
near VDD terminal.
2 Ceramic capacitor is mounted between FB and S terminal. OK/NG If it is not mounted, it is not necessary to consider.
3 GND of Power loop is separated from IPD'control circuit. OK/NG
4 Transformer isn't saturated at IDS=ILIMIT_max. Allowable current of transformer>ILIMIT_max Please ask the transformer OK/NG

*　[ _max、_min ] mean the maximum or minimum value of SPEC.

－P15－
A note of caution January. 2012

Re qu e st for you r spe c ial atte n tion an d pre c au tion s in usin g th e technical information and semiconductors described in this doc u me n t

(1) Please observe the laws and regulations , especially Security trade control laws of relevant country if any information in this document is exported or
offered to any non‐resident person.

(2) The technical information provided herein explains characteristics and application circuits of the product, which, however, does not constitute a
waiver of any intellectual property or right of Panasonic Corporation or third parties.

(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment,
communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
・Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety
devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the
human body.
・Any applications other than the standard applications intended.

(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final
stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date.

(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply
voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as
power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode that possibly
occurred in semiconductor products. Countermeasure such as fire trapped circuit or glitch prevention circuit are recommended when using the products
to prevent physical injury, fire or social damages.

(6)　Please keep all precautions for use to avoid failure and characteristic change by external factors (ESD, EOS, thermal stress and mechanical stress)
when products are used or mounted.
When using products of which moisture-proof packing is required, please observe the conditions, including shelf life and the time allowed for exposure, as
indicated upon specification sheets when handed in.

(7) This book may not be reprinted or reproduced whether wholly or partially, without the prior written permission of Panasonic Corporation.

(8)The technical information of application provided herein is for your reference, we do not guarantee quality and characteristic of your application
design. Please investigate actual sets on your side and make the final decision, based on your specification or regulation

－P16－