11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts

More Next Blog»

VLSI Concepts
An online information center for all who have Interest in Semiconductor Industry.

Content VLSI BASIC STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Job Posting Video Lectu

Recommended Book About Us Assessment

Want to accelerate your

time to design closure?
Learn More
Tempus™ Timing Signoff Solution

Search This Blog ASIC Verification

Search

Index

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8

STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6

Extraction &
DFM Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other
n Corner) Modeling Layer Variation Topic Register Now

Featured Post
Friday, January 10, 2014

"Fresher" become
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) 3Ps (Passion, Pati
Basic (Part-8) The Journey from Fres
easy as everyone think
suggest to students/ca

Part1 Part2 Part3a Part3b Part3c Part4a Part4b Part4c Part5a

Part5b Part6a Part6b Part6c Part7a Part7b Part7c Part 8

Static Timing analysis is divided into several parts:

Part1 -> Timing Paths

Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Total Pageviews
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
5,366,390
Part4a -> Delay - Timing Path Delay
Part4b -> Delay - Interconnect Delay Models
Part4c -> Delay - Wire Load Model
Part5a -> Maximum Clock Frequency
Subscribe To VLSI EXP
Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
Posts
Part 6a -> How to solve Setup and Hold Violation (basic example)
Comments
Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
Part 8 -> 10 ways to fix Setup and Hold Violation.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 1/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts
10 Ways to fix SETUP and HOLD violation:
Till now, We have discussed basic concepts of fixing the Setup and Hold violation which include
Different formulas + explanation to identify the type of violation in design.
How to fix those violations?
Different methods of Increasing and Decreasing the Delay in the circuit to fix these type of violations?
And Now it’s the time to list down different methods to fix these violations. I have also explained in brief each and every method, which
also referring previous post for reference. One point to remember here that Fixing the Setup and Hold Violation are reverse in nature. All the
Edusaksham
methods which are applicable to fix one type of methods , hold true and can be apply to fix other type of if we will do the opposite thing. E.g - if
VLSI - Self...
setup can be fix by adding 1 buffer in some path then Hold can be fix by removing buffer in that path. (You will see these things below in the post)
INR 5,750.00
In the last you will also find DOs and DON'Ts and recommended approach to fix these violations. These Recommendations helps designer in
Shop now
reducing iteration and fix the violations fast.

8 Ways To Fix Setup violation:

Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop.
With that in mind there are several things a designer can do to fix the setup violations.

Method 1 : Reduce the amount of buffering in the path.

It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to
wire delay, the effective stage delay decreases. Edusaksham
VLSI - Static...

Method 2 : Replace buffers with 2 Inverters place farther apart INR 2,300.00

Adding 2 inverters in place of 1 buffer, reducing the overall stage delay. Shop now

Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the
RC delay of the wire (interconnect delay) decreases.
Popular Posts
As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate
So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in "Timing Paths" : Sta
the same path. Timing Analysis (ST
basic (Part 1)
You will get the clear understanding by following figure and you can refer the first post to understand
how transition time varies across the wire. Basic of Timing
Analysis in Physical
Design

"Setup and Hold Tim

: Static Timing Analy
(STA) basic (Part 3a

Delay - "Wire Load

Model" : Static Timin
Analysis (STA) basic
(Part 4c)

"Setup and Hold Tim

Violation" : Static
Timing Analysis (ST
basic (Part 3b)

"Examples Of Setup
and Hold time" : Sta
Timing Analysis (ST
basic (Part 3c)

Delay - "Interconnec
Delay Models" : Sta
Timing Analysis (ST
basic (Part 4b)

"Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)

5 Steps to Crack VL
Interview

10 Ways to fix SETU

and HOLD violation
Static Timing Analys
(STA) Basic (Part-8)
Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
Low Vt decrease the transition time and so propagation delay decreases.
Recent Visitors
HVT/NVT/LVT type cells have same size and pin position. In both leakage current and speed, LVT>NVT>HVT.
So replace HVT with NVT or LVT will speed up the timing without disturb layout.
Negative effect: Leakage current/power also increases.

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)
Explained the basic and details in the previous post
Note: Normally larger cell has higher speed. But some special cell may have larger cell slower than normal
cell. Check the technology library timing table to find out these special cells. Increasing driver is very
commonly used in setup fix.
Negative effect: Higher power consumption and more area used in the layout.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 2/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts
I have notice one explanation in book <book name>. I am copying and pasting (not 100%) that here because I Live Traffic Feed
like that one. J Marked the important part by Bold. A visitor from San
California viewed
The basic layout technique for reducing the gate delay consists in connecting MOS devices in Concepts" 1 min ag
parallel.
A visitor from Ban
The equivalent width of the resulting MOS device is the sum of each elementary gate width. Both Karnataka arrived f
nMOS and pMOS devices are designed using parallel elementary devices. google.co.in and vi
"Layout Design Ru
Most cell libraries include so-called x1, x2, x4, x8 inverters.
Design Rule Check
The x1 inverter has the minimum size, and is targeted for low speed, low power operations. (DRC)
A visitor |VLSI
fromConc Ban
The x2 inverter uses two devices x1 inverters, in parallel. The resulting circuit is an inverter min ago arrived f
Karnataka
with twice the current capabilities. The output capacitance may be charge and discharged google.co.in and vi
""Setup and Hold T
twice as fast as for the basic inverter (see below figure), because the Ron resistance of the
Static Timing Anal
MOS device is divided by two. The price to pay is a higher power consumption. (STA) basic (Part 3
A visitor from Jaka
The equivalent Ron resistance of the x4 inverter is divided by four. |VLSI Concepts"
Jakarta Raya viewe 3
The clock signals, bus, ports and long wires with severe time constraints use such high drive circuits. ago
""Timing Paths" : S
Timing Analysis (S
basic (Part 1) |VLS
A visitor from
Concepts" 6 mins Alga
arrived from googl
and viewed ""Timi
Paths" : Static Tim
Analysis (STA) bas
A visitor
(Part from Con
1) |VLSI Tha
Maharashtra
7 mins ago arrive
google.co.in and vi
"DIGITAL BASIC
Sequential Circuit
A visitor from
Concepts" 11 mins Sant
Maria, California a
from vlsi-expert.co
viewed "Fixing Set
Hold Violation : St
Timing Analysis (S
A visitor
Basic from
( Part 6a)Hyd |VL
Andhra
Concepts" Pradesh
12 mins arr
from google.co.in a
viewed "Synopsys
Constraints (SDC)
A visitor
|VLSI from Ho1C
Concepts"
Minh
ago City, Ho Chi
arrived from googl
and viewed "10 Wa
fix SETUP and HO
violation: Static Tim
A visitor (STA)
Analysis from Pula Ba
Pinang
(Part-8)viewed |VLSI Con "Pa
Interconnect
13 mins ago Corne
Method 5 : Insert Buffers Corner) Basics - Pa
Some time we insert the buffer to decrease over all delay in case of log wire. |VLSI Concepts" 1
Real-time view · Get Feedjit
Inserting buffer decreases the transition time, which decreases the wire delay.
If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay
decreases.
Negative Effect: Area will increase and increase in the power consumption.
Followers

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 3/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts
Method 6 : Inserting repeaters:
Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to
explain this in a different way but the over concept are same.
Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good
alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in
terms of delay? Because the gate delay is quite small compared to the RC delay.

In case of Interconnect driven by a single inverter, the propagation delay become

Tdelay= tgate+ nR.nC = tgate + n2RC
If two repeaters are inserted, the delay becomes:
Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
So you can see how RC delay is impacting in case of non-repeater in the circuit.
Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed
performances, at the price of higher power consumption.
Below figure helps you to understand the practical use of this.

Method 7 : Adjust cell position in layout.

Let’s assume there are 2 gate (GATE A and GATE B) separated by 1000um. There is another GATE C placed
at the distance of 900um from GATE A.
If we re-position the GATE C at 500um from GATE A (center of GATE A and B), overall delay between GATE A
and B decreases.
You will get the clear understanding by first post and the following diagram.
Note: The placement in layout may prevent such movement. Always use layout viewer to check if there are
any spare space to move the critical cell to an optimal location.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 4/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts

Method 8 : Clock skew:

By delaying the clock to the end point can relax the timing of the path, but you have to make sure the
downstream paths are not critical paths.
Related to clock skew basic – I will discuss that in SI section.

2 Ways to Fix Hold Violations:

Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock
speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is
nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be
reduced.
The designer needs to simply add more delay to the data path. This can be done by

Method 9 : By Adding delays.

Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
Note: The hold violation path may have its start point or end point in other setup violation paths. So we have to
take extra care before adding the buffer/delay.
E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert
the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other
path.
if the start point of hold violation path has setup violation with respect to some other path, insert the
buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
I am sure you may be asking what is this and why?
Below figure and explanation can help you to understand this.
From below figure, you can also conclude that don’t add buffer/delay in the common segment of 2
paths (where one path has hold violation and other setup violation).

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 5/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts

Method 10 : Decreasing the size of certain cells in the data path.

It is better to reduce the cells closer to the capture flip flop because there is less likely hood of affecting other
paths and causing new errors.

Note: Following points are recommended while fixing setup and hold violations.
Make modification to the data path only.
Adjusting register location or removing/adding buffers to the clock path will fix the violation that but it
may cause more violations for some other paths which may not present before.
First try to fix setup violation as much as possible. Then later on start fixing hold violation.
In general, hold time will be fixed during back-end work (during PNR) while building clock tree. If u r a front-end designer, concentrate on
fixing setup time violations rather than hold violations.
Fix all the hold violation, if you have to choose between setup and hold.
If a chip is done with some setup violations it can work by reducing the frequency.
If a chip is done with hold violations, we have “JUST DUMP” the chip.

Previous Index Next

Posted by VLSI EXPERT at 5:17 PM

Reactions: Excellent (16) Good (1) Interesting (0) Need More (2)

32 comments:
Prashanth Anil Mascarenhas February 16, 2014 at 2:00 PM

Awesome Learning Experience. It is a very interesting blog to refresh the concepts on STA. Thank you:)

Reply

Anonymous March 7, 2014 at 2:24 AM

Kudos to you!! This is one great blog for learners like me! Thank you loads for all your effort! May god bless you!

Reply

Anonymous April 20, 2014 at 7:31 PM

really nice to learn...

Reply

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 6/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts

Anonymous June 5, 2014 at 2:51 PM

Explanation in awesome. Efficient use of examples. Looking forward to read more topics.

Reply

Anonymous June 28, 2014 at 3:42 AM

thank you very much.

interesting.....

Reply

Anonymous August 20, 2014 at 3:01 PM

The explanation is great. Thanks for sharing the post :)

Reply

Anonymous August 24, 2014 at 6:05 AM

Thank you

Reply

Anonymous October 6, 2014 at 6:59 PM

Thank you very informative :)

Reply

wenjun he December 22, 2014 at 9:03 PM

Hi, Sir,

when will RC delay (wire delay) > cell delay?

Sincerely,
Eric

Reply

Anonymous February 12, 2015 at 11:54 PM

Thank you for a very informative blog on STA. Lot of concepts got clearer.

Reply

Anonymous February 16, 2015 at 9:57 PM

Very nice and great work sir..Kudos to you..

Reply

Anonymous April 20, 2015 at 12:38 PM

Great stuff. Check method 2, bullet 3.

Reply

Anonymous June 3, 2015 at 9:38 AM

If a chip has hold violations it can be fixed by changing the supply voltage. For hold you might need to increase the logic delay and so decreasing the
supply voltage. This might actually trigger set up violation but care needs to be taken.

Reply

Vivek Soni July 28, 2015 at 12:56 AM

This was really helpful. Can you please suggest any sources to practice questions on this topic?

Reply

Anonymous September 12, 2015 at 10:32 PM

Thank you very much

Reply

mani teja naik October 30, 2015 at 10:30 AM

wow super pakka very good explanation

Reply

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 7/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts
Unknown November 20, 2015 at 3:43 PM

Thanks a lot!!! learnt a lot from this blog

Reply

Anonymous December 12, 2015 at 7:25 PM

Hi,
You have said, "hold violation happens when data is too fast compared to clock speed". But how can hold violation be related to clock speed? Here
with clock speed do you mean delay in capture path or clock frequency?

Reply

Unknown December 15, 2015 at 7:15 PM

You got to efficiently explain what Synopsys and Cadence manuals don't do. Thanks a mill.

Reply

Parthasarathi Patra January 14, 2016 at 8:45 AM

Who fix these setup and hold violation?

Whether the designer or backend team?

Reply

Replies

VlsiExpertGroup January 18, 2016 at 4:46 PM

Before I can help you with the Answer - you have to differentiate the work of Designer and backend Team? What do you mean by Backend
team ?

Reply

Anonymous March 17, 2016 at 1:29 AM

sir ur saying like first go for setup violation then after for hold ..but after CTS also preference only for setup first and then for hold ???...plz clearify

Reply

Unknown April 16, 2016 at 10:02 PM

Thanks for the blog post . Quick query : Hold time of a flop dictates that logic delay of the combinational path be more than a given value ( Tdelay >
Thold ) . So can we say that Thold puts a limit on the max frequency of operation since 1/ (max freq) > Tsetup + Tdelay ( I am ignoring c2q delays and
clk skews for simplicity )

Reply

Replies

VLSI EXPERT April 18, 2016 at 8:54 AM

I can reply you .. but best is you check these 2 Articles

http://www.vlsi-expert.com/2016/02/setup-and-hold-check.html
http://www.vlsi-expert.com/2016/02/setup-and-hold-violation.html

At the end of these 2, I am sure you can yourself figure out whether it has dependency or not. If Not - Ping me again - I will explain you.

VLSI EXPERT April 18, 2016 at 8:59 AM

links are:

Advance Setup and Hold Check

Advance Setup and Hold Violation

Anonymous May 26, 2016 at 12:18 PM

Hi, thanks for the reply.. I read through the blogs; still I think there is a dependence ie If I reduce the combinational path delay to a very low
value (~0) then there would be hold violation; hence "max freq period" = Tsetup + Tcombdelay.

Reply

Appasab Naganasure June 19, 2016 at 10:09 AM

Thanks a lot for information...............

Reply

Unknown June 20, 2016 at 1:00 AM

If there is a long wire between cells then adding buffers will reduces the delay through decrease in transition time. So, my question is, how is optimum
number of buffers are determined? I hope adding in more numbers will increase delay than reducing it!!

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 8/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts
Reply

Replies

VLSI EXPERT June 20, 2016 at 11:33 AM

You are right .. If you will add more buffer , it will increase the delay. There are lot of ways to find the optimum number of buffers. Basically
there are algorithm for that. but this post is just to provide a insight about the methods which can help you in the field or during design.
Other Algorithm I will try to cover in some other post.

Reply

pram August 27, 2016 at 10:03 PM

Is it possible to fix the hold violation of a manufactured chip by tweaking operating condition, e.g., decreasing supply voltage or increasing
temperature?

Reply

Srinivasan May 31, 2017 at 5:33 PM

Hi,

I am using Vivado design suite from Xilinx. After synthesis, in timing summary, I got a some setup time violations. There was an option to maximize the
delay from start point to end point. After following that step, the setup time violation issue was solved.

The above condition contradicts the fact that "decreasing the delay" fixes the setup time violation. Please explain.

Reply

Anonymous October 11, 2017 at 1:57 PM

hi expert
what about pipeline technique?
if the timing is not meeting b/wn two flops by regular methods .we can insert flop to meet timing is it correct or not? please reply me

Reply

Links to this post

Create a Link

Newer Post Home Older Post

Subscribe to: Post Comments (Atom)

Must Read Article

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 9/10
11/9/2017 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts

5 Steps to Crack VLSI Fixing Setup and Hold Fixing Setup and Hold "Examples Of Setup
Interview Violation : Static Timing Violation : Static Timing and Hold time" : Static
Analysis (STA) Basic (... Analysis (STA) Basic (... Timing Analysis (STA)

Setup and Hold Check: Skew Types Of Clock Skew STA & SI
Advance STA (Static
Timing Analysis )

Follow by Email

Email address... Submit

Vlsi expert group. Simple theme. Powered by Blogger.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html 10/10