2.

1 INTRODUCTION
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This description is called the programmer's model. We´ll begin by examining the basic parts of the ARM7TDMI and Cortex-M4
programmer's models.

2.2 DATA TYPES

Data in machines is represented as binary digits, or bits, where one binary digit can be seen as either on or off. A one or a zero.
A collection of bits are often grouped together into units of eight, called bytes, or larger units whose sizes depend on the maker
of the divice.

Cortex-M4 processors support the following data types:

☺ Byte, or 8 bits
☺ Halfword, or 16 bits
☺ Word or 32 bits

So you will need two bytes to create a Thumb instructions and four bytes to create either an ARM instructions or a Thumb-2
instructions.

When reading ro writing data, halfwords must be aligned to two-bytes boundaries, which means that the address in memory
must end in an even number. Words must be aligned to four-byes boundaries, i.e addresses ending 0,4,8 or C.
Boundaries =
The Cortex-M4 allows unaligned accesses under certain conditions, so it is actually possible ro read or write a word of data
limites
located at an odd address. EITHER = YA SEA
Even = par
Odd = impar
3.2 ARM7TDMI
Older programmer's model is to show its similarity to the more advanced cores-The Cortes-A and Cortex-R processor.

It is also noteworthy to point out features that are common to all ARM processor but differ by number, use, and limitations.

The size of the integer regster file on the Cortex-M4.

3.2.1 PRECESSOR MODES

Version 4t cores support seven processor modes: User, FIQ,IRQ,Supervisor,Abort, Undefined, and System,

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Abort mode allows the processor to recover from exceptional conditions such as a memory access to an address that doesn´t

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Abort mode allows the processor to recover from exceptional conditions such as a memory access to an address that doesn´t
physically exist, for instruction or data. This mode can also be used to support virtual memory sistems.

The processor will switch to Undefined mode when it sees an instruction in the pipeline that it does not recognize;

2.3.2 REGISTERS
The register is the most fundamental storage area on the chip. You can put: data values, timer, a counter, or a coefficient for an
FIR filter; or addresses , table, memory.

☺ 30 general-purpose register, i.e., registers which can holdd any value

☺ 6 status register
☺ A Program Counter Register

The general-purpose register are 32 bits wide, the registers are arranged in partially overlapping bank.

Wide = ampli@
15 general-purpose register(R0 to R14), and the program Counter (PC or 15) are visible.
Overlapping = superposición
Register R14(the Link Register)

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Being = siendo, ser existencia

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Being = siendo, ser existencia
Fetch = ir a buscar, extraer,
Meaning that while one instruction is being fetched, another is being decoded, and yet another is being executed. The address
entregar
of the instruction that is being fetched(not the one being executed)is contained in the program counter. This register is not Certain = ciert@
normally accessed by the programmer unless certain specific actions are needed, such as jumping long distances in memory or
recovering from an exception.

The current program Status Register (CPSR) can be seen as the state of the machine allowing programs to recover from
exceptions ro branch on the results of an operation. It contains condition code flags, interrupt enable flags, the current mode,
Each privileged mode (except System mode) has a Saved Program Status Register (SPSR) that is used to prserve the value of the
CPSR when an exception accurs. Since User mode and System mode are not entered on any exception.

The format of the Current Program Status Register and the Saved Program Status Register is that it contians four bits at the top,
collectively know as the condition code flags.

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The condition code flags in the CPSR can be altered by arithmetic and logical instructions, such as subtractions logical shifts, and
rotations.

The bottom eight bits of a status register are known as the control bits. The I and F bits are the interrupt disable bits, which
disable interrupts in the processor if they are set. The I bit control the IRQ interrupts, and the F bit controls the FIQ interrupts.
The T bit is a status bit, menat only to indicate the state of the machine, so as a programmer you woild only read this bit, not
write to it, if the bit is set to 1, the core is executing Thumb code, which consists of 16-bit instructions.

Table 2.1 shows the interpretation of the least significant bits in the PSRs, whick determine the mode in which the processor
operates.

2.3.3 THE VECTOR TABLE

The exception vector table consists of designated addresses in external memory that hold informations
necessary to handle an exception, an interrupt. Or other atypical event such as a reset.

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So the next instruction that the machine will likely fetch is a branch (B) instruction, assuming the programmer
put such an instruction at address 0x18. Once this branch instruction is executed,

2.4 CORTEX-M4
These cores are designed to be used in applications that require 32-bit processors to achieve high code
density, fast interrupt response times.

2.4.1 PROCESSOR MODES

The Cortex-M4 has only two models: Handler model and thread mode. There are also two access levels to go
along with the modes. Privileged and User, and depending on what the system is doing.

2.4.2 REGISTERS
If you have a Cortex-M4 that includes a floating-point unit. There are actually more.The Cortex-M4 with
floating-point hardware contains the following registers as part of the programmer´s model:

☺ 17 genaral purpose register, i.e., registers than can hold any value
☺ A status register than can be viewed in its entirety or in three specialized views
☺ 3 Interrupt mask registers
☺ A control Regiter
☺ 32 single-precision floating-point registers (S0-s31) or 16 double-precision registers (do- d15) or a mix
☺ 4 Floating-point control register (Although these are memory-mapped, not physical registers)

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Stack = apilar
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Register R0 through R12 are general purpose registers, and the registers hold 32-bit values that can be
anything you like addresses,data,packed data, fractional data values, anything. Thera are some special purpose
registers, such as register R13, the stack pointer(and there are two of them, giving you the ability to work with
separate stacks).

Register R14, the Link Register, and Register R15, which is the Program Counter. Register R13 (the Stack
pionter or SP) holds the address of the stack in memory, only there are just two of them in the Cortex-M4.

There is only one Link Register. Register R15, the Program Counter or PC, points to the instruction being
fetched, but due to pipelining, there are enough corner cases to make hard and fast rules about its value
difficult.

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The Application Program Status Register (APSR), the Interrupt Program Status Register(IPSR), and the
Execution Program Status Register (EPSR) are just three specialized views of the same register. The APSR
contians the status flags(N,C,V AND Z), the Greater Than or Equal flags(used by the SEL instruction), and an
additional "sticky" Q flag used in saturation arithmetic

The last special purpose register is the Control register, which consists of only three bits, The least significant
bit, CONTROL[0], changes the access level while in Thread mode to either a Prvileged or User level. The next
most significant bit, CONTROL[1], selects which stack the processor is to use, either the Main Stack Pointer
(MSP), The most significant bit, CONTROL[2], indicates whether or not to preserve the floating-point state
during exception processing.

2.4.3 THE VECTOR TABLE

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