Tutorial 4

1. Briefly explain what are adders?

2. What are the full-adder inputs that will produces each of the following
outputs:
(a) Σ = 0 , Cout = 0
(b) Σ = 1 , Cout = 0
(c) Σ = 1 , Cout = 1
(d) Σ = 0 , Cout = 1

3.Design a logic circuit of the 2 bit comparator shows

4. In the process of checking a 74LS283 4-bit parallel adder, the following logic
levels are observed on its pins: 1-High, 2-High, 3-High, 4-High, 5-Low, 6-Low, 7-
Low, 9-High, 10-Low, 11-High, 12-Low, 13-High, 14-High, and 15-High. Determine
if the IC is functioning properly.

5. For the 4-bit comparator, plot each output waveform for the inputs shown. The
outputs are active-High.

6. For each set of binary numbers, determine the output states for the comparator
shown.
(a) A3 A2 A1 A0 = 1100 (b) A3 A2 A1 A0 = 1000 (c) A3 A2 A1 A0 = 0100
B3 B2 B1 B0 = 1001 B3 B2 B1 B0 = 1011 B3 B2 B1 B0 = 0100
 Decoder

7. Assume the output of the decoder shown in Figure 8 is logic 1. What are the
inputs to the decoder?

8. Assume the inputs to the 74HC42 (in Figure 9) decoders are the sequence
0101,0110, 0011, and 0010. Describe the output.

Encoder

9. Show how the decimal-to-BCD encoder converts the decimal number 3 into a
BCD 0011
Multiplexers
10. Which data line is selected when S1S0= 10?

11. Draw a block diagram for a 8:1 multiplexer using 4:1 multiplexer. Show the truth
table.

12. Determine the outputs, given the inputs shown in figure below.
Extra

13.

Try all input combinations and fill in the following truth table :

14.
Draw the logic diagram of a 4 x 16 decoder using two 3 x 8 decoders
constructed with NAND gates (active LOW outputs).
15.
Complete the truth table below for the BCD-to-Seven-Segment decoder with
inputs A, B, C, D and outputs a, b, c, d, e, f, g for common anode Seven-
Segment display.
16. Consider what happens when, instead of using a 16 to 1 Multiplexer, we use an 8
to 1 Mux. If we choose to connect A, B, and C to the inputs of the Multiplexer, then
for each combination of A, B and C,

17. Replace with 4-1 mux.

18. Replace with 2-1 mux.
19 Design a binary to 7-segment code converter for use in displaying a hexadecimal
representation of a 4-bit binary number. (Use lowercase for ‘b’ and ‘d’.) You may use
multiplexers and decoders in your design, as you feel appropriate, as well as primitive
gates (e.g., nand gates).
20. Determine what state the ”select control” input line has to be in to select InputA to
be sent to the output, and what state it has to be in to select InputB to go to the output.

21. Implement the function f(A,B,C) = Σ(0, 3, 6, 7) using a 4 x 1 multiplexer.

The multiplexer implementation table is shown below.

22. Show the MUX implementation table for the function in (21) if B and C are
connected to the select lines.

23. Design a 4x16 decoder using a minimum number of 74138 and logic
gates.

24. Design a combinational circuit to generate the following:

F0 = SUM (m(1,3,4))
F1 = SUM ( m(0,2,4,7))
F2 = SUM (m(0,1,3,5,6))
F3 =SUM (m(2,6))
Draw a logic diagram using a 74138 decoder and external gates.

25. Design -using 74154 Decoder and OR gates- a combinational circuit that has 4-
inputs A,B,C,D, and F1 as the output: F1(A,B,C,D) = Σm (0,3,7,9,14)
26. Design a 4 bit Adder using full adders to add 4-bit binary numbers.

27. Referring to the encoder circuit in Figure 1, determine what the output code would
be if:

Figure 1

a. Button 9 is pressed
b. Button 2 and 4 pressed at the same time
c. Button 5, 9 and 6 pressed at the same time
d. All button are pressed at the same time