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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
BIST-Based Fault Diagnosis for PCM With
Enhanced Test Scheme and Fault-Free
Region Finding Algorithm
Chenchen Xie , Xi Li, Yu Lei, Member, IEEE, Houpeng Chen , Qian Wang,
Jiashu Guo, Jie Miao, Yi Lv, and Zhitang Song
Abstract— As one of the most promising candidates for non-
volatile memory, phase change memory (PCM) technology has
shown great performance advantages in market applications.
However, the conventional test methods have not kept pace
with the development. In this article, focusing on specific PCM
faults and others, an enhanced march test algorithm is proposed
to achieve 100% fault coverage and diagnostic accuracy in
bit-oriented PCM. The proposed algorithm is then converted
for word-oriented PCM and equipped with capability to detect
potential intraword impact. In addition, to reduce the dependence
of memory test on the external devices, a novel storage scheme
of fault information is devised. Through the modeling and
simulation in C-language, this method is proven to improve the
probability of finding the predefined fault-free regions in the
tested memory. Finally, combining the enhanced test algorithm
and the novel storage scheme, a built-in self-test (BIST) march
test scheme is proposed, realizing the independent test of PCM
without any external equipment. By comparison, the result of
experiments, which are performed with C-language, proves that
the proposed test scheme not only increases the fault coverage
and diagnostic accuracy, but also reduces the additional area
overhead.
Manuscript received November 8, 2019; revised January 18, 2020 and
March 7, 2020; accepted March 27, 2020. This work was supported in part
by the National Natural Science Foundation of China under Grant 91964204,
Grant 61874178, Grant 61874129, Grant 61904186, and Grant 61904189; in
part by the National Key Research and Development Program of China under
Grant 2017YFA0206101, Grant 2017YFB0701703, Grant 2017YFA0206104,
Grant 2017YFB0405601, and Grant 2018YFB0407500; in part by the Sci-
ence and Technology Council of Shanghai under Grant 19JC1416801 and
Grant 17DZ2291300; in part by the Shanghai Sailing Program under
Grant 19YF1456100; and in part by the Shanghai Research and Innovation
Functional Program under Grant 17DZ2260900. (Corresponding author:
Xi Li.)
Chenchen Xie, Jiashu Guo, Jie Miao, and Yi Lv are with the State Key
Laboratory of Functional Materials for Informatics, Shanghai Institute of
Microsystem and Information Technology, Chinese Academy of Sciences,
Shanghai 200050, China, and also with the University of Chinese Academy
of Sciences, Beijing 100049, China (e-mail: xcc@mail.sim.ac.cn).
Xi Li is with the State Key Laboratory of Functional Materials for Informat-
ics, Shanghai Institute of Microsystem and Information Technology, Chinese
Academy of Sciences, Shanghai 200050, China, and also with the Shanghai
Technology Development and Entrepreneurship Platform for Neuromorphic
and AI SoC, Shanghai 20090, China (e-mail: ituluck@mail.sim.ac.cn).
Yu Lei, Houpeng Chen, Qian Wang, and Zhitang Song are with the State
Key Laboratory of Functional Materials for Informatics, Shanghai Institute
of Microsystem and Information Technology, Chinese Academy of Sciences,
Shanghai 200050, China (e-mail: leiyu@mail.sim.ac.cn).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2020.2986469
1063-8210 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1
Index Terms— Built-in self-test (BIST), fault-free region (FFR),
phase change memory (PCM), test algorithm, test scheme.
I. I NTRODUCTION
P HASE change memory (PCM), one of the most promis-
ing and commercialized emerging nonvolatile memories,
has attracted more attentions because of its excellent perfor-
mance [1]–[3]. With the shrinking of process dimension and
the increasing of capacity, the possibility and types of defects
increase in the memory, making the reliability problem more
critical. However, conventional test methods for memory are
becoming more inefficient. There are several major obstacles
for conventional test using automatic test equipment (ATE).
First, the memory technology has been developed very fast
that it is hard for ATE to test the memory chips at full
speed. Second, the test needs external content-addressable
memories (CAMs) to record the information including fault
types and locations for analysis and subsequent redundant
substitution, which inevitably increases the cost. Last but not
least, the defects of memories will change with environment
and lifetime, and it is impossible for conventional method to
test the chip after it has been put into application.
Built-in self-test (BIST) is a preferred test methodology
which is capable of solving the above issues. It requires
additional test modules inside the chip for the purpose of
completely getting rid of external ATE. This design for testa-
bility (DFT) was first proposed in 1979, but the integration
level was not high enough for the primary consideration of area
cost; thus, the design was not realistic at that time. In recent
years, the integrated circuit industry has been developing
rapidly. The continuous improvement of integration makes the
proportion of chip area occupied by BIST become negligible,
which brings it back to the hot point of research [4]–[7].
Most of the studies focusing on SRAM or Flash memory have
proved the superiority of BIST-based test method. Therefore,
it suggests a more efficient way to test PCM with BIST design.
Mohammad et al. [8] and Mohammad [9] summarize some
fault models of PCM and propose a march test algorithm
named March-PCM to detect these faults [9]. But there is
limitation in detecting proximity disturb (PD) faults with
March-PCM and some faults cannot be distinguished accord-
ing to the test results. Moreover, the above test algorithm
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
is proposed under the assumption that the PCMs are bit-
oriented memories (BOMs)—the read and write operations
affect only a single cell in the memory. As for word-oriented
memories (WOMs) which are more common in application,
the influence between different bits in one word cannot be
ignored and special algorithm should be developed to detect
intraword faults.
Kannan et al. [10] utilize the sneak-path in the crossbar-
based nonvolatile random access memories to improve the
test efficiency, while the faults mentioned in [9] cannot be
tested effectively by the proposed algorithm [11]. Furthermore,
a DFT of forcibly introducing sneak-path is proposed for
memories based on 1-Transistor/Diode-1-Memristor structure,
but it cannot reflect the fault condition of tested memories in
their normal working mode. On the contrary, it may also detect
some faults that do not even exist originally due to the sneak-
path. Cui et al. [11] propose a test algorithm March-SA using
snake addressing scheme to reduce the test length. However,
when detecting PD faults, it only considers the impact of
four neighboring cells instead of the eight first neighboring
cells defined in [8] and [9]. Besides, the detection of one-to-
many determines the fact that it is impossible to diagnose the
detected fault as the correct type.
In addition to fault types and test algorithm, the storage
of fault information is also a major problem. Conventional
memory test methods store fault information in external
devices with the help of ATE, and most BIST approaches
always utilize CAMs. Oh et al. [12] propose a built-in
redundancy analysis (BIRA) method, which utilizes a fault-
free memory region to store the faulty cell information
instead [12]. Although the concrete procedure for finding this
fault-free region (FFR) is not mentioned, it still provides a
good conception to reduce area overhead in memory BIST
scheme.
In this article, an enhanced march test algorithm named
March-BOPCM is proposed after analyzing the constraints
faced by previous algorithms from several aspects, such as
fault type, activation, and detection conditions. Based on the
various array structures in WOMs, a systematic method is
utilized to convert March-BOPCM to March-WOPCM. This
test algorithm is also equipped with the capability of detecting
potential intraword defects. Then a novel storage scheme of
fault information is introduced from different perspectives.
Combining the March-WOPCM and the storage scheme,
we develop a BIST-based test scheme for PCM. Finally,
experiments built in C-language are performed to evaluate the
performance of the proposed BIST scheme.
The remainder of this article is organized as follows. The
enhanced march test algorithm for bit-oriented PCM and the
converted algorithm for word-oriented PCM are introduced in
Section II and Section III, respectively; Section IV systemati-
cally introduces the concrete scheme of saving fault informa-
tion to FFR in tested memory. The overall structure of PCM
with BIST and the proposed test scheme are demonstrated
in Section V; the results of simulations built in C-language
and the analysis of BIST area are displayed in Section VI.
Section VII concludes this article.
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Fig. 1. Program operation of PCM.
II. E NHANCED M ARCH T EST A LGORITHM FOR BOM S
A. Program Method and Storage Array of PCM
A brief introduction to PCM technology could be helpful
to understand the specific faults mentioned in this article.
The basic concept in PCM starts with the chalcogenide
phase change materials (typical Ge2 Sb2 Te5 , GST) which can
transform between the two relatively stable phase (amorphous
and crystalline phase) by structural changes [13], [14]. The
amorphous phase shows high electrical resistivity, while the
crystalline phase exhibits that with three or four orders of
magnitude lower. The program operation from crystalline to
amorphous phase is called RESET which is accomplished with
a large electrical current pulse applied to the PCM cell. It is
noted that the RESET current pulse should have an abrupt
trailing edge so that the molten material quenches into an
amorphous phase. As for SET operation, a wider electrical
current pulse with lower amplitude is always used to heat
the material to its crystallization temperature until it becomes
crystalline phase. Fig. 1 displays the abovementioned program
operation. On the other hand, the analysis of any failure types
should be based on a certain understanding of the storage
array structure. Fig. 2 shows a typical storage array of PCM.
The memory cell can be modeled as a SELECTOR connected
with a variable resistance. The SELECTOR controlled by
word line (WL) can be a transistor, diode, bipolar, and other
switches, while the variable resistance represents the GST
materials. As depicted in Fig. 2, the memory cell surrounded
by a red circle is marked as victim cell (VC), and there are
other eight memory cells in its immediate proximity (first
neighbors) marked as A1–8 (Aggressor Cell 1–8). Seen from
the position relationship, this VC is most likely to be affected
by these eight aggressor cells.
B. Fault Models
The fault models used in this work are summarized
in Table I. They are basically proposed in [9] and the brief
introductions are as follows (It is noted that the subscript “m”
in fault notation represents the margin read operation explained
in Section II-C).
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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM
Fig. 2. Typical storage array of PCM.
TABLE I
FAULT M ODELS FOR PCM S
1) PD: This fault can be explained as the unintentional
loss of the data (RESET or “0”) in VC when a cell in
its immediate proximity is programmed to a RESET
state [8], [15]. It is modeled as an idempotent coupling
fault of the type xw0; 0/1m /−. This fault model is
given using traditional coupling fault notation Sa ;
Sv /F/R [16]: where Sa ∈ {0w0, 0w1, 1w0, 1w1} is the
operation sequence of the aggressor cell, “xw0” means
that the initial state of aggressor cell is not limited;
Sv ∈ {0, 1} is the operation sequence or initial state
of the VC; F ∈ {0, 1} is the state stored in the faulty
cell; R ∈ {0, 1, −} describes the logic output of a read
operation; and “−” is used in case a write operation is
utilized to sensitize the fault.
2) Read Recovery Disturb (RRD): A newly programmed
RESET cell could return to SET state because of an
immediate read operation [17]. This fault is modeled as
a dynamic incorrect read fault of the type 1w0r0/0/1m 
and the corresponding notation is S, F, R [16]: where
S ∈ {0w0r0, 0w1r1, 1w0r0, 1w1r1} is the initial state
and operation sequence of the VC; F ∈ {0, 1} and
R ∈ {0, 1, −}.
3) Read Disturb (RD): When reading a RESET cell,
the amount of current flowing through GST layer is
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3
Fig. 3. Syndrome of March-PCM.
increased because of the defects or cycling, resulting in
the switch from amorphous to crystalline state. In addi-
tion, this fault model assumes that the read operation
is short enough to read the true value before switch-
ing [18]. This fault is modeled as a deceptive RD fault
0r0/1m /0 and the fault notation is S/F/R [16] where
S ∈ {0r0, 0r1, 1r0, 1r1}, F ∈ {0, 1}, and R ∈ {0, 1, −}.
4) Fault Write (FWR): The read operation changes the
addressed cell from a SET state to a RESET state due
to the false activation of write driver. It can be viewed
as the complement of RD [19] and it is also modeled
as a deceptive RD fault 1r1/0/1 [16].
5) Stuck SET (SS): A faulty cell permanently keeps value
“1” because of overheating 18]. Since this type of fault
will not be detected unless the VC is programmed
to the RESET state at least once, it is modeled as a
transition fault ↓/1 [9].
6) Stuck RESET (SR): A faulty cell permanently keeps
value “0” because of extensive cycling [20], it is also
modeled as a transition fault ↑/0 [9].
7) Incomplete Program Fault (IPF0/1): A cell becomes a
less or more resistive state after a program operation
because of contaminants or variation [21], [22]. It is
modeled as a stuck-at fault ∀/1m  or ∀/0m  and the
fault notation is ∀/F: where “∀” symbolizes the
idea that for all operations the same value F ∈ {0,1}
remains in the VC.
C. Enhanced March Test Algorithm
Aiming at the abovementioned fault models,
Mohammad [9] has proposed a test algorithm March-PCM as
shown in Fig. 3. It follows the notation of the March algorithm,
where  denotes the arbitrary addressing sequence in a
linearly up-addressing sequence (⇑) or down-addressing
sequence (⇓), W0/W1 denotes the operation of RESET or
SET, R0/R1 denotes the read operation expecting “0” or “1,”
and Rm represents the margin read operation, which uses
different current references instead of the only reference used
in normal read operation, to detect PCM-specific faults [9].
The method used in March-PCM to activate and detect all
PD fault except for the last one is to apply RESET operation
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 4. Effect of march direction on PD fault coverage. (a) Up-addressing
sequence. (b) Down-addressing sequence.
to all memory cells in an arbitrary addressing sequence
and then execute read operation expecting value “0” in an
up-addressing sequence. However, this method is invalid in
some cases. As depicted in Fig. 2, there are eight aggressor
cells that may produce disturbs to the VC. In addition to
detect the PD fault, the VC must be initially in the RESET
state and activated by the RESET operation of neighboring
cell. As shown in Fig. 4(a), if RESET operation is applied
in up-addressing sequence at first, the state of VC cannot
be sure until it is programmed to RESET state. Even if the
initial state of VC is RESET and one of A1–A4 does have an
impact on it, the following W0 to VC will overwrite this fact.
Thus, the up-addressing read operation can only detect the
fault if it is caused by one of A5–A8. For the same reason,
as shown in Fig. 4(b), when the first march element M0 is
executed in down-addressing sequence, the influence from
A5–A8 cannot be detected at all by the following Rm 0 and the
rest operations in March-PCM. Thus, there are 50% PD faults
that cannot be detected by March-PCM in a probabilistic
sense.
Another problem is that the same read operation is responsi-
ble for detecting multiple fault types in March-PCM, resulting
in a fact that the faults can only be detected but not diagnosed
as the right types. This problem can be an advantage in some
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Fig. 5. Syndrome of March-BOPCM.
Fig. 6. Margin read reference currents.
case because it reduces the complexity of the test algorithm
and saves the test time. However, when we need to know the
exact type of the detected fault to analyze its origin or avoid it
by adjusting memory configuration, this problem could bring
much inconvenience.
Given the research above, this article proposes an enhanced
march test algorithm named March-BOPCM
March-BOPCM = {M1 :⇑ (W0, Rm 0, R0, Rm 0);
M2 :⇑ (Rm 0, W1, Rm 1, R1);
M3 :⇓ (W0 − Rm 0);
M4 :⇓ (Rm 0);}.
Fig. 5 summarizes the test algorithm March-BOPCM and
shows the test results of all kinds of fault memory cells. It also
follows the notation of march algorithm and another margin
read operation Rm 1 is adopted to detect IPF1 fault. To clearly
distinguish the two states of the PCM cell, the standard read
reference current IRef is generally set in the middle of two
currents conducted by typical RESET and SET cells, as shown
in Fig. 6. Margin read operations are designed to distinguish
the faulty cells from fault-free cells since some faulty cell’s
resistive value is marginally different than a typical cell.
Furthermore, considering the device-difference of PCM in
large-scale array, the margin read reference currents are always
set between the current conducted by typical cell and IRef .
The test conditions of March-BOPCM are listed in Table II.
PD fault is divided into two groups to test: The W0 in
M1 and W0 in M3 RESET all cell to “0,” PD1 (the address
of aggressor cell is larger than that of VC) is activated
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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM
TABLE II
T EST AND D IAGNOSIS C ONDITIONS OF M ARCH -BOPCM
by W0 (neighboring cells) in M1 and detected by the first
Rm 0 in M2, PD2 (the address of aggressor cell is smaller than
that of VC) is activated by W0 (neighboring cells) in M3 and
detected by Rm 0 in M4. In this way, all potential PD faults
can be detected regardless of the aggressor cells’ location.
IPF0 and IPF1 are activated by W0 in M1 and W1 in M2,
detected by Rm 0 in M1 and Rm 1 in M2, respectively. The
“W0-Rm 0” in M2 means an immediate read operation after
RESET to activate the RRD fault, and the Rm 0 in M3 is also
utilized to detect this kind of fault. The operation intervals
in other elements are set to be long enough for the stability
of phase change materials. All cells are initialized to RESET
state by W0 in M1, and RD is activated by the first Rm 0 or R0
in M1 and detected by the second Rm 0 in M1. W1 in M2
initializes all cells to SET state, and FWR is activated and
detected by Rm 1 and R1 in M2, respectively. SS and SR are
activated by W0 in M1 and W1 in M2, detected by R0 in
M1 and R1 in M2, respectively.
Besides, Table II presents the fault diagnosis conditions
of March-BOPCM in form of collection. To eliminate the
misdiagnosis case, some fault types are diagnosed based on
the composite outcomes of multiple detections. For instance,
IPF0, SS, and RD are diagnosed according to the detection
combination of {M1: Rm 0, R0, Rm 0}, IPF1, FWR, and SR are
diagnosed based on the detection combination of {M2: Rm 1,
R1}. As shown in Fig. 5, IPF0, IPF1, RD, FWR, SS, and SR
can be diagnosed as the corresponding fault type once they are
detected by following the abovementioned diagnosis method.
As for other faults, the detection is capable of detecting not
only the target fault type but also some other faults. Such as
RRD, its detection Rm 0 in M3 can also detect IPF0 and SS.
All fault information will be saved so that the correct type of
target fault can be determined by the method of exclusion.
The diagnosis conditions of these faults are indicated as
an expression of complement collection, X ∈ C{U } {A} =
{X | X ∈ U, X ∈ / A}, where “X” represents that target fault,
“U ” denotes the fault collection that can be detected by the
detection of “X,” and “A” denotes the collection of faults
misdiagnosed by the detection of “X.” It should be noted
that the key to determine the fault type by the exclusion
method is that the fault misdiagnosed by the same detection
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5
can be diagnosed by the other methods mentioned above. For
example, the misdiagnosis of IPF0 and SS by Rm 0 in M3 can
be diagnosed with the detection combination of {M1: Rm 0,
R0, Rm 0} instead.
The proposed enhanced test algorithm March-BOPCM cov-
ers all PD faults and every fault mentioned above can be
diagnosed correctly according to final fault information.
III. M ARCH T EST A LGORITHM FOR WOM S
A. Structure of Memory Array in WOMs
The internal structure of WOMs can be very different based
on various designs. Fig. 7 displays two kinds of internal
array arrangement of PCM. In general, the memory array is
always divided into many blocks to reduce the latency in WLs
and BLs. Each bit in one word comes from different block
in Fig. 7(a) and there is enough distance between blocks so that
the influence between them can be ignored. Fig. 7(b) shows
another case where every two bits of one word come from
the same selected block (there could be more than two bits
in one block in actual design). The bits in the same block
can also be organized in many different ways (depending on
where the bits of a word are physically located): 1) adjacent
and 2) interleaved. This article only discusses the adjacent case
since march tests for the interleaved case are a subset of the
adjacent case [23].
B. Fault Models in WOMs
For single-cell faults, such as RRD, RD, FWR, SS, SR, and
IPF0/1, there is no difference between BOMs and WOMs, thus
the established fault models are still valid. PD fault is classified
to interword fault since the aggressor and VCs belong to
different words. The test and diagnosis conditions of above
faults in WOPCM are the same as that in BOPCM, which is
shown in Table II. Besides, there are multiple bits in one word
being programmed simultaneously in WOMs and the influence
between them should be considered as intraword fault.
As for intraword fault in PCM, the original states of victim
and aggressor cells can be ignored, because what really
matter are the program operations applied on them. When
the coupling cells are both programmed to crystalline or
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 7. Different internal memory array arrangements. (a) Single bit in an array block. (b) Multiple bits in an array block.

amorphous state, the magnitude and duration of the current or

voltage pulses applied on them are all the same; consequently,
there is no interaction between them. However, when the
program operations of coupling cells are different and there
is heat diffusion caused by defects or improper isolation,
the interaction between coupling cells may lead the loss of
stored data. For example, in the case where the aggressor
cell is applied a SET operation while the VC is applied a
RESET operation, even if the RESET operation is completed,
the temperature of VC can hardly descend rapidly because the
SET time is longer than that of RESET. This situation may
cause the VC stores value “1” whereas it is supposed to be “0.”
This failure occurs due to the fact that newly programmed cell
is in a nonequilibrium state and additional time is required for
free carries to recombine/diffuse to restore equilibrium [17].
In conclusion, an intraword fault, named intraword proximity
disturb (IPD), is most likely to occur when the coupling cells Fig. 8. State diagram for sensitizing CFids (N = 2).
are applied different operations. Since the operation applied
to the VC is also limited by the activation condition, it is IPD fault may exist between any two bits. According to the
modeled as a subset of idempotent coupling fault. excitation and detection conditions discussed in Section III-B,
the IPD fault can only be detected when the coupling cells are
C. Diagnosis Algorithm for WOMs programmed to the opposite states. However, in the converted
In Fig. 7(a), each bit of the same word is organized in an march test algorithm mentioned above, all bits in one word
isolated array block which has enough space to eliminate the are applied the same program operation; thus, the IPD fault
influence from other blocks. In this circumstance, this kind of can never be detected with it.
WOMs have no IPD failure. Every block can be regarded as Since IPD failure is modeled as a subset of idempotent CFs
a small BOM, and the whole memory is actually a parallel (CFids), special DBS are required to cover this fault. There
connection of BOMs. Therefore, the march test algorithm of are four subtypes of CFids in an N-bit memory: ↑; ↓ ci ,
BOMs can be converted to that of WOMs by extending the c j , ↑; ↑ ci , c j , ↓; ↓ ci , c j , and ↓; ↑ ci , c j , where i ,
data background sequences (DBS). Assuming that each word j ∈ {0, 1, 2, …, N− 1}. “ci ” and “c j ” denote aggressor cell
contains n bits, the converted march test algorithm can be as and VC, respectively. “↑” and “↓” represent the transitions
follows: that take place on aggressor cell and VC. For example, ↑; ↓
M1: ⇑ (W0 . . . 0n , Rm 0 . . . 0n , R0 . . . 0n , Rm 0 . . . 0n ); c1, c0 means that the “↑” transition of aggressor cell “c1”
M2: ⇑ (Rm 0 . . . 0n , W1 . . . 1n , Rm 1 . . . 1n , R1 . . . 1n ); cause a different “↓” transition in VC “c0.” Each subtype has
CN2 = N ∗ (N − 1) possible cases where any of N cells can
M3: ⇓ (W0 . . . 0n − Rm 0 . . . 0n );
be the aggressor cell and any of other N − 1 nonaggressor
M4: ⇓ (Rm 0 . . . 0n ).
cell could be VC. Therefore, the total number of possible
As for cases like Fig. 7(b), several bits are arranged in one CFids is 4 ∗ N ∗ (N − 1). Fig. 8 shows the state diagram for
block or even the whole word is arranged in the same block, sensitizing CFids within a 2-bit WOM. To reduce the test time

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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM 7

Fig. 9. State diagram for sensitizing IPD (N = 2).

Fig. 10. Abstracted structure of FFR.

TABLE III
DBS S8 FOR AN 8-bit WOPCM
Level 3: The IPD between cell-pair (Ci , Ci+4 ) are
sensitized.
After the three-level test, all IPD for an 8-bit WOPCM can
be sensitized. Take the cell C7 as an example, according to
the fault detection condition described above, IPD fault occurs
when the aggressor and VCs are programmed to “1” and “0,”
respectively. Thus, the 1st, 3rd, and 5th DBS, where C7 is
operated to RESET state, are utilized to sensitize the intraword
disturb between C7 and other bits. To reduce the number of
unnecessary fault information, the diagnosis condition of each
and circuit overhead, the state diagram should be simplified
cell is the logic “or” of all detections concerned with the
as much as possible without decreasing the fault coverage.
target cell in the three levels. Hence, the diagnosis condition
After eliminating the duplicates and unnecessary cases where
of C7 (DC7 ) is described as “Rm 07 1 | Rm 07 3 | Rm 07 5 .”
IPD fault cannot be activated, the minimized state diagram is
The corresponding diagnosis conditions for other cells are
displayed in Fig. 9. The DBS for a 2-bit WOM is S2 = 01, 10.
listed in the last column of Table IV.
Then extend this DBS to 8-bit word length according to the
Since the IPD fault does not exist in every PCM, the march
steps in [23]. Finally, the DBS S8 for an 8-bit WOM is shown
element M5, which consumes half test length, is designed to
in Table III with three levels included. Herein, we just take
be optional according the actual situation.
the 8-bit WOMs as an example to demonstrate the converting
process, the method used above can be generalized for N-bit
WOMs. Combined with the above algorithm, the converted IV. S TORAGE S CHEME FOR FAULT I NFORMATION
march test algorithm for 8-bit WOMs with intraword faults Conventional memory BIST usually outputs the fault infor-
can be as follows: mation to the external CAMs for storage, which increases not
only the test time but also the cost. To completely get rid of
March-WOPCM: the external devices and reduce extra area overhead, a specific
M1: ⇑ (W 0000_0000, Rm 0000_0000, scheme is devised to store fault information in an FFR of the
R0000_0000, Rm 0000_0000) memory chip which is under test. When the test is completed,
this region can be released and used normally. To achieve this
M2: ⇑ (Rm 0000_0000, W 1111_1111,
scheme, three aspects need to be considered: storage structure
Rm 1111_1111, R1111_1111) of fault information, algorithm for finding FFR, and capacity
M3: ⇓ (W 0000_0000 − Rm 0000_0000) of FFR.
M4: ⇓ (Rm 0000_0000)
M5: ⇑ (W 0101_0101, Rm 0101_0101, A. Storage Structure of FFR
W 1010_1010, Rm 1010_1010, For better understanding, the FFR is abstracted as a stack
W 0011_0011, Rm 0011_0011, consisting of sequential memory groups as shown in Fig. 10.
Every piece of fault information is stored in one memory
W 1100_1100, Rm 1100_1100, group, and the size of which depends on the length of the infor-
W 0000_1111, Rm 0000_1111, mation. Each fault information includes two aspects: fault type
W 1111_0000, Rm 1111_0000). (3 bits, 0–7, corresponding to the eight fault types mentioned
in this article) and fault address (Log2 M bits, M denotes
Test and diagnosis conditions of IPD are summarized the maximum address). To adapt the storage structure of
in Table IV. According to the DBS, test condition is divided fault information to different word lengths and capacities,
into three levels. Fig. 10 shows two types of memory group. In type I, each
Level 1: The IPD between cell-pair (Ci , Ci+1+2∗k ) are group comprises one word where fault type is stored in
sensitized, where k ∈ {0, 1, 2, 3}. the first three bits and the fault address is stored in the
Level 2: The IPD between cell-pair (Ci , Ci+2+4∗k ) are rest bits. The group of type II comprises two words where
sensitized, where k ∈ {0, 1}. fault address is extended in the added word to adapt larger

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TABLE IV
T EST AND D IAGNOSIS C ONDITIONS OF IPD

Fig. 11. (a) Address sequence of March-WOPCM for finding FFR. (b) FFR and the extended region for edge fault activation.

TABLE V free from any of failures mentioned in this article. Therefore,

M EMORY C APACITY L IMITATION OF T WO D IFFERENT M EMORY G ROUPS
capacity. Table V illustrates the memory capacity limitations
of two different memory groups. The fault information can be
recorded correctly only if the capacity of the tested chip is
within this range. From Table V, we can see that two kinds
of storage structure of fault information cover most of the
memory capacity in practical applications. In some specific
design, the storage structure and the memory group can be
selected flexibly based on several composite factors: actual
capacity, word length, forecasting yield, etc.
B. Algorithm for Finding FFR
For the accuracy of fault information, the designated region,
which is used to store fault information during the test, must be
the algorithm for finding FFR is based on March-WOPCM
devised in Section III. The only difference is the address
sequence required for testing.
To begin with, the capacity or address length of FFR is
determined by the configuration. Then starting from the initial
address MIN, the test algorithm March-WOPCM is utilized
to test a memory region with equal address length as FFR,
shown in Fig. 11(a). During the process of finding FFR, it is
not necessary to store the fault information. If there is a fault
detected, the defective cell will be skipped and the next address
will be set as the new start point of FFR. Until a consecutive
FFR with predefined address length is found. Finally, only the
addresses of start and endpoint are recorded in special registers
to indicate where the fault information will be stored. When
the March-WOPCM is used to test an entire memory chip,
the address sequence is generated to cover all memory cells
without considering the special situation of edge memory
cells. However, the FFR is selected from the memory array
by testing. Its address sequence is only a part of the whole

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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM
address, and some special fault activation of edge cells needs
to be concerned. Fig. 11(b) shows an example indicating the
location of the FFR and the extended region for edge fault
activation. To ensure that the interword faults of all edge cells
can also be detected and the detection of faulty cells will
not be affected by the storing operations in FFR, M1(W0),
M2(Rm 0), M3(W0), and M4 in March-WOPCM must extend
their address range. As shown in Fig. 11(b), except in the
FFR, the extended region for fault activation includes all the
first neighboring cells of the edge FFR cells.
Based on this, the concrete process of finding FFR is
displayed in Fig. 11(a). First, starting from the initial address
MIN, a memory region with equal address length as FFR is
picked from the whole memory array. Then, the test algorithm
March-WOPCM is utilized to test the picked region and the
initial address MIN is recorded as the start point, which
is marked as “a1.” In addition, the endpoint is recorded at
the end of M1. If any fault is detected during this process,
the start point will be changed to the next address. Another
equal-length region will be tested and the endpoint will be
modified correspondingly. Then by following the rules of
address extension mentioned above, the address range of
M1(W0), M2(Rm 0), M3(W0) and M4 are extended to “start
point − m” and “endpoint + m,” where “‘m’ = the row
number of the array + 1.” Finally, the FFR is found when all
four (or five) march elements are executed without any fault
detected. The start and endpoint, which are marked as a4 and
b4 ultimately in Fig. 11(a), are stored in specific registers.
C. Capacity of FFR
In the conventional Memory BIST scheme, extra memories
are reserved to ensure that all fault information can be recorded
correctly, which inevitably results in large area overhead.
In this article, the scheme of saving fault information to the
FFR of the tested memory can completely omit the external
memories. Thus, there is a key factor determining the success
of this scheme: capacity setting of the FFR. It is certain that
the scheme is more likely to be valid with a larger capacity,
while a continuous FFR with such large capacity may not
exist in the tested memory. The following content will explain
how to improve the success rate of the proposed scheme by
reasonably setting capacity of the FFR.
To begin with, the conditions to guarantee that the proposed
scheme is valid are as follows.
1) There is a continuous FFR with predefined capacity in
the tested memory.
2) The amount of memory groups is greater than that of
fault information.
The first condition can be always achieved by adjusting the
configuration parameters. In addition, the core problem of
the second condition is the amount of fault information. It usu-
ally does not equal the number of faults, since the same fault
may be detected by multiple elements in March test. As the
March-WOPCM proposed in this article, the SS fault can be
detected by each read operation expecting “0.” Considering the
composite diagnosis mentioned in Section II, each SS fault
generates five pieces of fault information through detection,
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9
TABLE VI
P ROBABILITY OF F INDING THE FFR IN A 32-kb WOM
which is also the most extreme case in March-WOPCM.
Hence, the proposed scheme is 100% valid when the number
of memory groups is five times the number of faults in theory.
In most cases, however, the actual number of memory groups
required is less than that. Herein, a formula is introduced
to explain the relation between the capacity of FFR and the
number of faults
FFR capacity = C × N × P.
“C” is the capacity coefficient of FFR, it represents the ratio
of the number of memory groups over the number of faults.
“N” is the number of faults. “P” is the product of word length
and the number of words included in a memory group; it is a
fixed value once the tested memory is determined. Since the
type and number of faults in different memories are random,
the capacity of FFR can be modified by adjusting coefficient
“C” to achieve the conditions mentioned above.
Second, a 32-kb, 8-bit word length PCM with the proposed
scheme in this article is built in C-language. It is utilized
to study the probability of finding the predefined FFR in
different cases. For the universality and randomness of the
experiment, a large number of experiments are performed with
conditions that are permitted, and the type and location of
faults in each experiment is set randomly. Each memory group
contains two words according to Table V, and the “P” is
fixed as 16. Table VI shows the probabilities in 20 different
cases, each data are the average of 10 000 experiment results
under corresponding combinations. When the number of faults
is small, the ideal FFR (the number of memory groups is
five times fault amount) basically exists, and the probability
increases with the increase of FFR capacity. With the increase
of fault amount, the existing probability of FFR gradually
decreases. What is more, the maximum probability of finding
the predefined FFR moves to the section where 3<“C”<4.
This phenomenon is more obvious in Fig. 12(a) and (b),
which are the colormap surface and contour of the probability.
Fig. 12(b) shows that when the number of faults exceeds 35,
the ideal FFR does not necessarily exist. But the proposed
scheme can still achieve a high success rate by adjusting
coefficient “C” to modify the capacity of FFR.
V. OVERALL A RCHITECTURE OF
PCM W ITH BIST S CHEME
After considering the various aspects, including the
enhanced march test algorithm for BOPCMs, the converted
algorithms for WOPCMs with different array structures,
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10
Fig. 12. Probability of finding the predefined FFR. (a) Colormap surface.
(b) Contour.
Fig. 13. Block diagram of PCM with the proposed BIST.
and the FFR for fault information, a BIST-based test scheme
is developed for WOPCMs.
Fig. 13 shows the block diagram of PCM with the proposed
BIST, assuming that the maximum address is “M” and the
word length is “N.” It is just for a better understanding of
the connection between them to separate BIST apart from
PCM. In fact, all BIST modules are integrated into the PCM
chip. As illustrated in Fig. 13, under the control of signal
User_Mode, the PCM is divided into two parts in terms of
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 14. Block diagram of the proposed BIST architecture.
working modes (normal working mode and test mode) and
signal sources (CE, WE, OE, ADDR, etc. It is an example of
PCM chip with SRAM interface. There are special read–write
control and driver modules inside the PCM chip, which can
convert external CE, WE, and OE signals to control signals
of RESET, SET, and READ.): Under normal working state,
the control signals (CE_E, WE_E, and OE_E) and address
signal (ADDR_E) of PCM come from the external interfaces,
performing conventional reading and writing function; When
the PCM is in test state, its control signals (CE_I, WE_I,
and OE_I) and address signal (ADDR_I) are generated by
BIST module. The data exchange is completed by a group of
time-sharing data bus.
Fig. 14 shows the block diagram of the proposed BIST
architecture. The BIST module mainly consists of a finite
state machine (FSM), a fault information processor, and a test
pattern generator (TPG). The external parameters (PARAs)
are input to the configuration registers (CFG REGs) and
modify the parameters such as the capacity of FFR. The CLK
frequency multiplier can convert the input clock signal into
multifrequency clock signals and drive different modules. The
overall test procedure is controlled by the FSM of BIST, and
there is an FSM of March responsible for the test program
executed by each march element. TPG is composed of control
signal generator (CSG), test address generator (TAG), and test
vectors generator (TVG), and it can automatically generate
address signals, test vectors, read/write signals under the con-
trol of FSM and CLK. Furthermore, after processing, the fault
information, the number of detected faults, and the location
of FFR are temporarily stored in the corresponding registers
until the whole test procedure is completed.
The FFR needs to be found every time before the BIST
starts since the number and location of faults may change
over time. In this way, the fault information can be accurately
preserved without any extra devices. Therefore, the algorithm
for finding FFR is combined with the March-WOPCM pro-
posed in Section III to form the final test scheme for PCM.
The flowchart of the final algorithm is displayed in Fig. 15.
Started with the signal User_mode, the PCM is switched from
normal working mode to the test mode. The PCM is tested
from the initial address to find an FFR with the predefined
capacity. Once the FFR is found, the main test procedure will
get started from the initial address again. A key point here
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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM
TABLE VII
P ERFORMANCE C OMPARISON B ETWEEN M ARCH -PCM AND M ARCH -BOPCM IN AN 8-kb B IT-O RIENTED PCM M ODEL
Fig. 15. Flowchart of the proposed BIST scheme.
is that the developed algorithm must skip the FFR which has
been tested already to ensure the saved fault information will
not be covered. When there is a fault detected, the march
is suspended temporarily and the fault information is written
to FFR. The only case which leads to a failure of the test
scheme is that all FFR is fulfilled while there is another fault
detected. In this case, the BIST module will output a signal to
inform of the failure, but the stored fault information can still
be accessed. To get the complete information, the capacity of
FFR has to be modified according the conclusion in Section IV.
When the test is finished successfully, the start point of FFR
will be sent to the output ports to inform the location where
fault information is saved.
VI. E XPERIMENTAL R ESULTS
To numerically estimate the performance of the proposed
BIST-based test scheme for PCM, we build a test simu-
lation environment in C-language. It is composed of three
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11
Fig. 16. Percentage of BIST area changes with different array sizes.
major projects. The first one is utilized to assess the per-
formance improvement of the March-BOPCM for an 8-kb
word-oriented PCM. The second project is about the probabil-
ity of finding the predefined FFR and it has been introduced
in Section IV. The test procedure combining the FFR finding
algorithm and March-WOPCM is simulated in the last project.
The type and address of the faults injected to the PCM
in every experiment are determined by the peruse-random
sequence generated from rand (). Furthermore, some perfor-
mance indexes are introduced to get a better understanding of
the experiment results. Fault coverage indicates the percentage
of the detected faults to the actual number. It only means
that the fault can be detected but not necessarily diagnosed
correctly. Immediate identification is the accuracy that the
fault can be diagnosed as the correct type immediately after
it is detected. Final diagnosis indicates the accuracy that the
detected fault can be correctly diagnosed according the final
result. Test length reflects the complexity and the time cost
of the test algorithm, where “W ” and “R” represent the write
and read operation, respectively, “N” denotes the number of
address.
Table VII shows the performance comparison between
March-PCM and March-BOPCM in an 8-kb bit-oriented PCM
model. The number of faults is set to 16, and the type
and the address are generated randomly. After 10 000 trials,
the performance indexes of each fault type are concluded
in Table VII. As mentioned in Section II, 50% of the PD
faults cannot be detected by March-PCM due to the principle
of algorithm. This point is also confirmed by the results of
experiments. The enhanced algorithm March-BOPCM solves
the problem and achieves 100% coverage of each fault type.
In terms of fault diagnosis, there is only one kind of fault that
can achieve 100% immediate identification in March-PCM.
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12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE VIII
P ERFORMANCE S UMMARY OF THE BIST-BASED S CHEME W ITH FFR F INDING A LGORITHM

TABLE IX
C OMPARISON B ETWEEN THE P ROPOSED T EST A LGORITHM AND T HOSE IN [8]–[11]

Even if the final fault information is taken into account, only
SR fault and FWR fault can be diagnosed as the correct type.
In contrast, for most fault types, the immediate identification
of March-BOPCM can reach 100%. And all detected faults
can be diagnosed as the corresponding type according to the
final results. Finally, the cost of improving fault coverage and
diagnostic accuracy is that the test length increases within an
acceptable range.
As for word-oriented PCM, a 32-kb PCM model with 8-bit
word length is built in C-language. The number of predefined
faults is set to 32 in each experiment, with randomly generated
type and address. After 10 000 trials, Table VIII shows the
performance summary of the BIST-based scheme with FFR
finding algorithm. Including the IPD fault, the fault coverage
and diagnostic accuracy can still achieve 100% with March-
WOPCM. Due to the addition of march element M5 for IPD
detection, the test length of the entire algorithm becomes
much larger. However, as mentioned in Section II, M5 is an
optional march element. It can be skipped through parameters
configuration if there is no IPD fault in the tested memory.
Hence the test length in Table VIII indicates the worst case.
Due to the design of storing fault information to the FFR in
tested memory, the proposed test scheme saves the external
memory which is essential in conventional test. 2.56 kb is just
the ideal capacity needed in this case, these data will increase
with the fault amount and the capacity of the tested memory.
In addition, except for the reduction of area overhead, the test
time is saved by avoiding data exchange between different
memories, which is not included in Table VIII.
Table IX compares the test algorithms proposed in this
article with other test algorithms for PCM based on fault
coverage, functions of detection and diagnosis, and test length.
It should be noted that the time consumed by program opera-
tion is much longer than that of read operation, hence the test
length is mainly decided by the coefficient of “W .” As we
can see, all kinds of faults in BOPCM shown in Table IX can
be tested effectively by March-BOPCM with acceptable test
length. Although the test length of March-WOPCM is higher
than that of other algorithms, it extends the fault coverage
capability to WOPCM. In addition, unlike other algorithms
where the faults can only be detected, the two test algorithms
proposed in this article can not only detect the faults but also
diagnose them as the correct fault types.
Since the whole BIST architecture is integrated into
memory, the area overhead should be concerned. Fig. 16 shows
the percentage of BIST area changes with the different array
sizes, where abscissa is the logarithm (log2 capacity) of
array capacity. The BIST circuits are realized by Verilog
Hardware Description Language (HDL) and synthesized by
design compiler using SMIC CMOS standard cell libraries
of 40 nm, which correspond to the target PCMs. For the
objectivity of experiment results, only the area of PCM arrays
and the indispensable address decoders are included to the
calculation. As shown in Fig. 16, the percentage of BIST
area decreases exponentially with the increase of array size.
The percentage of BIST area is less than 2% when the array
size reaches 6 Mb. This area overhead can be ignored in the
memory with larger capacity.

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XIE et al.: BIST-BASED FAULT DIAGNOSIS FOR PCM
VII. C ONCLUSION
To solve the problems of high cost and low efficiency in
testing PCMs, this article proposed a BIST-based test scheme.
The main contents involve primarily the following aspects:
an enhanced march test algorithm for bit-oriented PCM,
a converted march test algorithm for word-oriented PCM,
and a BIST-based test scheme with FFR finding algorithm.
The proposed March-BOPCM enhances the detection of PD
faults and achieves 100% diagnostic accuracy for all fault
types. The converted March-WOPCM not only retains the
original detection capabilities, but also adds the detection of
potential IPD faults for word-oriented PCM with different
array structures. Furthermore, a novel storage scheme based
on March-WOPCM is proposed to find a continuous FFR in
tested memory for the storage of detected fault information.
Through the modeling and simulation experiments in
C-language, we study the approach to improve the probability
of finding the predefined FFR. Finally, combining the
enhanced detection of PD fault and FFR finding algorithm, a
BIST-based test scheme for PCM is proposed to completely
break away the constraint from the external devices.
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